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stm32h7: Implement setup packet events.
This commit is contained in:
William D. Jones
parent
8b165e1024
commit
f602534536
@ -35,6 +35,100 @@
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t _setup_offs; // We store up to 3 setup packets.
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typedef struct {
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uint8_t * buffer;
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_size;
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bool short_packet;
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} xfer_ctl_t;
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xfer_ctl_t xfer_status[4][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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// Setup the control endpoint 0.
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static void bus_reset(void)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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for(int n = 0; n < 4; n++)
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{
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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}
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dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
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dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
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// Peripheral FIFO architecture (Rev6 RM 56.11.1)
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//
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// --------------- 1024 ( 4096 bytes )
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// | IN FIFO 7 |
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// ---------------
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// | ... |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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// --------------- x + 16 + GRXFSIZ
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// | IN FIFO 1 |
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// --------------- 16 + GRXFSIZ
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// | IN FIFO 0 |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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// --------------- 0
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//
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// FIFO sizes are set up by the following rules (each word 32-bits):
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// All EP OUT shared a unique OUT FIFO which uses (based on page 2747 of Rev 6 of reference manual):
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// * 10 locations in hardware for setup packets + setup control words
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// (up to 3 setup packets).
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// * 2 locations for OUT endpoint control words.
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// * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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// * 1 location for global NAK (not required/used here).
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//
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// It is recommended to allocate 2 times the largest packet size, therefore
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// Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
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USB2_OTG_FS->GRXFSIZ = 50;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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USB2_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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}
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static void end_of_reset(void)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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// On current silicon on the Full Speed core, speed is fixed to Full Speed.
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// However, keep for debugging and in case Low Speed is ever supported.
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uint32_t enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
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// Maximum packet size for EP 0 is set for both directions by writing
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// DIEPCTL.
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if(enum_spd == 0x03) {
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// 64 bytes
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in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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xfer_status[0][TUSB_DIR_OUT].max_size = 64;
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xfer_status[0][TUSB_DIR_IN].max_size = 64;
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} else {
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// 8 bytes
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in_ep[0].DIEPCTL |= (0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
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xfer_status[0][TUSB_DIR_OUT].max_size = 8;
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xfer_status[0][TUSB_DIR_IN].max_size = 8;
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}
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}
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/*------------------------------------------------------------------*/
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/* Controller API
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@ -148,9 +242,87 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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/*------------------------------------------------------------------*/
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static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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uint32_t * rx_fifo = FIFO_BASE(0);
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// Pop control word off FIFO (completed xfers will have 2 control words,
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// we only pop one ctl word each interrupt).
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uint32_t ctl_word = USB2_OTG_FS->GRXSTSP;
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uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
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uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos;
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uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
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(void) bcnt;
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switch(pktsts) {
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case 0x01: // Global OUT NAK (Interrupt)
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break;
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case 0x02: // Out packet recvd
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break;
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case 0x03: // Out packet done (Interrupt)
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break;
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case 0x04: // Setup packet done (Interrupt)
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_setup_offs = 2 - ((out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_STUPCNT_Msk) >> USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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break;
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case 0x06: // Setup packet recvd
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{
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uint8_t setup_left = ((out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_STUPCNT_Msk) >> USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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// We can receive up to three setup packets in succession, but
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// only the last one is valid.
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_setup_packet[4 - 2*setup_left] = (* rx_fifo);
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_setup_packet[5 - 2*setup_left] = (* rx_fifo);
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}
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break;
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default: // Invalid, do something here, like breakpoint?
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TU_BREAKPOINT();
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break;
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}
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}
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static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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// DAINT for a given EP clears when DOEPINTx is cleared.
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// OEPINT will be cleared when DAINT's out bits are cleared.
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for(int n = 0; n < 4; n++) {
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if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
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// SETUP packet Setup Phase done.
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if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
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out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP;
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dcd_event_setup_received(0, (uint8_t*) &_setup_packet[2*_setup_offs], true);
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_setup_offs = 0;
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}
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}
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}
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}
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void OTG_FS_IRQHandler (void)
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{
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTMSK_USBRST)
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{
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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bus_reset();
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}
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if(int_status & USB_OTG_GINTMSK_ENUMDNEM)
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{
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTMSK_ENUMDNEM;
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end_of_reset();
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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}
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if(int_status & USB_OTG_GINTSTS_RXFLVL) {
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read_rx_fifo(out_ep);
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}
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// OUT endpoint interrupt handling.
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if(int_status & USB_OTG_GINTSTS_OEPINT) {
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handle_epout_ints(dev, out_ep);
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}
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}
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#endif
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