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stm32f4: Refactor RX FIFO read into its own function; remove RXFLVL

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resetting (read only) and masking (no nested ints).
This commit is contained in:
William D. Jones 2019-02-27 10:39:37 -05:00
parent c51b11f103
commit f43161353c
1 changed files with 42 additions and 44 deletions
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64
src/portable/st/stm32f4/dcd_stm32f4.c
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@ -512,40 +512,9 @@ static void transmit_packet(xfer_ctl_t * xfer, USB_OTG_INEndpointTypeDef * in_ep
}
}
void OTG_FS_IRQHandler(void) {
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
uint32_t * rx_fifo = FIFO_BASE(0);
uint32_t int_status = USB_OTG_FS->GINTSTS;
if(int_status & USB_OTG_GINTSTS_USBRST) {
// USBRST is start of reset.
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
bus_reset();
}
if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
// ENUMDNE detects speed of the link. For full-speed, we
// always expect the same value. This interrupt is considered
// the end of reset.
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
end_of_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if(int_status & USB_OTG_GINTSTS_SOF) {
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
if(int_status & USB_OTG_GINTSTS_RXFLVL) {
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_RXFLVL;
// Receive data before reenabling interrupts.
USB_OTG_FS->GINTMSK &= (~USB_OTG_GINTMSK_RXFLVLM);
// Pop control word off FIFO (completed xfers will have 2 control words,
// we only pop one ctl word each interrupt).
uint32_t ctl_word = USB_OTG_FS->GRXSTSP;
@ -582,8 +551,37 @@ void OTG_FS_IRQHandler(void) {
default: // Invalid, do something here, like breakpoint?
break;
}
}
USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
void OTG_FS_IRQHandler(void) {
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
uint32_t int_status = USB_OTG_FS->GINTSTS;
if(int_status & USB_OTG_GINTSTS_USBRST) {
// USBRST is start of reset.
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
bus_reset();
}
if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
// ENUMDNE detects speed of the link. For full-speed, we
// always expect the same value. This interrupt is considered
// the end of reset.
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
end_of_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if(int_status & USB_OTG_GINTSTS_SOF) {
USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
if(int_status & USB_OTG_GINTSTS_RXFLVL) {
read_rx_fifo(out_ep);
}
// OUT endpoint interrupt handling.