mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-27 11:37:17 +00:00
update ra type to include usbhs registers
This commit is contained in:
hathach
parent
4f4c93594d
commit
f308435b64
@ -120,7 +120,6 @@ function(family_configure_example TARGET RTOS)
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
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${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
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${TOP}/src/portable/renesas/rusb2/rusb2_ra.c
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)
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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@ -18,7 +18,6 @@ CFLAGS += \
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SRC_C += \
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src/portable/renesas/rusb2/dcd_rusb2.c \
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src/portable/renesas/rusb2/hcd_rusb2.c \
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src/portable/renesas/rusb2/rusb2_ra.c \
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$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
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$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
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$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
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@ -1,16 +0,0 @@
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#include "tusb_option.h"
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#include "rusb2_ra.h"
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#if (CFG_TUSB_RHPORT0_MODE != 0)
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IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
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void tud_set_irq_usbfs(IRQn_Type q) {
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_usb_fs_irqn = q;
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}
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#endif
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#if (CFG_TUSB_RHPORT1_MODE != 0)
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IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
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void tud_set_irq_usbhs(IRQn_Type q) {
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_usb_hs_irqn = q;
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}
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#endif
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@ -47,55 +47,53 @@ extern "C" {
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#pragma GCC diagnostic pop
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#endif
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extern IRQn_Type _usb_fs_irqn;
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extern IRQn_Type _usb_hs_irqn;
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#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
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// fallback
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#define CFG_TUSB_RHPORT0_MODE ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
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#define CFG_TUSB_RHPORT1_MODE 0
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#endif
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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// IAR does not have __builtin_ctz
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#if defined(__ICCARM__)
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#define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x))
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#define __builtin_ctz(x) __iar_builtin_CLZ(__iar_builtin_RBIT(x))
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#endif
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typedef struct {
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uint32_t reg_base;
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int32_t irqnum;
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}rusb2_controller_t;
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#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
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#define RUSB2_HAS_HIGHSPEED
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#define RUSB2_CONTROLLER_COUNT 2
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#else
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#define RUSB2_CONTROLLER_COUNT 1
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#endif
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// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
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static rusb2_controller_t rusb2_controller[] = {
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{ .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
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#ifdef RUSB2_HAS_HIGHSPEED
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{ .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
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#endif
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};
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TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
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{
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#ifdef CFG_TUSB_RHPORT1_MODE
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#if (CFG_TUSB_RHPORT1_MODE != 0)
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if (rhport == 1) {
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NVIC_EnableIRQ(_usb_hs_irqn);
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}
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#endif
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#endif
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#ifdef CFG_TUSB_RHPORT0_MODE
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#if (CFG_TUSB_RHPORT0_MODE != 0)
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if (rhport == 0) {
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NVIC_EnableIRQ(_usb_fs_irqn);
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}
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#endif
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#endif
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#if RUSB2_CONTROLLER_COUNT > 1
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NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
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#else
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(void) rhport;
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NVIC_EnableIRQ(rusb2_controller[0].irqnum);
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#endif
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}
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TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
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{
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#ifdef CFG_TUSB_RHPORT1_MODE
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#if (CFG_TUSB_RHPORT1_MODE != 0)
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if (rhport == 1) {
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NVIC_DisableIRQ(_usb_hs_irqn);
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}
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#endif
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#endif
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#ifdef CFG_TUSB_RHPORT0_MODE
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#if (CFG_TUSB_RHPORT0_MODE != 0)
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if (rhport == 0) {
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NVIC_DisableIRQ(_usb_fs_irqn);
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}
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#endif
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#endif
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#if RUSB2_CONTROLLER_COUNT > 1
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NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
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#else
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(void) rhport;
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NVIC_DisableIRQ(rusb2_controller[0].irqnum);
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#endif
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}
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// MCU specific PHY init
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@ -103,6 +101,15 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
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{
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}
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void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
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#if RUSB2_CONTROLLER_COUNT > 1
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rusb2_controller[rhport].irqnum = irqnum;
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#else
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(void) rhport;
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rusb2_controller[0].irqnum = irqnum;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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@ -46,10 +46,10 @@ typedef struct {
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volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
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struct TU_ATTR_PACKED {
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uint16_t : 8;
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uint16_t : 8;
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volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
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volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
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uint16_t : 6;
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uint16_t : 6;
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} E_b;
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};
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@ -62,7 +62,8 @@ typedef struct {
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};
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} RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
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/* LINK_REG Structure */
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/* RUSB2 Registers Structure */
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typedef struct {
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union {
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volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
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@ -74,7 +75,7 @@ typedef struct {
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volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
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volatile uint16_t DRPD : 1; /* [5..5] D+/D- Line Resistor Control */
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volatile uint16_t DCFM : 1; /* [6..6] Controller Function Select */
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uint16_t : 1;
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volatile uint16_t HSE : 1; // [7..7] High-Speed Operation Enable
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volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
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uint16_t : 1;
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volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
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@ -87,7 +88,7 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
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uint16_t : 12;
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uint16_t : 12;
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} BUSWAIT_b;
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};
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@ -98,8 +99,7 @@ typedef struct {
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volatile const uint16_t LNST : 2; /* [1..0] USB Data Line Status Monitor */
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volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
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uint16_t : 2;
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volatile const uint16_t
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SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
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volatile const uint16_t SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
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volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
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uint16_t : 7;
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volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
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@ -111,7 +111,7 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
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uint16_t : 15;
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uint16_t : 15;
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} PLLSTA_b;
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};
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@ -139,7 +139,7 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile uint16_t UTST : 4; /* [3..0] Test Mode */
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uint16_t : 12;
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uint16_t : 12;
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} TESTMODE_b;
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};
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volatile const uint16_t RESERVED1;
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@ -295,7 +295,7 @@ typedef struct {
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volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
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struct TU_ATTR_PACKED {
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uint16_t : 8;
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uint16_t : 8;
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volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
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volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
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volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
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@ -316,7 +316,10 @@ typedef struct {
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volatile uint16_t SACKE : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
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volatile uint16_t SIGNE : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
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volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
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uint16_t : 4;
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uint16_t : 1;
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volatile uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */
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volatile uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */
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uint16_t : 1;
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volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
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volatile uint16_t DTCHE : 1; /* [12..12] Disconnection Detection Interrupt Enable */
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uint16_t : 1;
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@ -340,7 +343,7 @@ typedef struct {
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volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
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volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
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volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} BRDYENB_b;
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};
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@ -358,7 +361,7 @@ typedef struct {
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volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
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volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
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volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} NRDYENB_b;
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};
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@ -376,7 +379,7 @@ typedef struct {
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volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
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volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
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volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} BEMPENB_b;
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};
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@ -390,7 +393,7 @@ typedef struct {
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volatile uint16_t BRDYM : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
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uint16_t : 1;
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volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
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uint16_t : 7;
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uint16_t : 7;
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} SOFCFG_b;
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};
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@ -467,7 +470,7 @@ typedef struct {
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volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
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volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
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volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} BRDYSTS_b;
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};
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@ -485,7 +488,7 @@ typedef struct {
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volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
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volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
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volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} NRDYSTS_b;
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};
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@ -503,7 +506,7 @@ typedef struct {
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volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
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volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
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volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
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uint16_t : 6;
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uint16_t : 6;
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} BEMPSTS_b;
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};
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@ -609,7 +612,8 @@ typedef struct {
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volatile uint16_t SQCLR : 1; /* [8..8] Sequence Toggle Bit Clear */
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uint16_t : 2;
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volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
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uint16_t : 2;
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volatile uint16_t CSSTS : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */
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volatile uint16_t CSCLR : 1; /* [13..13] Split Transaction CSPLIT Status Clear */
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volatile uint16_t SUREQ : 1; /* [14..14] Setup Token Transmission */
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volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
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} DCPCTR_b;
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@ -621,7 +625,7 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
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uint16_t : 12;
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uint16_t : 12;
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} PIPESEL_b;
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};
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volatile const uint16_t RESERVED11;
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@ -634,21 +638,31 @@ typedef struct {
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volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
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uint16_t : 2;
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volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
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uint16_t : 1;
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volatile uint16_t CNTMD : 1; /* [8..8] Continuous Transfer Mode */
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volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
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volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
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uint16_t : 3;
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volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
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} PIPECFG_b;
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};
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volatile const uint16_t RESERVED12;
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union {
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volatile uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */
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struct {
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volatile uint16_t BUFNMB : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h)
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uint16_t : 2;
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volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */
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uint16_t : 1;
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} PIPEBUF_b;
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};
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union {
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volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
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struct TU_ATTR_PACKED {
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volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
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uint16_t : 3;
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volatile uint16_t MXPS : 11; /* [10..0] Maximum Packet Size */
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uint16_t : 1;
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volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
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} PIPEMAXP_b;
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};
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@ -694,11 +708,9 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile uint16_t RPDME0 : 1; /* [0..0] D- Pin Pull-Down Control */
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volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
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volatile uint16_t
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IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
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volatile uint16_t IDMSINKE0 : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
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volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
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volatile uint16_t
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IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
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volatile uint16_t IDPSINKE0 : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
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volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
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uint16_t : 1;
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volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
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@ -715,7 +727,7 @@ typedef struct {
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struct TU_ATTR_PACKED {
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volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
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uint16_t : 15;
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uint16_t : 15;
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} UCKSEL_b;
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};
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volatile const uint16_t RESERVED18;
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@ -737,11 +749,11 @@ typedef struct {
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volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
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struct TU_ATTR_PACKED {
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uint16_t : 6;
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uint16_t : 6;
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volatile uint16_t USBSPD : 2; /* [7..6] Transfer Speed of Communication Target Device */
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volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
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volatile uint16_t UPPHUB : 4; /* [14..11] Communication Target Connecting Hub Register */
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uint16_t : 1;
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uint16_t : 1;
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} DEVADD_b[10];
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};
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volatile const uint32_t RESERVED21[3];
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@ -754,7 +766,7 @@ typedef struct {
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volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
|
||||
volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
|
||||
volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
|
||||
uint32_t : 28;
|
||||
uint32_t : 28;
|
||||
} PHYSLEW_b;
|
||||
};
|
||||
volatile const uint32_t RESERVED22[3];
|
||||
@ -763,9 +775,9 @@ typedef struct {
|
||||
volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
|
||||
|
||||
struct TU_ATTR_PACKED {
|
||||
uint16_t : 7;
|
||||
uint16_t : 7;
|
||||
volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
|
||||
uint16_t : 8;
|
||||
uint16_t : 8;
|
||||
} LPCTRL_b;
|
||||
};
|
||||
|
||||
@ -773,9 +785,9 @@ typedef struct {
|
||||
volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
|
||||
|
||||
struct TU_ATTR_PACKED {
|
||||
uint16_t : 14;
|
||||
uint16_t : 14;
|
||||
volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
|
||||
uint16_t : 1;
|
||||
uint16_t : 1;
|
||||
} LPSTS_b;
|
||||
};
|
||||
volatile const uint32_t RESERVED23[15];
|
||||
@ -793,7 +805,7 @@ typedef struct {
|
||||
uint16_t : 2;
|
||||
volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
|
||||
volatile const uint16_t PDDETSTS : 1; /* [9..9] PDDET Status */
|
||||
uint16_t : 6;
|
||||
uint16_t : 6;
|
||||
} BCCTRL_b;
|
||||
};
|
||||
volatile const uint16_t RESERVED24;
|
||||
@ -809,7 +821,7 @@ typedef struct {
|
||||
volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
|
||||
uint16_t : 2;
|
||||
volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
|
||||
uint16_t : 1;
|
||||
uint16_t : 1;
|
||||
} PL1CTRL1_b;
|
||||
};
|
||||
|
||||
@ -817,10 +829,10 @@ typedef struct {
|
||||
volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
|
||||
|
||||
struct TU_ATTR_PACKED {
|
||||
uint16_t : 8;
|
||||
uint16_t : 8;
|
||||
volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
|
||||
volatile uint16_t RWEMON : 1; /* [12..12] RWE Value Monitor */
|
||||
uint16_t : 3;
|
||||
uint16_t : 3;
|
||||
} PL1CTRL2_b;
|
||||
};
|
||||
|
||||
@ -830,7 +842,7 @@ typedef struct {
|
||||
struct TU_ATTR_PACKED {
|
||||
volatile uint16_t L1REQ : 1; /* [0..0] L1 Transition Request */
|
||||
volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
|
||||
uint16_t : 13;
|
||||
uint16_t : 13;
|
||||
} HL1CTRL1_b;
|
||||
};
|
||||
|
||||
@ -846,18 +858,48 @@ typedef struct {
|
||||
volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
|
||||
} HL1CTRL2_b;
|
||||
};
|
||||
volatile const uint32_t RESERVED25[5];
|
||||
|
||||
volatile uint32_t RESERVED25_1;
|
||||
|
||||
union {
|
||||
volatile uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */
|
||||
|
||||
struct {
|
||||
volatile uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */
|
||||
volatile uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */
|
||||
uint16_t : 3;
|
||||
volatile uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */
|
||||
volatile uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */
|
||||
volatile uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance. */
|
||||
uint16_t : 1;
|
||||
} PHYTRIM1_b;
|
||||
};
|
||||
|
||||
union {
|
||||
volatile uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */
|
||||
|
||||
struct {
|
||||
volatile uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */
|
||||
uint16_t : 3;
|
||||
volatile uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */
|
||||
volatile uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */
|
||||
uint16_t : 2;
|
||||
volatile uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */
|
||||
uint16_t : 1;
|
||||
} PHYTRIM2_b;
|
||||
};
|
||||
volatile uint32_t RESERVED25_2[3];
|
||||
|
||||
union {
|
||||
volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
|
||||
|
||||
struct TU_ATTR_PACKED {
|
||||
uint32_t : 20;
|
||||
uint32_t : 20;
|
||||
volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
|
||||
volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
|
||||
uint32_t : 1;
|
||||
volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
|
||||
uint32_t : 8;
|
||||
uint32_t : 8;
|
||||
} DPUSR0R_b;
|
||||
};
|
||||
|
||||
@ -865,7 +907,7 @@ typedef struct {
|
||||
volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
|
||||
|
||||
struct TU_ATTR_PACKED {
|
||||
uint32_t : 4;
|
||||
uint32_t : 4;
|
||||
volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
|
||||
volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
|
||||
uint32_t : 1;
|
||||
@ -875,7 +917,7 @@ typedef struct {
|
||||
volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
|
||||
uint32_t : 1;
|
||||
volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
|
||||
uint32_t : 8;
|
||||
uint32_t : 8;
|
||||
} DPUSR1R_b;
|
||||
};
|
||||
|
||||
@ -891,7 +933,7 @@ typedef struct {
|
||||
uint16_t : 2;
|
||||
volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
|
||||
volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
|
||||
uint16_t : 6;
|
||||
uint16_t : 6;
|
||||
} DPUSR2R_b;
|
||||
};
|
||||
|
||||
@ -901,7 +943,7 @@ typedef struct {
|
||||
struct TU_ATTR_PACKED {
|
||||
volatile uint16_t FIXPHY : 1; /* [0..0] USB Transceiver Control Fix */
|
||||
volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
|
||||
uint16_t : 14;
|
||||
uint16_t : 14;
|
||||
} DPUSRCR_b;
|
||||
};
|
||||
volatile const uint32_t RESERVED26[165];
|
||||
@ -924,7 +966,7 @@ typedef struct {
|
||||
volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
|
||||
uint32_t : 1;
|
||||
volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
|
||||
uint32_t : 8;
|
||||
uint32_t : 8;
|
||||
} DPUSR0R_FS_b;
|
||||
};
|
||||
|
||||
@ -947,10 +989,10 @@ typedef struct {
|
||||
volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
|
||||
uint32_t : 1;
|
||||
volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
|
||||
uint32_t : 8;
|
||||
uint32_t : 8;
|
||||
} DPUSR1R_FS_b;
|
||||
};
|
||||
} RUSB2_REG_t; /* Size = 1032 (0x408) */
|
||||
} rusb2_reg_t; /* Size = 1032 (0x408) */
|
||||
|
||||
TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
|
||||
TU_ATTR_BIT_FIELD_ORDER_END
|
||||
@ -970,13 +1012,15 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */
|
||||
#define RUSB2_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */
|
||||
|
||||
// LINK_REG
|
||||
// Core Registers
|
||||
|
||||
// SYSCFG
|
||||
#define RUSB2_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */
|
||||
#define RUSB2_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */
|
||||
#define RUSB2_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */
|
||||
#define RUSB2_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */
|
||||
#define RUSB2_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */
|
||||
@ -1135,6 +1179,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */
|
||||
#define RUSB2_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */
|
||||
#define RUSB2_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */
|
||||
#define RUSB2_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */
|
||||
#define RUSB2_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */
|
||||
@ -1299,6 +1347,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */
|
||||
#define RUSB2_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */
|
||||
#define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
|
||||
#define RUSB2_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
|
||||
#define RUSB2_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */
|
||||
#define RUSB2_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */
|
||||
@ -1325,6 +1377,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */
|
||||
#define RUSB2_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
|
||||
#define RUSB2_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */
|
||||
#define RUSB2_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */
|
||||
@ -1332,6 +1386,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */
|
||||
#define RUSB2_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */
|
||||
|
||||
// PIPEBUF
|
||||
#define RUSB2_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */
|
||||
#define RUSB2_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */
|
||||
#define RUSB2_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */
|
||||
#define RUSB2_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */
|
||||
|
||||
// PIPEMAXP
|
||||
#define RUSB2_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */
|
||||
#define RUSB2_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
|
||||
@ -1478,6 +1538,28 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define RUSB2_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */
|
||||
#define RUSB2_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */
|
||||
|
||||
// PHYTRIM1
|
||||
#define RUSB2_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */
|
||||
#define RUSB2_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */
|
||||
#define RUSB2_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */
|
||||
#define RUSB2_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */
|
||||
#define RUSB2_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */
|
||||
#define RUSB2_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */
|
||||
#define RUSB2_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */
|
||||
#define RUSB2_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */
|
||||
#define RUSB2_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */
|
||||
|
||||
// PHYTRIM2
|
||||
#define RUSB2_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */
|
||||
#define RUSB2_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */
|
||||
#define RUSB2_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */
|
||||
#define RUSB2_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */
|
||||
#define RUSB2_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */
|
||||
#define RUSB2_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */
|
||||
#define RUSB2_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */
|
||||
#define RUSB2_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */
|
||||
|
||||
// DPUSR0R
|
||||
#define RUSB2_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */
|
||||
#define RUSB2_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
|
||||
@ -1599,69 +1681,72 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
|
||||
TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size");
|
||||
TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size");
|
||||
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG ) == 0x00000000, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA ) == 0x00000006, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO ) == 0x00000014, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO ) == 0x00000018, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0 ) == 0x00000030, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1 ) == 0x00000032, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB ) == 0x00000036, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB ) == 0x00000038, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET ) == 0x0000003E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR ) == 0x00000050, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ ) == 0x00000054, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL ) == 0x00000056, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX ) == 0x00000058, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG ) == 0x0000005A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR ) == 0x00000060, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL ) == 0x00000064, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG ) == 0x00000068, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC ) == 0x000000CC, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD ) == 0x000000D0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL ) == 0x00000100, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS ) == 0x00000102, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL ) == 0x00000140, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG ) == 0x0000, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT ) == 0x0002, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0 ) == 0x0004, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA ) == 0x0006, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0 ) == 0x0008, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE ) == 0x000C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO ) == 0x0014, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO ) == 0x0018, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO ) == 0x001C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL ) == 0x0020, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR ) == 0x0022, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL ) == 0x0028, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR ) == 0x002A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL ) == 0x002C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR ) == 0x002E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0 ) == 0x0030, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1 ) == 0x0032, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB ) == 0x0036, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB ) == 0x0038, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB ) == 0x003A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG ) == 0x003C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET ) == 0x003E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0 ) == 0x0040, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1 ) == 0x0042, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS ) == 0x0046, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS ) == 0x0048, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS ) == 0x004A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM ) == 0x004C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM ) == 0x004E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR ) == 0x0050, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ ) == 0x0054, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL ) == 0x0056, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX ) == 0x0058, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG ) == 0x005A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG ) == 0x005C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP ) == 0x005E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR ) == 0x0060, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL ) == 0x0064, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG ) == 0x0068, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF ) == 0x006A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP ) == 0x006C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI ) == 0x006E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR ) == 0x0070, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR ) == 0x0090, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL ) == 0x00C4, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC ) == 0x00CC, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD ) == 0x00D0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW ) == 0x00F0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL ) == 0x0100, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS ) == 0x0102, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL ) == 0x0140, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1 ) == 0x0144, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2 ) == 0x0146, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1 ) == 0x0148, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2 ) == 0x014A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1 ) == 0x0150, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2 ) == 0x0152, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R ) == 0x0160, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R ) == 0x0164, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R ) == 0x0168, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR ) == 0x016A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user