mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-23 22:43:49 +00:00
Ha Thach
GitHub
commit
f1e006d09b
84
.github/workflows/build_arm.yml
vendored
84
.github/workflows/build_arm.yml
vendored
@ -67,12 +67,6 @@ jobs:
|
||||
repository: hathach/linkermap
|
||||
path: linkermap
|
||||
|
||||
- name: Checkout pico-sdk for rp2040
|
||||
if: matrix.family == 'rp2040'
|
||||
run: |
|
||||
git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
|
||||
echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
|
||||
|
||||
- name: Get Dependencies
|
||||
run: python3 tools/get_deps.py ${{ matrix.family }}
|
||||
|
||||
@ -87,81 +81,3 @@ jobs:
|
||||
do
|
||||
find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
|
||||
done
|
||||
|
||||
# Upload binaries for hardware test with self-hosted
|
||||
- name: Prepare stm32l412nucleo Artifacts
|
||||
if: contains(matrix.family, 'stm32l4')
|
||||
run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
|
||||
|
||||
- name: Upload Artifacts for stm32l412nucleo
|
||||
if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
|
||||
uses: actions/upload-artifact@v3
|
||||
with:
|
||||
name: stm32l4
|
||||
path: |
|
||||
*.elf
|
||||
|
||||
# # ---------------------------------------
|
||||
# # Hardware in the loop (HIL)
|
||||
# # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
|
||||
# # - STM32L412 Nucleo with on-board jlink as ttyACM0
|
||||
# # ---------------------------------------
|
||||
# hw-stm32l412nucleo-test:
|
||||
# needs: build-arm
|
||||
# runs-on: [self-hosted, Linux, X64, hifiphile]
|
||||
#
|
||||
# steps:
|
||||
# - name: Clean workspace
|
||||
# run: |
|
||||
# echo "Cleaning up previous run"
|
||||
# rm -rf "${{ github.workspace }}"
|
||||
# mkdir -p "${{ github.workspace }}"
|
||||
#
|
||||
# - name: Download stm32l4 Artifacts
|
||||
# uses: actions/download-artifact@v3
|
||||
# with:
|
||||
# name: stm32l4
|
||||
#
|
||||
# - name: Create flash.sh
|
||||
# run: |
|
||||
# echo > flash.sh 'echo halt > flash.jlink'
|
||||
# echo >> flash.sh 'echo r >> flash.jlink'
|
||||
# echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
|
||||
# echo >> flash.sh 'echo r >> flash.jlink'
|
||||
# echo >> flash.sh 'echo go >> flash.jlink'
|
||||
# echo >> flash.sh 'echo exit >> flash.jlink'
|
||||
# echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
|
||||
# echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
|
||||
# chmod +x flash.sh
|
||||
#
|
||||
# - name: Test cdc_dual_ports
|
||||
# run: |
|
||||
# ./flash.sh cdc_dual_ports.elf
|
||||
# while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
|
||||
# test -e /dev/ttyACM1 && echo "ttyACM1 exists"
|
||||
# test -e /dev/ttyACM2 && echo "ttyACM2 exists"
|
||||
#
|
||||
# # Debian does not auto mount usb drive. skip this test for now
|
||||
# - name: Test cdc_msc
|
||||
# if: false
|
||||
# run: |
|
||||
# ./flash.sh cdc_msc.elf
|
||||
# readme='/media/pi/TinyUSB MSC/README.TXT'
|
||||
# while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
|
||||
# test -e /dev/ttyACM1 && echo "ttyACM1 exists"
|
||||
# test -f "$readme" && echo "$readme exists"
|
||||
# cat "$readme"
|
||||
#
|
||||
# - name: Test dfu
|
||||
# run: |
|
||||
# ./flash.sh dfu.elf
|
||||
# while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
|
||||
# dfu-util -d cafe -a 0 -U dfu0
|
||||
# dfu-util -d cafe -a 1 -U dfu1
|
||||
# grep "TinyUSB DFU! - Partition 0" dfu0
|
||||
# grep "TinyUSB DFU! - Partition 1" dfu1
|
||||
#
|
||||
# - name: Test dfu_runtime
|
||||
# run: |
|
||||
# ./flash.sh dfu_runtime.elf
|
||||
# while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
|
||||
|
||||
1
.github/workflows/cmake_arm.yml
vendored
1
.github/workflows/cmake_arm.yml
vendored
@ -38,6 +38,7 @@ jobs:
|
||||
- 'lpc18'
|
||||
- 'lpc55'
|
||||
- 'mcx'
|
||||
- 'ra'
|
||||
- 'rp2040'
|
||||
- 'stm32f0'
|
||||
- 'stm32f1'
|
||||
|
||||
7
.idea/cmake.xml
generated
7
.idea/cmake.xml
generated
@ -2,7 +2,7 @@
|
||||
<project version="4">
|
||||
<component name="CMakeSharedSettings">
|
||||
<configurations>
|
||||
<configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
|
||||
<configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
|
||||
<configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
|
||||
@ -25,7 +25,7 @@
|
||||
</envs>
|
||||
</ADDITIONAL_GENERATION_ENVIRONMENT>
|
||||
</configuration>
|
||||
<configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
|
||||
<configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
|
||||
<configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
|
||||
<configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
|
||||
@ -43,6 +43,9 @@
|
||||
<configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
|
||||
<configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
|
||||
<configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
|
||||
<configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
|
||||
</configurations>
|
||||
</component>
|
||||
</project>
|
||||
2
.idea/runConfigurations/kl25.xml
generated
2
.idea/runConfigurations/kl25.xml
generated
@ -1,5 +1,5 @@
|
||||
<component name="ProjectRunConfigurationManager">
|
||||
<configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MKL25Z128xxx4" -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
|
||||
<configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "MKL25Z128xxx4" -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
|
||||
<custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
|
||||
<debugger kind="GDB" isBundled="true" />
|
||||
</custom-gdb-server>
|
||||
|
||||
2
.idea/runConfigurations/stm32g474.xml
generated
2
.idea/runConfigurations/stm32g474.xml
generated
@ -1,5 +1,5 @@
|
||||
<component name="ProjectRunConfigurationManager">
|
||||
<configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "stm32g474re" -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
|
||||
<configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device "stm32g474re" -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
|
||||
<custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
|
||||
<debugger kind="GDB" isBundled="true" />
|
||||
</custom-gdb-server>
|
||||
|
||||
@ -36,6 +36,13 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
|
||||
message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
|
||||
endif()
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
set(WARNING_FLAGS_GNU
|
||||
-Wall
|
||||
-Wextra
|
||||
|
||||
@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -15,13 +15,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -23,12 +23,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
@ -124,8 +118,6 @@ function(family_configure_example TARGET RTOS)
|
||||
)
|
||||
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
|
||||
|
||||
|
||||
|
||||
# Link dependencies
|
||||
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
|
||||
|
||||
|
||||
180
hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
180
hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
Normal file
@ -0,0 +1,180 @@
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.0
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software. If you wish to use our Amazon
|
||||
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
// skip if included from IAR assembler
|
||||
#ifndef __IASMARM__
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#pragma GCC diagnostic ignored "-Wundef"
|
||||
|
||||
// extra push due to https://github.com/renesas/fsp/pull/278
|
||||
#pragma GCC diagnostic push
|
||||
#endif
|
||||
|
||||
#include "bsp_api.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Cortex M23/M33 port configuration. */
|
||||
#define configENABLE_MPU 0
|
||||
#define configENABLE_FPU 1
|
||||
#define configENABLE_TRUSTZONE 0
|
||||
#define configMINIMAL_SECURE_STACK_SIZE (1024)
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configCPU_CLOCK_HZ SystemCoreClock
|
||||
#define configTICK_RATE_HZ ( 1000 )
|
||||
#define configMAX_PRIORITIES ( 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( 128 )
|
||||
#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
|
||||
#define configMAX_TASK_NAME_LEN 16
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 2
|
||||
#define configUSE_QUEUE_SETS 0
|
||||
#define configUSE_TIME_SLICING 0
|
||||
#define configUSE_NEWLIB_REENTRANT 0
|
||||
#define configENABLE_BACKWARD_COMPATIBILITY 1
|
||||
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
|
||||
|
||||
#define configSUPPORT_STATIC_ALLOCATION 0
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1
|
||||
|
||||
/* Hook function related definitions. */
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
|
||||
/* Run time and task stats gathering related definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define configRECORD_STACK_HIGH_ADDRESS 1
|
||||
#define configUSE_TRACE_FACILITY 1 // legacy trace
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES 2
|
||||
|
||||
/* Software timer related definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
|
||||
#define configTIMER_QUEUE_LENGTH 32
|
||||
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
|
||||
|
||||
/* Optional functions - most linkers will remove unused functions anyway. */
|
||||
#define INCLUDE_vTaskPrioritySet 0
|
||||
#define INCLUDE_uxTaskPriorityGet 0
|
||||
#define INCLUDE_vTaskDelete 0
|
||||
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
|
||||
#define INCLUDE_xResumeFromISR 0
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 0
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 0
|
||||
#define INCLUDE_xTaskGetIdleTaskHandle 0
|
||||
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
|
||||
#define INCLUDE_pcTaskGetTaskName 0
|
||||
#define INCLUDE_eTaskGetState 0
|
||||
#define INCLUDE_xEventGroupSetBitFromISR 0
|
||||
#define INCLUDE_xTimerPendFunctionCall 0
|
||||
|
||||
/* Define to trap errors during development. */
|
||||
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
|
||||
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
|
||||
#define configASSERT(_exp) \
|
||||
do {\
|
||||
if ( !(_exp) ) { \
|
||||
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
|
||||
if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
|
||||
taskDISABLE_INTERRUPTS(); \
|
||||
__asm("BKPT #0\n"); \
|
||||
}\
|
||||
}\
|
||||
} while(0)
|
||||
#else
|
||||
#define configASSERT( x )
|
||||
#endif
|
||||
|
||||
/* FreeRTOS hooks to NVIC vectors */
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Interrupt nesting behavior configuration.
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
#endif
|
||||
10
hw/bsp/ra/boards/ra4m1_ek/board.cmake
Normal file
10
hw/bsp/ra/boards/ra4m1_ek/board.cmake
Normal file
@ -0,0 +1,10 @@
|
||||
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
|
||||
set(MCU_VARIANT ra4m1)
|
||||
|
||||
set(JLINK_DEVICE R7FA4M1AB)
|
||||
|
||||
function(update_board TARGET)
|
||||
# target_compile_definitions(${TARGET} PUBLIC)
|
||||
# target_sources(${TARGET} PRIVATE)
|
||||
# target_include_directories(${BOARD_TARGET} PUBLIC)
|
||||
endfunction()
|
||||
53
hw/bsp/ra/boards/ra4m1_ek/board.h
Normal file
53
hw/bsp/ra/boards/ra4m1_ek/board.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_01_PIN_06
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_01_PIN_05
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
|
||||
{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
|
||||
// USB FS D+, D-, VBus
|
||||
{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,13 +1,7 @@
|
||||
CPU_CORE = cortex-m4
|
||||
|
||||
FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m1
|
||||
FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
|
||||
MCU_VARIANT = ra4m1
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA4M1AB
|
||||
JLINK_IF = SWD
|
||||
|
||||
flash: flash-jlink
|
||||
|
||||
@ -2,7 +2,6 @@
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#include "board.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
@ -32,4 +31,13 @@
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
|
||||
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
|
||||
|
||||
#define BSP_FEATURE_TFU_SUPPORTED 0
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
@ -1,5 +0,0 @@
|
||||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
10
hw/bsp/ra/boards/ra4m3_ek/board.cmake
Normal file
10
hw/bsp/ra/boards/ra4m3_ek/board.cmake
Normal file
@ -0,0 +1,10 @@
|
||||
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
|
||||
set(MCU_VARIANT ra4m3)
|
||||
|
||||
set(JLINK_DEVICE R7FA4M3AF)
|
||||
|
||||
function(update_board TARGET)
|
||||
# target_compile_definitions(${TARGET} PUBLIC)
|
||||
# target_sources(${TARGET} PRIVATE)
|
||||
# target_include_directories(${BOARD_TARGET} PUBLIC)
|
||||
endfunction()
|
||||
53
hw/bsp/ra/boards/ra4m3_ek/board.h
Normal file
53
hw/bsp/ra/boards/ra4m3_ek/board.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 (BSP_IO_PORT_04_PIN_15)
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_05)
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
|
||||
{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
|
||||
// USB FS D+, D-, VBus
|
||||
{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -1,13 +1,7 @@
|
||||
CPU_CORE = cortex-m33
|
||||
|
||||
FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
|
||||
FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
|
||||
MCU_VARIANT = ra4m3
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA4M3AF
|
||||
JLINK_IF = SWD
|
||||
|
||||
flash: flash-jlink
|
||||
|
||||
4
hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h → hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
Executable file → Normal file
4
hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h → hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
Executable file → Normal file
@ -2,7 +2,6 @@
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#include "board.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
@ -32,4 +31,7 @@
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
@ -1,7 +0,0 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
@ -1,5 +0,0 @@
|
||||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
@ -1,236 +0,0 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022, Rafael Silva
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "r_ioport_api.h"
|
||||
#include "renesas.h"
|
||||
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
|
||||
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
|
||||
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_05)
|
||||
#define SW2 (BSP_IO_PORT_00_PIN_06)
|
||||
#define LED1 (BSP_IO_PORT_04_PIN_15)
|
||||
#define LED3 (BSP_IO_PORT_04_PIN_00)
|
||||
#define LED2 (BSP_IO_PORT_04_PIN_04)
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
void usbfs_d0fifo_handler(void);
|
||||
void usbfs_d1fifo_handler(void);
|
||||
|
||||
BSP_DONT_REMOVE const
|
||||
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
|
||||
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
|
||||
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
|
||||
{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void usbfs_interrupt_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
void usbfs_resume_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d0fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void usbfs_d1fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
tuh_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Init systick */
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
|
||||
return lvl;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
int close(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
int fstat(int fd, void *pstat)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pstat;
|
||||
return 0;
|
||||
}
|
||||
off_t lseek(int fd, off_t pos, int whence)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pos;
|
||||
(void) whence;
|
||||
return 0;
|
||||
}
|
||||
int isatty(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
@ -1,575 +0,0 @@
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x20000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x100000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x90000000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* This is a non-secure project if the OPTION_SETTING region is non-zero and it does not start at the base address for
|
||||
* secure option settings (meaning the secure option settings were already allocated in the secure project). */
|
||||
__TZ_NS_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) != ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* This is a secure project if the option setting base address matches the option setting base address for secure
|
||||
* option settings. This is also set for flat projects because the CPU runs in secure mode for flat projects.
|
||||
* This is not defined for projects that do not support TrustZone. */
|
||||
__TZ_S_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) == ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* If a flat (secure) project has defined RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = __TZ_S_PROJECT && DEFINED(RAM_NS_BUFFER_LENGTH);
|
||||
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
OPTION_SETTING_START_NS = 0x0100A180;
|
||||
OPTION_SETTING_START_S = 0x0100A100;
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* ROM Registers start at address 0x00000400 */
|
||||
. = __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = __ROM_Start + 0x500;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section. */
|
||||
.gnu.sgstubs : ALIGN (1024)
|
||||
{
|
||||
. = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.qspi_non_retentive : AT (__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_N = __ID_Code_End;
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING);
|
||||
|
||||
.option_setting :
|
||||
{
|
||||
__OPTION_SETTING_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = OPTION_SETTING_START_NS;
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
}
|
||||
10
hw/bsp/ra/boards/ra6m1_ek/board.cmake
Normal file
10
hw/bsp/ra/boards/ra6m1_ek/board.cmake
Normal file
@ -0,0 +1,10 @@
|
||||
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
|
||||
set(MCU_VARIANT ra6m1)
|
||||
|
||||
set(JLINK_DEVICE R7FA6M1AD)
|
||||
|
||||
function(update_board TARGET)
|
||||
# target_compile_definitions(${TARGET} PUBLIC)
|
||||
# target_sources(${TARGET} PRIVATE)
|
||||
# target_include_directories(${BOARD_TARGET} PUBLIC)
|
||||
endfunction()
|
||||
53
hw/bsp/ra/boards/ra6m1_ek/board.h
Normal file
53
hw/bsp/ra/boards/ra6m1_ek/board.h
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_01_PIN_12
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_04_PIN_15
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
|
||||
{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
|
||||
// USB FS D+, D-, VBus
|
||||
{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
7
hw/bsp/ra/boards/ra6m1_ek/board.mk
Normal file
7
hw/bsp/ra/boards/ra6m1_ek/board.mk
Normal file
@ -0,0 +1,7 @@
|
||||
CPU_CORE = cortex-m4
|
||||
MCU_VARIANT = ra6m1
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA6M1AD
|
||||
|
||||
flash: flash-jlink
|
||||
77
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
Normal file
77
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
Normal file
@ -0,0 +1,77 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
#define RA_NOT_DEFINED 0
|
||||
#ifndef BSP_CFG_RTOS
|
||||
#if (RA_NOT_DEFINED) != (2)
|
||||
#define BSP_CFG_RTOS (2)
|
||||
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (1)
|
||||
#else
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_RTC_USED
|
||||
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
|
||||
#endif
|
||||
|
||||
#undef RA_NOT_DEFINED
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
|
||||
#define BSP_CFG_HEAP_BYTES (0x1000)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
#endif
|
||||
|
||||
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
|
||||
#define BSP_FEATURE_TFU_SUPPORTED 0
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
|
||||
#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
@ -0,0 +1,5 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_CFG_MCU_PART_SERIES (6)
|
||||
#endif /* BSP_MCU_DEVICE_CFG_H_ */
|
||||
@ -0,0 +1,11 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_R7FA6M1AD3CFP
|
||||
#define BSP_MCU_FEATURE_SET ('A')
|
||||
#define BSP_ROM_SIZE_BYTES (524288)
|
||||
#define BSP_RAM_SIZE_BYTES (262144)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (100)
|
||||
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
|
||||
84
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
Normal file
84
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
Normal file
@ -0,0 +1,84 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_FAMILY_CFG_H_
|
||||
#define BSP_MCU_FAMILY_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_mcu_device_pn_cfg.h"
|
||||
#include "bsp_mcu_device_cfg.h"
|
||||
#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
|
||||
#define BSP_MCU_GROUP_RA6M1 (1)
|
||||
#define BSP_LOCO_HZ (32768)
|
||||
#define BSP_MOCO_HZ (8000000)
|
||||
#define BSP_SUB_CLOCK_HZ (32768)
|
||||
#if BSP_CFG_HOCO_FREQUENCY == 0
|
||||
#define BSP_HOCO_HZ (16000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 1
|
||||
#define BSP_HOCO_HZ (18000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 2
|
||||
#define BSP_HOCO_HZ (20000000)
|
||||
#else
|
||||
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_FLL_ENABLE (0)
|
||||
|
||||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/*
|
||||
ID Code
|
||||
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
|
||||
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
|
||||
*/
|
||||
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
|
||||
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
|
||||
#else
|
||||
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
|
||||
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
23
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
23
hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
@ -0,0 +1,23 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
10
hw/bsp/ra/boards/ra6m5_ek/board.cmake
Normal file
10
hw/bsp/ra/boards/ra6m5_ek/board.cmake
Normal file
@ -0,0 +1,10 @@
|
||||
set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
|
||||
set(MCU_VARIANT ra6m5)
|
||||
|
||||
set(JLINK_DEVICE R7FA6M5BH)
|
||||
|
||||
function(update_board TARGET)
|
||||
# target_compile_definitions(${TARGET} PUBLIC)
|
||||
# target_sources(${TARGET} PRIVATE)
|
||||
# target_include_directories(${BOARD_TARGET} PUBLIC)
|
||||
endfunction()
|
||||
66
hw/bsp/ra/boards/ra6m5_ek/board.h
Normal file
66
hw/bsp/ra/boards/ra6m5_ek/board.h
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_00_PIN_08
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_00_PIN_05
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{ .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
|
||||
{ .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
|
||||
|
||||
// USB FS D+, D-, VBus
|
||||
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
|
||||
{ .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
|
||||
{ .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
|
||||
|
||||
// USB HS D+, D-, VBus
|
||||
{ .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
|
||||
{ .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
|
||||
{ .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
|
||||
|
||||
// ETM Trace
|
||||
{ .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
|
||||
{ .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
7
hw/bsp/ra/boards/ra6m5_ek/board.mk
Normal file
7
hw/bsp/ra/boards/ra6m5_ek/board.mk
Normal file
@ -0,0 +1,7 @@
|
||||
CPU_CORE = cortex-m33
|
||||
MCU_VARIANT = ra6m5
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA6M5BH
|
||||
|
||||
flash: flash-jlink
|
||||
65
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
Normal file
65
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
Normal file
@ -0,0 +1,65 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
#define RA_NOT_DEFINED 0
|
||||
#ifndef BSP_CFG_RTOS
|
||||
#if (RA_NOT_DEFINED) != (2)
|
||||
#define BSP_CFG_RTOS (2)
|
||||
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (1)
|
||||
#else
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#endif
|
||||
#endif
|
||||
#ifndef BSP_CFG_RTC_USED
|
||||
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
|
||||
#define BSP_CFG_HEAP_BYTES (0x1000)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
#endif
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_CFG_H_ */
|
||||
@ -0,0 +1,5 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_CFG_MCU_PART_SERIES (6)
|
||||
#endif /* BSP_MCU_DEVICE_CFG_H_ */
|
||||
@ -0,0 +1,11 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_R7FA6M5BH3CFC
|
||||
#define BSP_MCU_FEATURE_SET ('B')
|
||||
#define BSP_ROM_SIZE_BYTES (2097152)
|
||||
#define BSP_RAM_SIZE_BYTES (524288)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (176)
|
||||
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
|
||||
387
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
Normal file
387
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
Normal file
@ -0,0 +1,387 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_FAMILY_CFG_H_
|
||||
#define BSP_MCU_FAMILY_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_mcu_device_pn_cfg.h"
|
||||
#include "bsp_mcu_device_cfg.h"
|
||||
#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
|
||||
#define BSP_MCU_GROUP_RA6M5 (1)
|
||||
#define BSP_LOCO_HZ (32768)
|
||||
#define BSP_MOCO_HZ (8000000)
|
||||
#define BSP_SUB_CLOCK_HZ (32768)
|
||||
#if BSP_CFG_HOCO_FREQUENCY == 0
|
||||
#define BSP_HOCO_HZ (16000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 1
|
||||
#define BSP_HOCO_HZ (18000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 2
|
||||
#define BSP_HOCO_HZ (20000000)
|
||||
#else
|
||||
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_FLL_ENABLE (0)
|
||||
|
||||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
|
||||
|
||||
#if defined(_RA_TZ_SECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (1)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#elif defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (1)
|
||||
#else
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#endif
|
||||
|
||||
/* TrustZone Settings */
|
||||
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
|
||||
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
|
||||
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
|
||||
|
||||
/* CMSIS TrustZone Settings */
|
||||
#define SCB_CSR_AIRCR_INIT (1)
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL (0)
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
|
||||
#define SCB_AIRCR_PRIS_VAL (0)
|
||||
#define TZ_FPU_NS_USAGE (1)
|
||||
#ifndef SCB_NSACR_CP10_11_VAL
|
||||
#define SCB_NSACR_CP10_11_VAL (3U)
|
||||
#endif
|
||||
|
||||
#ifndef FPU_FPCCR_TS_VAL
|
||||
#define FPU_FPCCR_TS_VAL (1U)
|
||||
#endif
|
||||
#define FPU_FPCCR_CLRONRETS_VAL (1)
|
||||
|
||||
#ifndef FPU_FPCCR_CLRONRET_VAL
|
||||
#define FPU_FPCCR_CLRONRET_VAL (1)
|
||||
#endif
|
||||
|
||||
/* The C-Cache line size that is configured during startup. */
|
||||
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
|
||||
#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
|
||||
#endif
|
||||
|
||||
/* Type 1 Peripheral Security Attribution */
|
||||
|
||||
/* Peripheral Security Attribution Register (PSAR) Settings */
|
||||
#ifndef BSP_TZ_CFG_PSARB
|
||||
#define BSP_TZ_CFG_PSARB (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
|
||||
0x33f4f9) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARC
|
||||
#define BSP_TZ_CFG_PSARC (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
|
||||
0x7fffcef4) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARD
|
||||
#define BSP_TZ_CFG_PSARD (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
|
||||
0xffae07f0) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARE
|
||||
#define BSP_TZ_CFG_PSARE (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
|
||||
0x3f3ff8) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_MSSAR
|
||||
#define BSP_TZ_CFG_MSSAR (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
|
||||
0xfffffffc) /* Unused */
|
||||
#endif
|
||||
|
||||
/* Type 2 Peripheral Security Attribution */
|
||||
|
||||
/* Security attribution for Cache registers. */
|
||||
#ifndef BSP_TZ_CFG_CSAR
|
||||
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for RSTSRn registers. */
|
||||
#ifndef BSP_TZ_CFG_RSTSAR
|
||||
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers of LVD channels. */
|
||||
#ifndef BSP_TZ_CFG_LVDSAR
|
||||
#define BSP_TZ_CFG_LVDSAR (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
|
||||
0xFFFFFFFCU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for LPM registers. */
|
||||
#ifndef BSP_TZ_CFG_LPMSAR
|
||||
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Deep Standby Interrupt Factor Security Attribution Register. */
|
||||
#ifndef BSP_TZ_CFG_DPFSAR
|
||||
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for CGC registers. */
|
||||
#ifndef BSP_TZ_CFG_CGFSAR
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect all CGC registers from Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers. */
|
||||
#ifndef BSP_TZ_CFG_BBFSAR
|
||||
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARA
|
||||
#define BSP_TZ_CFG_ICUSARA (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
|
||||
0xFFFF0000U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARB
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#ifndef BSP_TZ_CFG_ICUSARC
|
||||
#define BSP_TZ_CFG_ICUSARC (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
|
||||
0xFFFFFF00U)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARD
|
||||
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARE
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARF
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
#if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#else
|
||||
#define BSP_TZ_CFG_DTC_USED (1U)
|
||||
#endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
#ifndef BSP_TZ_CFG_FSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFEFEU)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
#ifndef BSP_TZ_CFG_SRAMSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (\
|
||||
1 | \
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
|
||||
4 | \
|
||||
0xFFFFFFF8U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#ifndef BSP_TZ_CFG_STBRAMSAR
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
#ifndef BSP_TZ_CFG_MMPUSARA
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
#endif
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARA
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARB
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#endif
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/* Dual Mode Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_DUALSEL
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#endif
|
||||
|
||||
/* Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS0
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS1
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS2
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS3
|
||||
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS0
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS1
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS2
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS3
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
35
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
35
hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
Normal file
@ -0,0 +1,35 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
|
||||
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
35
hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
Normal file
35
hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
Normal file
@ -0,0 +1,35 @@
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* OnProjectLoad
|
||||
*
|
||||
* Function description
|
||||
* Project load routine. Required.
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
void OnProjectLoad (void) {
|
||||
Project.AddSvdFile ("Cortex-M33.svd");
|
||||
Project.AddSvdFile ("./R7FA6M5BH.svd");
|
||||
|
||||
Project.SetDevice ("R7FA6M5BH");
|
||||
Project.SetHostIF ("USB", "");
|
||||
Project.SetTargetIF ("SWD");
|
||||
Project.SetTIFSpeed ("50 MHz");
|
||||
|
||||
Project.SetTraceSource ("Trace Pins");
|
||||
Project.SetTracePortWidth (4);
|
||||
|
||||
File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
|
||||
}
|
||||
/*********************************************************************
|
||||
*
|
||||
* BeforeTargetConnect
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
void BeforeTargetConnect (void) {
|
||||
//
|
||||
// Trace pin init is done by J-Link script file as J-Link script files are IDE independent
|
||||
//
|
||||
}
|
||||
@ -26,59 +26,123 @@
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "bsp/board.h"
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#pragma GCC diagnostic ignored "-Wundef"
|
||||
|
||||
// extra push due to https://github.com/renesas/fsp/pull/278
|
||||
#pragma GCC diagnostic push
|
||||
#endif
|
||||
|
||||
#include "bsp_api.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#include "r_ioport.h"
|
||||
#include "r_ioport_api.h"
|
||||
#include "renesas.h"
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "board.h"
|
||||
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
|
||||
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
|
||||
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
|
||||
|
||||
#define SW1 (BSP_IO_PORT_01_PIN_05)
|
||||
#define LED1 (BSP_IO_PORT_01_PIN_06)
|
||||
static const ioport_cfg_t family_pin_cfg = {
|
||||
.number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = board_pin_cfg,
|
||||
};
|
||||
static ioport_instance_ctrl_t port_ctrl;
|
||||
|
||||
#define LED_STATE_ON 1
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
//--------------------------------------------------------------------+
|
||||
// Vector Data
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
void usbfs_d0fifo_handler(void);
|
||||
void usbfs_d1fifo_handler(void);
|
||||
|
||||
BSP_DONT_REMOVE const
|
||||
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
|
||||
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
|
||||
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
|
||||
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{ .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
|
||||
{ .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
{ .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
|
||||
{ .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
|
||||
{ .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
|
||||
|
||||
};
|
||||
#ifdef TRACE_ETM
|
||||
// Enable trace clock with div 1 (100 Mhz)
|
||||
R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk;
|
||||
#endif
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
|
||||
board_led_write(false);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_led_write(bool state) {
|
||||
R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
|
||||
return lvl == BUTTON_STATE_ACTIVE;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len) {
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len) {
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void) {
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
@ -139,94 +203,29 @@ void usbfs_d1fifo_handler(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Init systick */
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
// stdlib
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
|
||||
return lvl == BUTTON_STATE_ACTIVE;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
int close(int fd)
|
||||
{
|
||||
int close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
int fstat(int fd, void *pstat)
|
||||
{
|
||||
|
||||
int fstat(int fd, void *pstat) {
|
||||
(void) fd;
|
||||
(void) pstat;
|
||||
return 0;
|
||||
}
|
||||
off_t lseek(int fd, off_t pos, int whence)
|
||||
{
|
||||
|
||||
off_t lseek(int fd, off_t pos, int whence) {
|
||||
(void) fd;
|
||||
(void) pos;
|
||||
(void) whence;
|
||||
return 0;
|
||||
}
|
||||
int isatty(int fd)
|
||||
{
|
||||
|
||||
int isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
131
hw/bsp/ra/family.cmake
Normal file
131
hw/bsp/ra/family.cmake
Normal file
@ -0,0 +1,131 @@
|
||||
include_guard()
|
||||
|
||||
if (NOT BOARD)
|
||||
message(FATAL_ERROR "BOARD not specified")
|
||||
endif ()
|
||||
|
||||
set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
|
||||
set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
|
||||
|
||||
# include board specific
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
|
||||
#set(FREERTOS_PORT A_CUSTOM_PORT CACHE INTERNAL "")
|
||||
|
||||
set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS RA CACHE INTERNAL "")
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
#------------------------------------
|
||||
# only need to be built ONCE for all examples
|
||||
function(add_board_target BOARD_TARGET)
|
||||
if (NOT TARGET ${BOARD_TARGET})
|
||||
add_library(${BOARD_TARGET} STATIC
|
||||
${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/startup.c
|
||||
${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/system.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_clocks.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_common.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_delay.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_group_irq.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_guard.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_io.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_irq.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
|
||||
${FSP_RA}/src/bsp/mcu/all/bsp_security.c
|
||||
${FSP_RA}/src/r_ioport/r_ioport.c
|
||||
)
|
||||
target_compile_definitions(${BOARD_TARGET} PUBLIC
|
||||
_RA_TZ_NONSECURE
|
||||
)
|
||||
|
||||
target_compile_options(${BOARD_TARGET} PUBLIC
|
||||
-ffreestanding
|
||||
)
|
||||
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp
|
||||
${CMSIS_DIR}/CMSIS/Core/Include
|
||||
${FSP_RA}/inc
|
||||
${FSP_RA}/inc/api
|
||||
${FSP_RA}/inc/instances
|
||||
${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
|
||||
${FSP_RA}/src/bsp/mcu/all
|
||||
${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
|
||||
)
|
||||
|
||||
update_board(${BOARD_TARGET})
|
||||
|
||||
if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld)
|
||||
endif ()
|
||||
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
# linker file
|
||||
"LINKER:--script=${LD_FILE_GNU}"
|
||||
-L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc
|
||||
-nostartfiles
|
||||
# nanolib
|
||||
--specs=nano.specs
|
||||
--specs=nosys.specs
|
||||
)
|
||||
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--config=${LD_FILE_IAR}"
|
||||
)
|
||||
endif ()
|
||||
endif ()
|
||||
endfunction()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# Functions
|
||||
#------------------------------------
|
||||
function(family_configure_example TARGET RTOS)
|
||||
family_configure_common(${TARGET} ${RTOS})
|
||||
|
||||
# Board target
|
||||
add_board_target(board_${BOARD})
|
||||
|
||||
#---------- Port Specific ----------
|
||||
# These files are built for each example since it depends on example's tusb_config.h
|
||||
target_sources(${TARGET} PUBLIC
|
||||
# BSP
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
# family, hw, board
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
|
||||
)
|
||||
|
||||
# # RA has custom freertos port
|
||||
# if (NOT TARGET freertos_kernel_port)
|
||||
# add_library(freertos_kernel_port STATIC)
|
||||
# target_sources(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port/port.c)
|
||||
# target_include_directories(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port)
|
||||
#
|
||||
# target_link_libraries(freertos_kernel_port PUBLIC freertos_kernel)
|
||||
# endif ()
|
||||
|
||||
# Add TinyUSB target and port source
|
||||
family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
|
||||
target_sources(${TARGET}-tinyusb PUBLIC
|
||||
${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
|
||||
${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
|
||||
)
|
||||
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
|
||||
|
||||
# Link dependencies
|
||||
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
|
||||
|
||||
# Flashing
|
||||
family_flash_jlink(${TARGET})
|
||||
endfunction()
|
||||
@ -1,5 +1,6 @@
|
||||
DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
|
||||
|
||||
FSP_RA = hw/mcu/renesas/fsp/ra/fsp
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
CFLAGS += \
|
||||
@ -10,44 +11,44 @@ CFLAGS += \
|
||||
-Wno-error=cast-qual \
|
||||
-Wno-error=unused-but-set-variable \
|
||||
-Wno-error=unused-variable \
|
||||
-mthumb \
|
||||
-nostdlib \
|
||||
-nostartfiles \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding
|
||||
|
||||
SRC_C += \
|
||||
src/portable/renesas/rusb2/dcd_rusb2.c \
|
||||
src/portable/renesas/rusb2/hcd_rusb2.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/r_ioport/r_ioport.c \
|
||||
$(FSP_BOARD_DIR)/board_init.c \
|
||||
$(FSP_BOARD_DIR)/board_leds.c
|
||||
$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
|
||||
$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_common.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_delay.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_group_irq.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_guard.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_io.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_irq.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_register_protection.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_rom_registers.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_sbrk.c \
|
||||
$(FSP_RA)/src/bsp/mcu/all/bsp_security.c \
|
||||
$(FSP_RA)/src/r_ioport/r_ioport.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(BOARD_PATH)/fsp_cfg \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
|
||||
$(TOP)/$(FSP_MCU_DIR) \
|
||||
$(TOP)/$(FSP_BOARD_DIR)
|
||||
$(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \
|
||||
$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
|
||||
$(TOP)/$(FSP_RA)/inc \
|
||||
$(TOP)/$(FSP_RA)/inc/api \
|
||||
$(TOP)/$(FSP_RA)/inc/instances \
|
||||
$(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
|
||||
|
||||
ifndef LD_FILE
|
||||
LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
|
||||
LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
|
||||
endif
|
||||
|
||||
# For freeRTOS port source
|
||||
# hack to use the port provided by renesas
|
||||
FREERTOS_PORTABLE_SRC = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
|
||||
FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
|
||||
|
||||
@ -1,29 +1,3 @@
|
||||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
|
||||
/*
|
||||
XIP_SECONDARY_SLOT_IMAGE = 1;
|
||||
@ -553,6 +527,7 @@ SECTIONS
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
PROVIDE(end = .);
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
@ -628,6 +603,11 @@ SECTIONS
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
|
||||
* Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
|
||||
* memory region between TrustZone projects. */
|
||||
__tz_ID_CODE_N = __tz_ID_CODE_S;
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
@ -635,8 +615,6 @@ SECTIONS
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_N = __ID_Code_End;
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
|
||||
22
hw/bsp/ra/linker/gcc/ra4m1.ld
Normal file
22
hw/bsp/ra/linker/gcc/ra4m1.ld
Normal file
@ -0,0 +1,22 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x8000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x40000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x01010018;
|
||||
ID_CODE_LENGTH = 0x20;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x0;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
22
hw/bsp/ra/linker/gcc/ra4m3.ld
Normal file
22
hw/bsp/ra/linker/gcc/ra4m3.ld
Normal file
@ -0,0 +1,22 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x20000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x100000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
22
hw/bsp/ra/linker/gcc/ra6m1.ld
Normal file
22
hw/bsp/ra/linker/gcc/ra6m1.ld
Normal file
@ -0,0 +1,22 @@
|
||||
RAM_START = 0x1FFE0000;
|
||||
RAM_LENGTH = 0x40000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x80000;
|
||||
DATA_FLASH_START = 0x40100000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x00000000;
|
||||
OPTION_SETTING_LENGTH = 0x0;
|
||||
OPTION_SETTING_S_START = 0x80000000;
|
||||
OPTION_SETTING_S_LENGTH = 0x0;
|
||||
ID_CODE_START = 0x0100A150;
|
||||
ID_CODE_LENGTH = 0x10;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x80020000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x80030000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
22
hw/bsp/ra/linker/gcc/ra6m5.ld
Normal file
22
hw/bsp/ra/linker/gcc/ra6m5.ld
Normal file
@ -0,0 +1,22 @@
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x80000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x200000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x8000000;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x10000000;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
29
hw/bsp/ra/vector_data.h
Normal file
29
hw/bsp/ra/vector_data.h
Normal file
@ -0,0 +1,29 @@
|
||||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#ifndef VECTOR_DATA_H
|
||||
#define VECTOR_DATA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef VECTOR_DATA_IRQ_COUNT
|
||||
#define VECTOR_DATA_IRQ_COUNT 4
|
||||
#endif
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
void usbfs_d0fifo_handler(void);
|
||||
void usbfs_d1fifo_handler(void);
|
||||
|
||||
/* Vector table allocations */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32F7 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
|
||||
|
||||
# enable LTO if supported
|
||||
include(CheckIPOSupported)
|
||||
check_ipo_supported(RESULT IPO_SUPPORTED)
|
||||
if (IPO_SUPPORTED)
|
||||
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
|
||||
endif ()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
|
||||
@ -31,9 +31,22 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#pragma GCC diagnostic ignored "-Wundef"
|
||||
|
||||
// extra push due to https://github.com/renesas/fsp/pull/278
|
||||
#pragma GCC diagnostic push
|
||||
#endif
|
||||
|
||||
/* renesas fsp api */
|
||||
#include "bsp_api.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#define RUSB2_REG_BASE (0x40090000)
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
|
||||
@ -6,7 +6,9 @@ if (TOOLCHAIN STREQUAL "gcc")
|
||||
-mfpu=fpv4-sp-d16
|
||||
)
|
||||
|
||||
set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
|
||||
if (NOT DEFINED FREERTOS_PORT)
|
||||
set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
|
||||
endif ()
|
||||
|
||||
elseif (TOOLCHAIN STREQUAL "iar")
|
||||
set(TOOLCHAIN_COMMON_FLAGS
|
||||
@ -14,6 +16,8 @@ elseif (TOOLCHAIN STREQUAL "iar")
|
||||
--fpu VFPv4
|
||||
)
|
||||
|
||||
set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
|
||||
if (NOT DEFINED FREERTOS_PORT)
|
||||
set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
|
||||
endif ()
|
||||
|
||||
endif ()
|
||||
|
||||
@ -11,4 +11,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
endif
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
|
||||
|
||||
@ -11,4 +11,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
endif
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
|
||||
|
||||
@ -14,4 +14,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
endif
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM3
|
||||
|
||||
@ -16,4 +16,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
|
||||
endif
|
||||
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
|
||||
|
||||
@ -10,4 +10,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
ASFLAGS += --cpu cortex-m4 --fpu VFPv4
|
||||
endif
|
||||
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
|
||||
|
||||
@ -16,4 +16,4 @@ else ifeq ($(TOOLCHAIN),iar)
|
||||
|
||||
endif
|
||||
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
|
||||
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user