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Merge pull request #2818 from hathach/add-esp32p4

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Add esp32p4 OTG HS support
This commit is contained in:
Ha Thach 2024-10-01 11:15:33 +07:00 committed by GitHub
commit eda3cceab2
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GPG Key ID: B5690EEEBB952194
36 changed files with 714 additions and 385 deletions
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2
.circleci/config2.yml
View File

@ -105,7 +105,7 @@ commands:
name: Build
command: |
if [ << parameters.toolchain >> == esp-idf ]; then
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python tools/build.py << parameters.family >>
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.1 python tools/build.py << parameters.family >>
else
# Toolchain option default is gcc
if [ << parameters.toolchain >> == arm-clang ]; then

2
.github/workflows/build.yml vendored
View File

@ -85,7 +85,7 @@ jobs:
- 'msp430-gcc'
- 'riscv-gcc'
- 'rx-gcc'
- 'esp-idf' # buid-system is ignored
- 'esp-idf' # build-system is ignored
with:
build-system: 'make'
toolchain: ${{ matrix.toolchain }}

4
.github/workflows/build_util.yml vendored
View File

@ -41,7 +41,7 @@ jobs:
uses: ./.github/actions/setup_toolchain
with:
toolchain: ${{ inputs.toolchain }}
toolchain_version: 'v5.1.1'
toolchain_version: 'v5.3.1'
- name: Get Dependencies
uses: ./.github/actions/get_deps
@ -61,7 +61,7 @@ jobs:
- name: Build
run: |
if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python tools/build.py ${{ matrix.arg }}
docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.1 python tools/build.py ${{ matrix.arg }}
else
python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ steps.set-one-per-family.outputs.build_option }} ${{ matrix.arg }}
fi

1
.github/workflows/ci_set_matrix.py vendored
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@ -45,6 +45,7 @@ family_list = {
"xmc4000": ["arm-gcc"],
"-bespressif_kaluga_1": ["esp-idf"],
"-bespressif_s3_devkitm": ["esp-idf"],
"-bespressif_p4_function_ev": ["esp-idf"],
}

7
.idea/cmake.xml generated
View File

@ -65,6 +65,13 @@
</envs>
</ADDITIONAL_GENERATION_ENVIRONMENT>
</configuration>
<configuration PROFILE_NAME="espressif_p4_function_ev" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_p4_function_ev -DLOG=1">
<ADDITIONAL_GENERATION_ENVIRONMENT>
<envs>
<env name="ESPBAUD" value="1500000" />
</envs>
</ADDITIONAL_GENERATION_ENVIRONMENT>
</configuration>
<configuration PROFILE_NAME="feather_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
<configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
<configuration PROFILE_NAME="feather_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />

1
examples/device/audio_4_channel_mic_freertos/skip.txt
View File

@ -4,6 +4,7 @@ mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040

1
examples/device/audio_test_freertos/skip.txt
View File

@ -4,6 +4,7 @@ mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040

1
examples/device/cdc_msc_freertos/skip.txt
View File

@ -4,6 +4,7 @@ mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040

1
examples/device/hid_composite_freertos/skip.txt
View File

@ -4,6 +4,7 @@ mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040

1
examples/device/net_lwip_webserver/skip.txt
View File

@ -3,6 +3,7 @@ mcu:CH32V20X
mcu:LPC11UXX
mcu:LPC13XX
mcu:LPC15XX
mcu:MCXA15
mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11

1
examples/device/video_capture/skip.txt
View File

@ -1,5 +1,6 @@
mcu:CH32V103
mcu:CH32V20X
mcu:MCXA15
mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11

1
examples/device/video_capture_2ch/skip.txt
View File

@ -6,6 +6,7 @@ mcu:CH32V103
mcu:CH32V20X
mcu:CH32V307
mcu:STM32L0
mcu:MCXA15
family:espressif
board:curiosity_nano
board:kuiic

4
hw/bsp/espressif/boards/CMakeLists.txt
View File

@ -2,7 +2,5 @@ set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../")
idf_component_register(SRCS family.c
INCLUDE_DIRS "." ${BOARD} ${hw_dir}
PRIV_REQUIRES "driver"
PRIV_REQUIRES driver usb
REQUIRES led_strip src tinyusb_src)
target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)

1
hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
View File

@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32")
set(MAX3421_HOST 1)

1
hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
View File

@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32s2")
set(MAX3421_HOST 1)

3
hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake Normal file
View File

@ -0,0 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32s3")
set(MAX3421_HOST 1)

53
hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h Normal file
View File

@ -0,0 +1,53 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
#define NEOPIXEL_PIN 33
#define NEOPIXEL_POWER_PIN 21
#define NEOPIXEL_POWER_STATE 1
#define BUTTON_PIN 0
#define BUTTON_STATE_ACTIVE 0
// SPI for USB host shield
#define MAX3421_SPI_HOST SPI2_HOST
#define MAX3421_SCK_PIN 36
#define MAX3421_MOSI_PIN 35
#define MAX3421_MISO_PIN 37
#define MAX3421_CS_PIN 10
#define MAX3421_INTR_PIN 9
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H_ */

1
hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
View File

@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32s2")
set(MAX3421_HOST 1)

1
hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake
View File

@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32c3")
set(MAX3421_HOST 1)

1
hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake
View File

@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32c6")
set(MAX3421_HOST 1)

2
hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake Normal file
View File

@ -0,0 +1,2 @@
# Apply board specific content here
set(IDF_TARGET "esp32p4")

43
hw/bsp/espressif/boards/espressif_p4_function_ev/board.h Normal file
View File

@ -0,0 +1,43 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
// #define NEOPIXEL_PIN 48
#define BUTTON_PIN 0
#define BUTTON_STATE_ACTIVE 0
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H_ */

135
hw/bsp/espressif/boards/family.c
View File

@ -31,20 +31,9 @@
#include "esp_mac.h"
#include "hal/gpio_ll.h"
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
#include "hal/usb_hal.h"
#include "soc/usb_periph.h"
static void configure_pins(usb_hal_context_t* usb);
#endif
#include "driver/gpio.h"
#include "driver/uart.h"
#if ESP_IDF_VERSION_MAJOR > 4
#include "esp_private/periph_ctrl.h"
#else
#include "driver/periph_ctrl.h"
#endif
#include "esp_private/periph_ctrl.h"
// Note; current code use UART0 can cause device to reset while monitoring
#define USE_UART 0
@ -60,6 +49,7 @@ static led_strip_handle_t led_strip;
static void max3421_init(void);
#endif
static bool usb_init(void);
//--------------------------------------------------------------------+
// Implementation
@ -111,16 +101,8 @@ void board_init(void) {
gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// USB Controller Hal init
periph_module_reset(PERIPH_USB_MODULE);
periph_module_enable(PERIPH_USB_MODULE);
usb_hal_context_t hal = {
.use_external_phy = false // use built-in PHY
};
usb_hal_init(&hal);
configure_pins(&hal);
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
usb_init();
#endif
#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
@ -129,35 +111,7 @@ void board_init(void) {
}
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
static void configure_pins(usb_hal_context_t* usb) {
/* usb_periph_iopins currently configures USB_OTG as USB Device.
* Introduce additional parameters in usb_hal_context_t when adding support
* for USB Host. */
for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
esp_rom_gpio_pad_select_gpio(iopin->pin);
if (iopin->is_output) {
esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
} else {
esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
#if ESP_IDF_VERSION_MAJOR > 4
if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
#else
if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
#endif
{
gpio_ll_input_enable(&GPIO, iopin->pin);
}
}
esp_rom_gpio_pad_unhold(iopin->pin);
}
}
if (!usb->use_external_phy) {
gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
}
}
#endif
//--------------------------------------------------------------------+
@ -204,6 +158,87 @@ int board_getchar(void) {
return board_uart_read(&c, 1) > 0 ? (int) c : (-1);
}
//--------------------------------------------------------------------
// PHY Init
//--------------------------------------------------------------------
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0)
#include "esp_private/usb_phy.h"
#include "soc/usb_pins.h"
static usb_phy_handle_t phy_hdl;
bool usb_init(void) {
// Configure USB PHY
usb_phy_config_t phy_conf = {
.controller = USB_PHY_CTRL_OTG,
.target = USB_PHY_TARGET_INT,
.otg_mode = USB_OTG_MODE_DEVICE,
};
// OTG IOs config
// const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io);
// if (config->self_powered) {
// phy_conf.otg_io_conf = &otg_io_conf;
// }
// ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed");
usb_new_phy(&phy_conf, &phy_hdl);
return true;
}
#else
#include "esp_private/usb_phy.h"
#include "hal/usb_hal.h"
#include "soc/usb_periph.h"
static void configure_pins(usb_hal_context_t* usb) {
/* usb_periph_iopins currently configures USB_OTG as USB Device.
* Introduce additional parameters in usb_hal_context_t when adding support
* for USB Host. */
for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
esp_rom_gpio_pad_select_gpio(iopin->pin);
if (iopin->is_output) {
esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
} else {
esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) {
gpio_ll_input_enable(&GPIO, iopin->pin);
}
}
esp_rom_gpio_pad_unhold(iopin->pin);
}
}
if (!usb->use_external_phy) {
gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
}
}
bool usb_init(void) {
// USB Controller Hal init
periph_module_reset(PERIPH_USB_MODULE);
periph_module_enable(PERIPH_USB_MODULE);
usb_hal_context_t hal = {
.use_external_phy = false // use built-in PHY
};
usb_hal_init(&hal);
configure_pins(&hal);
return true;
}
#endif
#endif
//--------------------------------------------------------------------+
// API: SPI transfer with MAX3421E, must be implemented by application
//--------------------------------------------------------------------+

3
hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
View File

@ -9,6 +9,9 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu)
list(APPEND compile_definitions
CFG_TUSB_MCU=${tusb_mcu}
CFG_TUSB_OS=OPT_OS_FREERTOS
# EXAMPLE port selection: port0 is fullspeed, port1 is highspeed
BOARD_TUD_RHPORT=${TUD_PORT}
BOARD_TUD_MAX_SPEED=$<IF:${TUD_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
)
list(APPEND srcs

13
hw/bsp/espressif/family.cmake
View File

@ -2,10 +2,21 @@ cmake_minimum_required(VERSION 3.5)
# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed)
if (NOT DEFINED TUD_PORT)
if (IDF_TARGET STREQUAL "esp32p4")
set(TUD_PORT 1)
else ()
set(TUD_PORT 0)
endif ()
endif()
# Add example src and bsp directories
set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
# set SDKCONFIG for each IDF Target
set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET})
include($ENV{IDF_PATH}/tools/cmake/project.cmake)

8
src/common/tusb_mcu.h
View File

@ -337,7 +337,13 @@
#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_ESP32
#define TUP_DCD_ENDPOINT_MAX 6
#define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_ESP32
#define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS
#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
#if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))

68
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -31,6 +31,9 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
// Debug level for DWC2
#define DWC2_DEBUG 2
#include "device/dcd.h"
#include "dwc2_type.h"
@ -57,16 +60,25 @@
#error "Unsupported MCUs"
#endif
enum {
DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
};
// DWC2 registers
//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
if (rhport >= DWC2_CONTROLLER_COUNT) {
// user mis-configured, ignore and use first controller
rhport = 0;
}
return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
// DWC2 registers
#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
// Debug level for DWC2
#define DWC2_DEBUG 2
static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
typedef struct {
@ -508,18 +520,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
void print_dwc2_info(dwc2_regs_t* dwc2) {
// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
// use dwc2_info.py/md for bit-field value and comparison with other ports
volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
for (size_t i = 0; i < 5; i++) {
TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]);
}
TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]);
}
#endif
static void reset_core(dwc2_regs_t* dwc2) {
// reset core
@ -538,13 +538,10 @@ static void reset_core(dwc2_regs_t* dwc2) {
static bool phy_hs_supported(dwc2_regs_t* dwc2) {
(void) dwc2;
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// note: esp32 incorrect report its hs_phy_type as utmi
return false;
#elif !TUD_OPT_HIGH_SPEED
#if !TUD_OPT_HIGH_SPEED
return false;
#else
return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
#endif
}
@ -555,7 +552,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg |= GUSBCFG_PHYSEL;
// MCU specific PHY init before reset
dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// Reset core after selecting PHY
reset_core(dwc2);
@ -566,7 +563,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
// MCU specific PHY update post reset
dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// set max speed
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
@ -578,7 +575,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// De-select FS PHY
gusbcfg &= ~GUSBCFG_PHYSEL;
if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
// Select ULPI
@ -599,7 +596,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
// Set 16-bit interface if supported
if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
if (dwc2->ghwcfg4_bm.phy_data_width) {
gusbcfg |= GUSBCFG_PHYIF16;
}
}
// Apply config
@ -615,7 +614,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// - 9 if using 8-bit PHY interface
// - 5 if using 16-bit PHY interface
gusbcfg &= ~GUSBCFG_TRDT_Msk;
gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
dwc2->gusbcfg = gusbcfg;
// MCU specific PHY update post reset
@ -628,7 +627,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
dcfg |= DCFG_XCVRDLY;
}
@ -637,10 +636,17 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
static bool check_dwc2(dwc2_regs_t* dwc2) {
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
print_dwc2_info(dwc2);
// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
// Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports
volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
for (size_t i = 0; i < 5; i++) {
TU_LOG1("0x%08" PRIX32 ", ", p[i]);
}
TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
#endif
// For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
// For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
(void) dwc2;
#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;

36
src/portable/synopsys/dwc2/dwc2_esp32.h
View File

@ -38,29 +38,41 @@
#include "soc/periph_defs.h"
#include "soc/usb_wrap_struct.h"
#define DWC2_REG_BASE 0x60080000UL
#define DWC2_EP_MAX 7
#define DWC2_EP_IN_MAX 5
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
#define DWC2_FS_REG_BASE 0x60080000UL
#define DWC2_EP_MAX 7
static const dwc2_controller_t _dwc2_controller[] = {
{ .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 }
{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
};
static intr_handle_t usb_ih;
#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
#define DWC2_FS_REG_BASE 0x50040000UL
#define DWC2_HS_REG_BASE 0x50000000UL
#define DWC2_EP_MAX 16
// On ESP32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] = {
{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
};
#endif
static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)];
static void dcd_int_handler_wrap(void* arg) {
(void)arg;
dcd_int_handler(0);
const uint8_t rhport = (uint8_t)(uintptr_t) arg;
dcd_int_handler(rhport);
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
(void)rhport;
esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]);
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
(void)rhport;
esp_intr_free(usb_ih);
esp_intr_free(usb_ih[rhport]);
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
@ -71,7 +83,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
(void)dwc2;
(void)hs_phy_type;
// nothing to do
}
@ -79,7 +90,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
(void)dwc2;
(void)hs_phy_type;
// nothing to do
}

113
src/portable/synopsys/dwc2/dwc2_info.md
View File

@ -1,55 +1,58 @@
| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 |
|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 |
|:---------------------------|:----------------|:-------------|:--------------|:-----------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------|
| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
| - arch | 2 | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 |
| - point2point | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| - hs_phy_type | 1 | 0 | 0 | 3 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 |
| - fs_phy_type | 1 | 1 | 1 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 |
| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 |
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 |
| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| - phy_data_width | 0 | 2 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 |
| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 |
| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |

65
src/portable/synopsys/dwc2/dwc2_info.py
View File

@ -3,24 +3,22 @@ import ctypes
import pandas as pd
# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
# Note: FS is FullSpeed, HS is HighSpeed
dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
dwc2_reg_value = {
'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
'STM32F 407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
'STM32F 407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
'STM32F 412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
'STM32H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
'STM32L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
'STM32U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
'GD32VF103 FS': [0x1000, 0, 0, 0, 0, 0],
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
}
@ -50,9 +48,9 @@ class GHWCFG2(ctypes.LittleEndianStructure):
("enable_dynamic_fifo", ctypes.c_uint32, 1),
("mul_cpu_int", ctypes.c_uint32, 1),
("reserved21", ctypes.c_uint32, 1),
("nperiod_tx_q_depth", ctypes.c_uint32, 2),
("host_period_tx_q_depth", ctypes.c_uint32, 2),
("dev_token_q_depth", ctypes.c_uint32, 5),
("nptx_q_depth", ctypes.c_uint32, 2),
("ptx_q_depth", ctypes.c_uint32, 2),
("token_q_depth", ctypes.c_uint32, 5),
("otg_enable_ic_usb", ctypes.c_uint32, 1)
]
@ -70,31 +68,34 @@ class GHWCFG3(ctypes.LittleEndianStructure):
("otg_enable_hsic", ctypes.c_uint32, 1),
("battery_charger_support", ctypes.c_uint32, 1),
("lpm_mode", ctypes.c_uint32, 1),
("total_fifo_size", ctypes.c_uint32, 16)
("dfifo_depth", ctypes.c_uint32, 16)
]
class GHWCFG4(ctypes.LittleEndianStructure):
_fields_ = [
("num_dev_period_in_ep", ctypes.c_uint32, 4),
("power_optimized", ctypes.c_uint32, 1),
("partial_powerdown", ctypes.c_uint32, 1),
("ahb_freq_min", ctypes.c_uint32, 1),
("hibernation", ctypes.c_uint32, 1),
("reserved7", ctypes.c_uint32, 3),
("service_interval_mode", ctypes.c_uint32, 1),
("ipg_isoc_en", ctypes.c_uint32, 1),
("acg_enable", ctypes.c_uint32, 1),
("reserved13", ctypes.c_uint32, 1),
("utmi_phy_data_width", ctypes.c_uint32, 2),
("dev_ctrl_ep_num", ctypes.c_uint32, 4),
("iddg_filter_enabled", ctypes.c_uint32, 1),
("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
("a_valid_filter_enabled", ctypes.c_uint32, 1),
("b_valid_filter_enabled", ctypes.c_uint32, 1),
("extended_hibernation", ctypes.c_uint32, 1),
("reserved8", ctypes.c_uint32, 1),
("enhanced_lpm_support1", ctypes.c_uint32, 1),
("service_interval_flow", ctypes.c_uint32, 1),
("ipg_isoc_support", ctypes.c_uint32, 1),
("acg_support", ctypes.c_uint32, 1),
("enhanced_lpm_support", ctypes.c_uint32, 1),
("phy_data_width", ctypes.c_uint32, 2),
("ctrl_ep_num", ctypes.c_uint32, 4),
("iddg_filter", ctypes.c_uint32, 1),
("vbus_valid_filter", ctypes.c_uint32, 1),
("a_valid_filter", ctypes.c_uint32, 1),
("b_valid_filter", ctypes.c_uint32, 1),
("session_end_filter", ctypes.c_uint32, 1),
("dedicated_fifos", ctypes.c_uint32, 1),
("num_dev_in_eps", ctypes.c_uint32, 4),
("dma_desc_enable", ctypes.c_uint32, 1),
("dma_dynamic", ctypes.c_uint32, 1)
("dma_desc_dynamic", ctypes.c_uint32, 1)
]

6
src/portable/synopsys/dwc2/dwc2_stm32.h
View File

@ -142,7 +142,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
// - dwc2 3.30a (H5) use USB_HS_PHYC
// - dwc2 4.11a (U5) use femtoPHY
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
if (hs_phy_type == HS_PHY_TYPE_NONE) {
if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
// Enable on-chip FS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
@ -175,7 +175,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
#endif
// Enable on-chip HS PHY
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
#ifdef USB_HS_PHYC
// Enable UTMI HS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
@ -218,7 +218,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// MCU specific PHY update, it is called AFTER init() and core reset
static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// used to set turnaround time for fullspeed, nothing to do in highspeed mode
if (hs_phy_type == HS_PHY_TYPE_NONE) {
if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
uint32_t turnaround;

458
src/portable/synopsys/dwc2/dwc2_type.h
View File

@ -87,92 +87,222 @@ typedef struct
#endif
enum {
HS_PHY_TYPE_NONE = 0 , // not supported
HS_PHY_TYPE_UTMI , // internal PHY (mostly)
HS_PHY_TYPE_ULPI , // external PHY
HS_PHY_TYPE_UTMI_ULPI ,
GHWCFG2_OPMODE_HNP_SRP = 0,
GHWCFG2_OPMODE_SRP = 1,
GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
GHWCFG2_OPMODE_SRP_DEVICE = 3,
GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4,
GHWCFG2_OPMODE_SRP_HOST = 5,
GHWCFG2_OPMODE_NON_OTG_HOST = 6,
};
enum {
GHWCFG2_ARCH_SLAVE_ONLY = 0,
GHWCFG2_ARCH_EXTERNAL_DMA = 1,
GHWCFG2_ARCH_INTERNAL_DMA = 2,
};
enum {
FS_PHY_TYPE_NONE = 0, // not supported
FS_PHY_TYPE_DEDICATED,
FS_PHY_TYPE_UTMI,
FS_PHY_TYPE_ULPI,
GHWCFG2_HSPHY_NOT_SUPPORTED = 0,
GHWCFG2_HSPHY_UTMI = 1, // internal PHY (mostly)
GHWCFG2_HSPHY_ULPI = 2, // external PHY (mostly)
GHWCFG2_HSPHY_UTMI_ULPI = 3, // both
};
enum {
GHWCFG2_ARCH_SLAVE_ONLY = 0,
GHWCFG2_ARCH_EXTERNAL_DMA, // 1
GHWCFG2_ARCH_INTERNAL_DMA, // 2
GHWCFG2_FSPHY_NOT_SUPPORTED = 0,
GHWCFG2_FSPHY_DEDICATED = 1, // have dedicated FS PHY
GHWCFG2_FSPHY_UTMI = 2, // shared with UTMI+
GHWCFG2_FSPHY_ULPI = 3, // shared with ULPI
};
typedef struct TU_ATTR_PACKED
{
uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
uint32_t num_host_ch : 4; // Number of host channel
uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
uint32_t reserved21 : 1;
uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
enum {
GHWCFFG4_PHY_DATA_WIDTH_8 = 0,
GHWCFFG4_PHY_DATA_WIDTH_16 = 1,
GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable
};
//--------------------------------------------------------------------
// Register bitfield definitions
//--------------------------------------------------------------------
typedef struct TU_ATTR_PACKED {
uint32_t ses_req_scs : 1; // 0 Session request success
uint32_t ses_req : 1; // 1 Session request
uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable
uint32_t vbval_ov_val : 1; // 3 VBUS valid override value
uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable
uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value
uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable
uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value
uint32_t hng_scs : 1; // 8 Host negotiation success
uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request
uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable
uint32_t dev_hnp_en : 1; // 11 Device HNP enabled
uint32_t embedded_host_en : 1; // 12 Embedded host enable
uint32_t rsv13_14 : 2; // 13.14 Reserved
uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass
uint32_t cid_status : 1; // 16 Connector ID status
uint32_t dbnc_done : 1; // 17 Debounce done
uint32_t ases_valid : 1; // 18 A-session valid
uint32_t bses_valid : 1; // 19 B-session valid
uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0
uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host
uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger
uint32_t chirp_en : 1; // 27 Chirp detection enable
uint32_t rsv28_30 : 3; // 28.30: Reserved
uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY
} dwc2_gotgctl_t;
TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED {
uint32_t rsv0_1 : 2; // 0..1 Reserved
uint32_t ses_end_det : 1; // 2 Session end detected
uint32_t rsv3_7 : 5; // 3..7 Reserved
uint32_t srs_status_change : 1; // 8 Session request success status change
uint32_t hns_status_change : 1; // 9 Host negotiation success status change
uint32_t rsv10_16 : 7; // 10..16 Reserved
uint32_t hng_det : 1; // 17 Host negotiation detected
uint32_t adev_timeout_change : 1; // 18 A-device timeout change
uint32_t dbnc_done : 1; // 19 Debounce done
uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change
uint32_t rsv21_31 :11; // 21..31 Reserved
} dwc2_gotgint_t;
TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED {
uint32_t gintmask : 1; // 0 Global interrupt mask
uint32_t hbst_len : 4; // 1..4 Burst length/type
uint32_t dma_en : 1; // 5 DMA enable
uint32_t rsv6 : 1; // 6 Reserved
uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level
uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level
uint32_t rsv9_20 : 12; // 9.20: Reserved
uint32_t remote_mem_support : 1; // 21 Remote memory support
uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes
uint32_t ahb_single : 1; // 23 AHB single
uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian
uint32_t rsv25_31 : 7; // 25..31 Reserved
} dwc2_gahbcfg_t;
TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED {
uint32_t timeout_cal : 3; /* 0..2 Timeout calibration.
The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field
based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
- High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times
- Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */
uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits
uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI
uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit
uint32_t srp_capable : 1; // 8 SRP-capable
uint32_t hnp_capable : 1; // 9 HNP-capable
uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+
uint32_t rsv14 : 1; // 14 Reserved
uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs.
- 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit)
- 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */
uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
valid only when the FS serial transceiver is selected on the ULPI PHY. */
uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume
uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM
uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive
uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator
uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing
uint32_t indicator_complement : 1; // 23 Indicator complement
uint32_t indicator_pass_through : 1; // 24 Indicator pass through
uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable
uint32_t ic_usb_capable : 1; // 26 IC_USB Capable
uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control
uint32_t tx_end_delay : 1; // 28 TX end delay
uint32_t force_host_mode : 1; // 29 Force host mode
uint32_t force_dev_mode : 1; // 30 Force device mode
uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug
} dwc2_gusbcfg_t;
TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED {
uint32_t core_soft_rst : 1; // 0 Core Soft Reset
uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset
uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host)
uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush
uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush
uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush
uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number
uint32_t rsv11_28 :18; // 11..28 Reserved
uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a
uint32_t dma_req : 1; // 30 DMA Request
uint32_t ahb_idle : 1; // 31 AHB Idle
} dwc2_grstctl_t;
TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED {
uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode
uint32_t arch : 2; // 3..4 Slave/External/Internal DMA
uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split
uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0)
uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control)
uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel
uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled
uint32_t mul_cpu_int : 1; // 20 Multi-Processor Interrupt Enabled
uint32_t reserved21 : 1; // 21 reserved
uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30
uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation
} dwc2_ghwcfg2_t;
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED
{
uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
uint32_t otg_enable : 1; // 1 is OTG capable
uint32_t i2c_enable : 1; // I2C interface is available
uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
uint32_t battery_charger_support : 1; // support battery charger
uint32_t lpm_mode : 1; // LPC mode
typedef struct TU_ATTR_PACKED {
uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits)
uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits)
uint32_t otg_enable : 1; // 7 OTG capable
uint32_t i2c_enable : 1; // 8 I2C interface is available
uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available
uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count
uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset
uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller
uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
uint32_t battery_charger_support : 1; // s14 upport battery charger
uint32_t lpm_mode : 1; // 15 LPM mode
uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
}dwc2_ghwcfg3_t;
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
typedef struct TU_ATTR_PACKED
{
uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
uint32_t power_optimized : 1; // Partial Power Down Enabled
uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
uint32_t hibernation : 1; // Hibernation feature is enabled
uint32_t reserved7 : 3;
uint32_t service_interval_mode : 1; // Service Interval supported
uint32_t ipg_isoc_en : 1; // IPG ISOC supported
uint32_t acg_enable : 1; // ACG enabled
uint32_t reserved13 : 1;
uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
uint32_t iddg_filter_enabled : 1;
uint32_t vbus_valid_filter_enabled : 1;
uint32_t a_valid_filter_enabled : 1;
uint32_t b_valid_filter_enabled : 1;
uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
typedef struct TU_ATTR_PACKED {
uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints
uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled
uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz
uint32_t hibernation : 1; // 6 Hibernation feature is enabled
uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled
uint32_t reserved8 : 1; // 8 Reserved
uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1
uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported
uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported
uint32_t acg_support : 1; // 12 Active clock gating is supported
uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support
uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0
uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled
uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled
uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled
uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled
uint32_t session_end_filter : 1; // 24 Session End Filter Enabled
uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint
uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0
uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled
uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA
}dwc2_ghwcfg4_t;
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
// Host Channel
typedef struct
{
typedef struct {
volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
@ -184,8 +314,7 @@ typedef struct
} dwc2_channel_t;
// Endpoint IN
typedef struct
{
typedef struct {
volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
uint32_t reserved04; // 904
volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
@ -197,8 +326,7 @@ typedef struct
} dwc2_epin_t;
// Endpoint OUT
typedef struct
{
typedef struct {
volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
uint32_t reserved04; // B04
volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
@ -208,105 +336,107 @@ typedef struct
uint32_t reserved18[2]; // B18..B1C
} dwc2_epout_t;
typedef struct
{
//------------- Core Global -------------//
volatile uint32_t gotgctl; // 000 OTG Control and Status
volatile uint32_t gotgint; // 004 OTG Interrupt
volatile uint32_t gahbcfg; // 008 AHB Configuration
volatile uint32_t gusbcfg; // 00c USB Configuration
volatile uint32_t grstctl; // 010 Reset
volatile uint32_t gintsts; // 014 Interrupt
volatile uint32_t gintmsk; // 018 Interrupt Mask
volatile uint32_t grxstsr; // 01c Receive Status Debug Read
volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
volatile uint32_t grxfsiz; // 024 Receive FIFO Size
union {
volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
};
volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
volatile uint32_t gi2cctl; // 030 I2C Address
volatile uint32_t gpvndctl; // 034 PHY Vendor Control
union {
volatile uint32_t ggpio; // 038 General Purpose IO
volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
};
volatile uint32_t guid; // 03C User (Application programmable) ID
volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
union {
volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
volatile dwc2_ghwcfg2_t ghwcfg2_bm;
};
union {
volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
volatile dwc2_ghwcfg3_t ghwcfg3_bm;
};
union {
volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
volatile dwc2_ghwcfg4_t ghwcfg4_bm;
};
volatile uint32_t glpmcfg; // 054 Core LPM Configuration
volatile uint32_t gpwrdn; // 058 Power Down
volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
uint32_t reserved64[39]; // 064..0FF
volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
uint32_t reserved140[176]; // 140..3FF
//--------------------------------------------------------------------
// CSR Register Map
//--------------------------------------------------------------------
typedef struct {
//------------- Core Global -------------//
volatile uint32_t gotgctl; // 000 OTG Control and Status
volatile uint32_t gotgint; // 004 OTG Interrupt
volatile uint32_t gahbcfg; // 008 AHB Configuration
volatile uint32_t gusbcfg; // 00c USB Configuration
volatile uint32_t grstctl; // 010 Reset
volatile uint32_t gintsts; // 014 Interrupt
volatile uint32_t gintmsk; // 018 Interrupt Mask
volatile uint32_t grxstsr; // 01c Receive Status Debug Read
volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
volatile uint32_t grxfsiz; // 024 Receive FIFO Size
union {
volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
};
volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
volatile uint32_t gi2cctl; // 030 I2C Address
volatile uint32_t gpvndctl; // 034 PHY Vendor Control
union {
volatile uint32_t ggpio; // 038 General Purpose IO
volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
};
volatile uint32_t guid; // 03C User (Application programmable) ID
volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
union {
volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
volatile dwc2_ghwcfg2_t ghwcfg2_bm;
};
union {
volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
volatile dwc2_ghwcfg3_t ghwcfg3_bm;
};
union {
volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
volatile dwc2_ghwcfg4_t ghwcfg4_bm;
};
volatile uint32_t glpmcfg; // 054 Core LPM Configuration
volatile uint32_t gpwrdn; // 058 Power Down
volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
uint32_t reserved64[39]; // 064..0FF
volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
uint32_t reserved140[176]; // 140..3FF
//------------- Host -------------//
volatile uint32_t hcfg; // 400 Host Configuration
volatile uint32_t hfir; // 404 Host Frame Interval
volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
uint32_t reserved40c; // 40C
volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
volatile uint32_t haint; // 414 Host All Channels Interrupt
volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
uint32_t reserved420[8]; // 420..43F
volatile uint32_t hprt; // 440 Host Port Control and Status
uint32_t reserved444[47]; // 444..4FF
//------------ Host -------------//
volatile uint32_t hcfg; // 400 Host Configuration
volatile uint32_t hfir; // 404 Host Frame Interval
volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
uint32_t reserved40c; // 40C
volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
volatile uint32_t haint; // 414 Host All Channels Interrupt
volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
uint32_t reserved420[8]; // 420..43F
volatile uint32_t hprt; // 440 Host Port Control and Status
uint32_t reserved444[47]; // 444..4FF
//------------- Host Channel -------------//
dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
uint32_t reserved700[64]; // 700..7FF
//------------- Host Channel -------------//
dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
uint32_t reserved700[64]; // 700..7FF
//------------- Device -------------//
volatile uint32_t dcfg; // 800 Device Configuration
volatile uint32_t dctl; // 804 Device Control
volatile uint32_t dsts; // 808 Device Status (RO)
uint32_t reserved80c; // 80C
volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
volatile uint32_t daint; // 818 Device All Endpoints Interrupt
volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
volatile uint32_t dthrctl; // 830 Device threshold Control
volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk
volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
uint32_t reserved8c0[16]; // 8C0..8FF
//------------- Device -----------//
volatile uint32_t dcfg; // 800 Device Configuration
volatile uint32_t dctl; // 804 Device Control
volatile uint32_t dsts; // 808 Device Status (RO)
uint32_t reserved80c; // 80C
volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
volatile uint32_t daint; // 818 Device All Endpoints Interrupt
volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
volatile uint32_t dthrctl; // 830 Device threshold Control
volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk
volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
uint32_t reserved8c0[16]; // 8C0..8FF
//------------- Device Endpoint -------------//
dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
uint32_t reservedd00[64]; // D00..DFF
//------------- Device Endpoint -------------//
dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
uint32_t reservedd00[64]; // D00..DFF
//------------- Power Clock -------------//
volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
volatile uint32_t pcgctl1; // E04
uint32_t reservede08[126]; // E08..FFF
//------------- Power Clock -------------//
volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
volatile uint32_t pcgctl1; // E04
uint32_t reservede08[126]; // E08..FFF
//------------- FIFOs -------------//
// Word-accessed only using first pointer since it auto shift
volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
//------------- FIFOs -------------//
// Word-accessed only using first pointer since it auto shift
volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
} dwc2_regs_t;
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size");

1
src/tusb_option.h
View File

@ -123,6 +123,7 @@
#define OPT_MCU_ESP32C6 904 ///< Espressif ESP32-C6
#define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2
#define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2
#define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4
#define TUP_MCU_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU
// Dialog

5
test/hil/hil_test.py
View File

@ -464,6 +464,8 @@ def main():
"""
global verbose
duration = time.time()
parser = argparse.ArgumentParser()
parser.add_argument('config_file', help='Configuration JSON file')
parser.add_argument('-b', '--board', action='append', default=[], help='Boards to test, all if not specified')
@ -488,9 +490,10 @@ def main():
with Pool(processes=os.cpu_count()) as pool:
err_count = sum(pool.map(test_board, config_boards))
duration = time.time() - duration
print()
print("-" * 30)
print(f'Total failed: {err_count}')
print(f'Total failed: {err_count} in {duration:.1f}s')
print("-" * 30)
sys.exit(err_count)

11
tools/build.py
View File

@ -84,10 +84,13 @@ def cmake_board(board, toolchain):
# for espressif, we have to build example individually
all_examples = get_examples(family)
for example in all_examples:
rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board} -DMAX3421_HOST=1')
if rcmd.returncode == 0:
rcmd = run_cmd(f'cmake --build {build_dir}/{example}')
ret[0 if rcmd.returncode == 0 else 1] += 1
if build_utils.skip_example(example, board):
ret[2] += 1
else:
rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board}')
if rcmd.returncode == 0:
rcmd = run_cmd(f'cmake --build {build_dir}/{example}')
ret[0 if rcmd.returncode == 0 else 1] += 1
else:
rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel -DTOOLCHAIN={toolchain}')
if rcmd.returncode == 0:

44
tools/build_utils.py
View File

@ -13,33 +13,25 @@ def skip_example(example, board):
ex_dir = pathlib.Path('examples/') / example
bsp = pathlib.Path("hw/bsp")
if (bsp / board / "board.mk").exists():
# board without family
board_dir = bsp / board
family = ""
mk_contents = ""
else:
# board within family
board_dir = list(bsp.glob("*/boards/" + board))
if not board_dir:
# Skip unknown boards
return True
# board within family
board_dir = list(bsp.glob("*/boards/" + board))
if not board_dir:
# Skip unknown boards
return True
board_dir = list(board_dir)[0]
board_dir = list(board_dir)[0]
family_dir = board_dir.parent.parent
family = family_dir.name
family_dir = board_dir.parent.parent
family = family_dir.name
# family.mk
family_mk = family_dir / "family.mk"
mk_contents = family_mk.read_text()
# family.mk
family_mk = family_dir / "family.mk"
mk_contents = family_mk.read_text()
# Find the mcu, first in family mk then board mk
if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents:
board_mk = board_dir / "board.cmake"
board_mk = board_dir / "board.mk"
if not board_mk.exists():
board_mk = board_dir / "board.mk"
board_mk = board_dir / "board.cmake"
mk_contents = board_mk.read_text()
mcu = "NONE"
@ -49,18 +41,23 @@ def skip_example(example, board):
token = token.strip("\"")
_, opt_mcu = token.split("=")
mcu = opt_mcu[len("OPT_MCU_"):]
break
if "esp32s2" in token:
mcu = "ESP32S2"
break
if "esp32s3" in token:
mcu = "ESP32S3"
if mcu != "NONE":
break
# Skip all OPT_MCU_NONE these are WIP port
if mcu == "NONE":
return True
max3421_enabled = False
for line in mk_contents.splitlines():
if "MAX3421_HOST=1" in line or 'MAX3421_HOST 1' in line:
max3421_enabled = True
break
skip_file = ex_dir / "skip.txt"
only_file = ex_dir / "only.txt"
@ -74,6 +71,7 @@ def skip_example(example, board):
if only_file.exists():
onlys = only_file.read_text().split()
if not ("mcu:" + mcu in onlys or
("mcu:MAX3421" in onlys and max3421_enabled) or
"board:" + board in onlys or
"family:" + family in onlys):
return True