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synced 2025-03-18 16:21:18 +00:00
clean up
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402a5fee90
commit
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@ -462,11 +462,12 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
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// Control out complete
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if ( ep_int_status & BIT_(0) )
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{
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if (sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK)
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{
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// Setup received
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(void) sie_read(SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT+0, 1); // clear setup bit
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bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
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LPC_USB->USBEpIntClr = BIT_(0);
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if (is_setup)
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{
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uint8_t setup_packet[8];
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control_ep_read(setup_packet, 8); // TODO read before clear setup above
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@ -491,6 +492,7 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
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// Control In complete
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if ( ep_int_status & BIT_(1) )
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{
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LPC_USB->USBEpIntClr = BIT_(1);
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dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true);
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}
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}
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@ -516,11 +518,10 @@ static void bus_event_isr(uint8_t rhport)
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
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}
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// else
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// { // resume signal
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// dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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// }
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// }
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else
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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}
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}
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@ -539,16 +540,18 @@ void hal_dcd_isr(uint8_t rhport)
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if (dev_int_status & DEV_INT_ENDPOINT_SLOW_MASK)
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{
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uint32_t const ep_int_status = LPC_USB->USBEpIntSt & LPC_USB->USBEpIntEn;
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// Note clear USBEpIntClr will also clear the setup received bit --> clear after handle setup packet
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// Only clear USBEpIntClr 1 endpoint each, and should wait for CDFULL bit set
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control_xfer_isr(rhport, ep_int_status);
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// Note clear USBEpIntClr will also clear the setup received bit --> clear after handle setup packet
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LPC_USB->USBEpIntClr = ep_int_status;
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// For non-control only IN transfer is enabled
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for ( uint8_t ep_id = 3; ep_id < DCD_ENDPOINT_MAX; ep_id += 2 )
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{
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if ( BIT_TEST_(ep_int_status, ep_id) )
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{
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LPC_USB->USBEpIntClr = BIT_(ep_id);
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// Clear Ep interrupt for next DMA
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LPC_USB->USBEpIntEn &= ~BIT_(ep_id);
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@ -558,15 +561,29 @@ void hal_dcd_isr(uint8_t rhport)
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}
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// DMA transfer complete (RAM <-> EP) for Non-Control
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// OUT: USB transfer is complete
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// IN : UBS transfer is on-going -> enable EpIntEn to know when it is complete
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// OUT: USB transfer is fully complete
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// IN : UBS transfer is still on-going -> enable EpIntEn to know when it is complete
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uint32_t const dma_int_status = LPC_USB->USBDMAIntSt & LPC_USB->USBDMAIntEn;
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if (dma_int_status & DMA_INT_END_OF_XFER_MASK)
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{
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uint32_t const eot = LPC_USB->USBEoTIntSt;
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LPC_USB->USBEoTIntClr = eot; // acknowledge interrupt source
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normal_xfer_isr(rhport, eot);
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for ( uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++ )
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{
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if ( BIT_TEST_(eot, ep_id) )
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{
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if ( ep_id & 0x01 )
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{
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// IN
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LPC_USB->USBEpIntEn |= BIT_(ep_id);
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}else
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{
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// OUT
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dd_complete_isr(rhport, ep_id);
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}
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}
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}
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}
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// Errors
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