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https://github.com/hathach/tinyusb.git
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use endpoint pool for more flexible multiple devices support
This commit is contained in:
hathach
parent
09ceaa6cf3
commit
ecf2f91042
@ -165,22 +165,26 @@ enum {
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//--------------------------------------------------------------------+
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typedef struct {
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uint16_t packet_size;
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struct TU_ATTR_PACKED {
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uint8_t ep_dir : 1;
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uint8_t is_iso : 1;
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uint8_t data_toggle : 1;
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uint8_t xfer_queued : 1;
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uint8_t xfer_pending : 1;
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uint8_t xfer_complete : 1;
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};
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struct TU_ATTR_PACKED {
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uint8_t daddr : 4;
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uint8_t ep_num : 4;
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};
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uint16_t packet_size;
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uint16_t total_len;
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uint16_t xferred_len;
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uint8_t* buf;
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} hcd_ep_t;
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} max3421_ep_t;
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typedef struct {
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atomic_bool busy; // busy transferring
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atomic_flag busy; // busy transferring
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// cached register
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uint8_t sndbc;
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@ -192,15 +196,16 @@ typedef struct {
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volatile uint16_t frame_count;
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hcd_ep_t ep[8][2];
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max3421_ep_t ep0_addr0; // control endpoint for addr0
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max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL];
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OSAL_MUTEX_DEF(spi_mutexdef);
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#if OSAL_MUTEX_REQUIRED
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osal_mutex_t spi_mutex;
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#endif
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} max2341_data_t;
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} max3421_data_t;
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static max2341_data_t _hcd_data;
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static max3421_data_t _hcd_data;
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//--------------------------------------------------------------------+
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// API: SPI transfer with MAX3421E, must be implemented by application
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@ -211,7 +216,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
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void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
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//--------------------------------------------------------------------+
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//
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// SPI Helper
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//--------------------------------------------------------------------+
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static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
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@ -318,6 +323,44 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
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reg_write(rhport, SNDBC_ADDR, data, in_isr);
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}
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//--------------------------------------------------------------------+
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// Endpoint helper
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//--------------------------------------------------------------------+
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static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
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for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
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max3421_ep_t* ep = &_hcd_data.ep[i];
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// for control endpoint, skip direction check
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if ( daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) {
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return ep;
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}
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}
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return NULL;
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}
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// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint
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TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
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return find_ep_not_addr0(0, 0, 0);
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}
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// free all endpoints belong to device address
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static void free_ep(uint8_t daddr) {
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for (size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
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max3421_ep_t* ep = &_hcd_data.ep[i];
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if (ep->daddr == daddr) {
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tu_memclr(ep, sizeof(max3421_ep_t));
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}
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}
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}
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TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
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if (daddr == 0 && ep_num == 0) {
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return &_hcd_data.ep0_addr0;
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}else{
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return find_ep_not_addr0(daddr, ep_num, ep_dir);
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}
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}
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//--------------------------------------------------------------------+
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// Controller API
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@ -379,8 +422,8 @@ bool hcd_init(uint8_t rhport) {
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hcd_int_disable(rhport);
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TU_LOG2_INT(sizeof(hcd_ep_t));
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TU_LOG2_INT(sizeof(max2341_data_t));
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TU_LOG2_INT(sizeof(max3421_ep_t));
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TU_LOG2_INT(sizeof(max3421_data_t));
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tu_memclr(&_hcd_data, sizeof(_hcd_data));
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@ -478,22 +521,29 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
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//--------------------------------------------------------------------+
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// Open an endpoint
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
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bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
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(void) rhport;
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(void) dev_addr;
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(void) daddr;
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uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
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uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
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hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir];
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ep->packet_size = tu_edpt_packet_size(ep_desc);
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if (ep_desc->bEndpointAddress == 0) {
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_hcd_data.ep[0][1].packet_size = ep->packet_size;
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max3421_ep_t * ep;
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if (daddr == 0 && ep_num == 0) {
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ep = &_hcd_data.ep0_addr0;
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}else {
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ep = allocate_ep();
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TU_ASSERT(ep);
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ep->daddr = daddr;
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ep->ep_num = ep_num;
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ep->ep_dir = ep_dir;
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}
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ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
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if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
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ep->is_iso = 1;
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}
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ep->packet_size = tu_edpt_packet_size(ep_desc);
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return true;
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}
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@ -505,50 +555,55 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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uint8_t const ep_num = tu_edpt_number(ep_addr);
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uint8_t const ep_dir = tu_edpt_dir(ep_addr);
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hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
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max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
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TU_ASSERT(ep);
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ep->buf = buffer;
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ep->total_len = buflen;
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ep->xferred_len = 0;
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ep->xfer_complete = 0;
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ep->xfer_queued = 1;
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ep->xfer_pending = 1;
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peraddr_write(rhport, daddr, false);
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// carry out transfer if not busy
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// if ( atomic_flag_test_and_set(&_hcd_data.busy) )
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{
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peraddr_write(rhport, daddr, false);
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uint8_t hctl = 0;
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uint8_t hxfr = ep_num;
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uint8_t hctl = 0;
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uint8_t hxfr = ep_num;
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if ( ep->is_iso ) {
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hxfr |= HXFR_ISO;
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} else if ( ep_num == 0 ) {
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ep->data_toggle = 1;
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if ( buffer == NULL || buflen == 0 ) {
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// ZLP for ACK stage, use HS
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hxfr |= HXFR_HS;
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hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
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hxfr_write(rhport, hxfr, false);
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return true;
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if ( ep->is_iso ) {
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hxfr |= HXFR_ISO;
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} else if ( ep_num == 0 ) {
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ep->data_toggle = 1;
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if ( buffer == NULL || buflen == 0 ) {
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// ZLP for ACK stage, use HS
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hxfr |= HXFR_HS;
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hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
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hxfr_write(rhport, hxfr, false);
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return true;
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}
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}
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if ( 0 == ep_dir ) {
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// Page 12: Programming BULK-OUT Transfers
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
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uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
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fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
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sndbc_write(rhport, xact_len, false);
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hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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hxfr |= HXFR_OUT_NIN;
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} else {
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// Page 13: Programming BULK-IN Transfers
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hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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}
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reg_write(rhport, HCTL_ADDR, hctl, false);
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hxfr_write(rhport, hxfr, false);
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}
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if ( 0 == ep_dir ) {
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// Page 12: Programming BULK-OUT Transfers
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
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uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
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fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
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sndbc_write(rhport, xact_len, false);
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hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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hxfr |= HXFR_OUT_NIN;
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} else {
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// Page 13: Programming BULK-IN Transfers
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hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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}
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reg_write(rhport, HCTL_ADDR, hctl, false);
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hxfr_write(rhport, hxfr, false);
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return true;
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}
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@ -566,7 +621,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
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(void) rhport;
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hcd_ep_t* ep = &_hcd_data.ep[0][0];
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max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
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ep->total_len = 8;
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ep->xferred_len = 0;
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@ -624,7 +679,7 @@ static void handle_xfer_done(uint8_t rhport) {
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if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
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// SETUP or OUT transfer
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hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
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max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0);
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uint8_t xact_len;
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if ( hxfr_type & HXFR_SETUP) {
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@ -644,10 +699,15 @@ static void handle_xfer_done(uint8_t rhport) {
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hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
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}else {
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// more to transfer
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xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
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fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true);
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sndbc_write(rhport, xact_len, true);
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hxfr_write(rhport, _hcd_data.hxfr, true);
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}
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} else {
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// IN transfer: fifo data is already received in RCVDAV IRQ
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hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
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max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
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if ( hxfr_type & HXFR_HS ) {
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ep->xfer_complete = 1;
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@ -702,6 +762,10 @@ void hcd_int_handler(uint8_t rhport) {
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if (speed == TUSB_SPEED_INVALID) {
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hcd_event_device_remove(rhport, true);
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}else {
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// FIXME multiple MAX3421 rootdevice address is not 1
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uint8_t const daddr = 1;
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free_ep(daddr);
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hcd_event_device_attach(rhport, true);
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}
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}
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@ -710,8 +774,8 @@ void hcd_int_handler(uint8_t rhport) {
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// not call this handler again. So we need to loop until all IRQ are cleared
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while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
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if ( hirq & HIRQ_RCVDAV_IRQ ) {
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uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
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uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
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uint8_t xact_len;
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// RCVDAV_IRQ can trigger 2 times (dual buffered)
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