diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h index 7841ec8b8..ba663d040 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.h +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -31,36 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED #define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_04_PIN_08 // D12 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, - { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - - // USB HS - { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, - { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - - // ETM Trace - #ifdef TRACE_ETM - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - #endif -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld deleted file mode 100644 index ba15588e6..000000000 --- a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld +++ /dev/null @@ -1,25 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -/* Board has bootloader */ -FLASH_IMAGE_START = 0x10000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 33d381850..90afbdef3 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -2,62 +2,61 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif + extern "C" { + #endif -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) + #define BSP_CFG_PFS_PROTECT ((1)) -#define BSP_CFG_PFS_PROTECT ((1)) + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 6845183db..e532478f8 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (176) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index d5428540f..c01219377 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,80 +5,80 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M5 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -146,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -166,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -186,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -213,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -232,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -267,118 +267,123 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h index 0eb5e0516..91b9de11e 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h @@ -1,37 +1,35 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CLOCK_CFG_H_ #define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/linker/gcc/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld similarity index 78% rename from hw/bsp/ra/linker/gcc/fsp.ld rename to hw/bsp/ra/boards/portenta_c33/script/fsp.ld index 453d46f24..627ffe4d9 100644 --- a/hw/bsp/ra/linker/gcc/fsp.ld +++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld @@ -1,3 +1,9 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + /* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ /* XIP_SECONDARY_SLOT_IMAGE = 1; @@ -14,8 +20,6 @@ ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0; -NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0; RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; @@ -32,20 +36,21 @@ PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE) USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); __bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; __bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; __bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; __bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; __bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; __bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; __bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH; + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; __bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; @@ -55,7 +60,7 @@ __bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : __bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); __bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; @@ -67,30 +72,34 @@ FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; /* Define memory regions. */ MEMORY { - ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34 - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH } /* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) +GROUP(libgcc.a libc.a libm.a) /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -144,27 +153,6 @@ ENTRY(Reset_Handler) SECTIONS { - /* Initialized ITCM data. */ - .itcm_data : - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start__ = .; - - KEEP(*(.itcm_data*)) - - /* All ITCM data end */ - __itcm_data_end__ = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192); - } > ITCM - .text : { __tz_FLASH_S = ABSOLUTE(FLASH_START); @@ -177,17 +165,17 @@ SECTIONS KEEP(*(.application_vectors*)) __Vectors_End = .; + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) - /* Reserving 0x100 bytes of space for ROM registers. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; - /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ - . = ALIGN(128); KEEP(*(.mcuboot_sce9_key*)) *(.text*) @@ -233,16 +221,54 @@ SECTIONS __Vectors_Size = __Vectors_End - __Vectors; - .ARM.extab : + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; __exidx_start = .; - .ARM.exidx : + /DISCARD/ : { + *(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH + } __exidx_end = .; /* To copy multiple ROM to RAM sections, @@ -337,50 +363,76 @@ SECTIONS } > RAM AT > FLASH - /* Start address of the initial values for .dtcm_data. */ - __dtcm_data_init_start = __etext + __data_end__ - __data_start__; + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); /* Initialized DTCM data. */ - .dtcm_data : + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) { /* Start of DTCM Secure Trustzone region. */ __tz_DTCM_S = ABSOLUTE(DTCM_START); /* Initialized DTCM data start */ - __dtcm_data_start__ = .; + __dtcm_data_start = .; KEEP(*(.dtcm_data*)) - /* Initialized DTCM data end */ - __dtcm_data_end__ = .; - } > DTCM AT > FLASH + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; /* Uninitialized DTCM data. */ - .dtcm_noinit (NOLOAD): + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : { /* Uninitialized DTCM data start */ - __dtcm_noinit_start = .; + __dtcm_bss_start = .; - KEEP(*(.dtcm_noinit*)) + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); /* Uninitialized DTCM data end */ - __dtcm_noinit_end = .; + __dtcm_bss_end = .; /* * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192); + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); } > DTCM - /* TrustZone Secure Gateway Stubs Section. */ + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); - /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */ - /* 1. Get the address to the next block after the .data section in FLASH. */ - DATA_END = LOADADDR(.data) + SIZEOF(.data); - /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024); - /* 3. Manually specify the start location for .gnu.sgstubs */ + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) { __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); @@ -407,8 +459,8 @@ SECTIONS __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__); - .qspi_non_retentive : AT (__qspi_flash_code_addr__) + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) { __qspi_non_retentive_start__ = .; KEEP(*(.qspi_non_retentive*)) @@ -456,8 +508,8 @@ SECTIONS __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__) + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) { __ospi_device_0_non_retentive_start__ = .; KEEP(*(.ospi_device_0_non_retentive*)) @@ -486,8 +538,8 @@ SECTIONS __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__) + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) { __ospi_device_1_non_retentive_start__ = .; KEEP(*(.ospi_device_1_non_retentive*)) @@ -527,7 +579,6 @@ SECTIONS { . = ALIGN(8); __HeapBase = .; - PROVIDE(end = .); /* Place the STD heap here. */ KEEP(*(.heap)) __HeapLimit = .; @@ -615,7 +666,6 @@ SECTIONS __ID_Code_End = .; } > ID_CODE - /* Symbol required for RA Configuration tool. */ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); diff --git a/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld new file mode 100644 index 000000000..74c648329 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld @@ -0,0 +1,25 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x80000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x68000000; + OSPI_DEVICE_0_LENGTH = 0x8000000; + OSPI_DEVICE_1_START = 0x70000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; + +/* Board has bootloader */ +FLASH_IMAGE_START = 0x10000; diff --git a/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml new file mode 100644 index 000000000..fcc9d711d --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml @@ -0,0 +1,240 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.5.6.0.pack + + + Board support package for R7FA6M5BH3CFC + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - FSP Data + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - Events + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/linker/gcc/ra2a1.ld b/hw/bsp/ra/linker/gcc/ra2a1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra2a1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld deleted file mode 100644 index 7b3a63fbe..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m3.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x20000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x100000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld deleted file mode 100644 index 91d27f74c..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x1FFE0000; -RAM_LENGTH = 0x40000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x80000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x0100A150; -ID_CODE_LENGTH = 0x10; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld deleted file mode 100644 index af747fd9b..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m5.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -INCLUDE fsp.ld