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https://github.com/hathach/tinyusb.git
synced 2025-03-25 23:38:06 +00:00
clean up ehci warnings
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hathach
parent
67d6d753d6
commit
def20ce35b
@ -74,7 +74,7 @@ uint32_t hcd_ehci_register_addr(uint8_t rhport)
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//--------------------------------------------------------------------+
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static inline ehci_link_t* get_period_head(uint8_t rhport, uint8_t interval_ms)
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{
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(uint8_t) rhport;
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(void) rhport;
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return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
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}
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@ -95,32 +95,29 @@ static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
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}
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static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
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static inline ehci_qhd_t* qhd_find_free (void);
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static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
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static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr);
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static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
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static inline ehci_qhd_t* qhd_find_free (void);
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static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
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// determine if a queue head has bus-related error
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static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
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static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
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{
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return ( p_qhd->qtd_overlay.buffer_err ||p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err );
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return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err);
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//p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
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}
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static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
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static void qhd_init (ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
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static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd ) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) ATTR_ALWAYS_INLINE;
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static inline void qtd_remove_1st_from_qhd(ehci_qhd_t *p_qhd) ATTR_ALWAYS_INLINE;
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static inline ehci_qtd_t* qtd_find_free (void);
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static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
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static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
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static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
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static void qtd_init (ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes);
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static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) ATTR_ALWAYS_INLINE;
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static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer) ATTR_PURE ATTR_ALWAYS_INLINE;
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static ehci_link_t* list_find_previous_item(ehci_link_t* p_head, ehci_link_t* p_current);
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static bool list_remove_qhd(ehci_link_t* p_head, ehci_link_t* p_remove);
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static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
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static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
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static bool ehci_init(uint8_t hostid);
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static bool ehci_init (uint8_t hostid);
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//--------------------------------------------------------------------+
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// HCD API
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@ -131,21 +128,25 @@ bool hcd_init(void)
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return ehci_init(TUH_OPT_RHPORT);
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}
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void hcd_port_reset(uint8_t hostid)
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void hcd_port_reset(uint8_t rhport)
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{
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(void) rhport;
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ehci_registers_t* regs = ehci_data.regs;
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regs->portsc_bm.port_enabled = 0; // disable port before reset
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regs->portsc_bm.port_reset = 1;
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}
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bool hcd_port_connect_status(uint8_t hostid)
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bool hcd_port_connect_status(uint8_t rhport)
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{
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(void) rhport;
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return ehci_data.regs->portsc_bm.current_connect_status;
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}
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tusb_speed_t hcd_port_speed_get(uint8_t hostid)
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tusb_speed_t hcd_port_speed_get(uint8_t rhport)
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{
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(void) rhport;
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return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
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}
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@ -278,17 +279,16 @@ static bool ehci_init(uint8_t hostid)
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return true;
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}
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static tusb_error_t hcd_controller_stop(uint8_t hostid)
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static void hcd_controller_stop(uint8_t rhport)
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{
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(void) rhport;
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ehci_registers_t* regs = ehci_data.regs;
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regs->command_bm.run_stop = 0;
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tu_timeout_t timeout;
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tu_timeout_set(&timeout, 2); // USB Spec: controller has to stop within 16 uframe = 2 frames
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while( regs->status_bm.hc_halted == 0 && !tu_timeout_expired(&timeout)) {}
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return tu_timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
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// USB Spec: controller has to stop within 16 uframe = 2 frames
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while( regs->status_bm.hc_halted == 0 ) {}
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}
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//--------------------------------------------------------------------+
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@ -296,6 +296,8 @@ static tusb_error_t hcd_controller_stop(uint8_t hostid)
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//--------------------------------------------------------------------+
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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(void) rhport;
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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@ -326,10 +328,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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(void) rhport;
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ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
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ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd;
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qtd_init(td, setup_packet, 8);
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qtd_init(td, (void*) setup_packet, 8);
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td->pid = EHCI_PID_SETUP;
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td->int_on_complete = 1;
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td->next.terminate = 1;
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@ -349,6 +353,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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//--------------------------------------------------------------------+
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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// TODO not support ISO yet
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TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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@ -400,7 +406,7 @@ bool hcd_pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], ui
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{
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//------------- set up QTD -------------//
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ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
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ehci_qtd_t *p_qtd = qtd_find_free(dev_addr);
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ehci_qtd_t *p_qtd = qtd_find_free();
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TU_ASSERT(p_qtd);
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@ -507,7 +513,6 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
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static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
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{
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uint8_t max_loop = 0;
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ehci_qhd_t *p_qhd = async_head;
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do
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{
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@ -516,9 +521,7 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
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qhd_xfer_complete_isr(p_qhd);
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}
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p_qhd = qhd_next(p_qhd);
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max_loop++;
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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// TODO abstract max loop guard for async
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}while(p_qhd != async_head); // async list traversal, stop if loop around
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}
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static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
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@ -560,8 +563,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
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{
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if ( (p_qhd->dev_addr != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
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qhd_has_xact_error(p_qhd) )
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{ // current qhd has error in transaction
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tusb_xfer_type_t const xfer_type = qhd_get_xfer_type(p_qhd);
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{
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// current qhd has error in transaction
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xfer_result_t error_event;
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// no error bits are set, endpoint is halted due to STALL
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@ -598,27 +601,23 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
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static void xfer_error_isr(uint8_t hostid)
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{
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//------------- async list -------------//
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uint8_t max_loop = 0;
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ehci_qhd_t * const async_head = qhd_async_head(hostid);
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ehci_qhd_t *p_qhd = async_head;
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do
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{
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qhd_xfer_error_isr( p_qhd );
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p_qhd = qhd_next(p_qhd);
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max_loop++;
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}while(p_qhd != async_head && max_loop < HCD_MAX_ENDPOINT*CFG_TUSB_HOST_DEVICE_MAX); // async list traversal, stop if loop around
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}while(p_qhd != async_head); // async list traversal, stop if loop around
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//------------- TODO refractor period list -------------//
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uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
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for (uint8_t interval_ms=1; interval_ms <= EHCI_FRAMELIST_SIZE; interval_ms *= 2)
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{
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uint8_t period_max_loop = 0;
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ehci_link_t next_item = * get_period_head(hostid, interval_ms);
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// TODO abstract max loop guard for period
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while( !next_item.terminate &&
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!(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
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period_max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUSB_HOST_DEVICE_MAX)
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!(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) )
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{
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switch ( next_item.type )
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{
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@ -637,7 +636,6 @@ static void xfer_error_isr(uint8_t hostid)
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}
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next_item = *list_next(&next_item);
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period_max_loop++;
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}
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}
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}
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@ -708,12 +706,6 @@ static inline ehci_qhd_t* qhd_find_free (void)
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return NULL;
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}
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static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd)
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{
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return ( p_qhd->ep_number == 0 ) ? TUSB_XFER_CONTROL :
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( p_qhd->int_smask != 0 ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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}
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static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd)
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{
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return (ehci_qhd_t*) tu_align32(p_qhd->next.address);
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@ -736,7 +728,7 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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}
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//------------- TD helper -------------//
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static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr)
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static inline ehci_qtd_t* qtd_find_free(void)
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{
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for (uint32_t i=0; i<HCD_MAX_XFER; i++)
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{
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@ -104,9 +104,9 @@ void hcd_int_disable(uint8_t rhport);
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// PORT API
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/// return the current connect status of roothub port
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bool hcd_port_connect_status(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
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bool hcd_port_connect_status(uint8_t hostid);
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void hcd_port_reset(uint8_t hostid);
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tusb_speed_t hcd_port_speed_get(uint8_t hostid) ATTR_PURE ATTR_WARN_UNUSED_RESULT; // TODO make inline if possible
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tusb_speed_t hcd_port_speed_get(uint8_t hostid);
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// HCD closs all opened endpoints belong to this device
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void hcd_device_remove(uint8_t rhport, uint8_t dev_addr);
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