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https://github.com/hathach/tinyusb.git
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restructure, add hcd endpoint, xfer to minimize footprint for managing xfer.
This commit is contained in:
hathach
parent
f953b6bf92
commit
c93d3eda5f
@ -34,20 +34,35 @@
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#include "host/hcd.h"
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#include "dwc2_common.h"
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// Max number of endpoints application can open
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// Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX
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#ifndef CFG_TUH_DWC2_ENDPOINT_MAX
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#define CFG_TUH_DWC2_ENDPOINT_MAX 16
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#endif
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#define DWC2_CHANNEL_COUNT_MAX 16 // absolute max channel count
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#define DWC2_CHANNEL_COUNT(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX)
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TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index");
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enum {
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HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE
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};
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enum {
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HCD_XFER_ERROR_MAX = 3
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};
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enum {
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HCD_XFER_STATE_UNALLOCATED = 0,
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HCD_XFER_STATE_ACTIVE = 1,
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HCD_XFER_STATE_DISABLING = 2,
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};
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//--------------------------------------------------------------------
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//
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//--------------------------------------------------------------------
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// Host driver struct for each opened endpoint
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// When making an usb transfer, we will find an inactive channel and use it by enabled haintmsk. When the transfer is
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// complete, haintmsk will be cleared, and channel is deactivated/deallocated.
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typedef struct {
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union {
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uint32_t hcchar;
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@ -58,20 +73,26 @@ typedef struct {
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dwc2_channel_split_t hcsplt_bm;
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};
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uint8_t next_data_toggle;
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// uint8_t resv[3];
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} hcd_endpoint_t;
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// Additional info for each channel when it is active
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typedef struct {
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volatile uint8_t state;
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volatile bool pending_data;
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uint8_t err_count;
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uint8_t* buffer;
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uint16_t total_bytes;
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uint8_t next_data_toggle;
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volatile bool pending_data;
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} hcd_pipe_t;
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} hcd_xfer_t;
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typedef struct {
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hcd_pipe_t pipe[CFG_TUH_DWC2_ENDPOINT_MAX];
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hcd_xfer_t xfer[DWC2_CHANNEL_COUNT_MAX];
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hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX];
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} hcd_data_t;
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hcd_data_t _hcd_data;
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#define DWC2_CHANNEL_MAX(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, 16)
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//--------------------------------------------------------------------
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//
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//--------------------------------------------------------------------
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@ -95,11 +116,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
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return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
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}
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// Check if channel is periodic (interrupt/isochronous)
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TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) {
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return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS;
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}
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TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) {
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if (is_period) {
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return dwc2->hptxsts_bm.req_queue_available;
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@ -108,40 +124,49 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_
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}
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}
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// Check if channel is periodic (interrupt/isochronous)
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TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) {
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return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS;
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}
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// Find a free channel for new transfer
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TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) {
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const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2);
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TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) {
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const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
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for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
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// haintmsk bit enabled means channel is currently in use
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if (!tu_bit_test(dwc2->haintmsk, ch_id)) {
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hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
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if (HCD_XFER_STATE_UNALLOCATED == xfer->state) {
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tu_memclr(xfer, sizeof(hcd_xfer_t));
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xfer->state = HCD_XFER_STATE_ACTIVE;
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return ch_id;
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}
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}
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return TUSB_INDEX_INVALID_8;
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}
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// Find currently enabled/active channel associated with a pipe
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TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled_by_pipe(dwc2_regs_t* dwc2, const hcd_pipe_t* pipe) {
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const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2);
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TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) {
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(void) dwc2;
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_hcd_data.xfer[ch_id].state = HCD_XFER_STATE_UNALLOCATED;
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}
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// Find currently enabled channel. Note: EP0 is bidirectional
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TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
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const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
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for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
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if (tu_bit_test(dwc2->haintmsk, ch_id)) {
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if (_hcd_data.xfer[ch_id].state != HCD_XFER_STATE_UNALLOCATED) {
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const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm;
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if (hcchar_bm.dev_addr == pipe->hcchar_bm.dev_addr &&
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hcchar_bm.ep_num == pipe->hcchar_bm.ep_num &&
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(hcchar_bm.ep_num == 0 || hcchar_bm.ep_dir == pipe->hcchar_bm.ep_dir)) {
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if (hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num && (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) {
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return ch_id;
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}
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}
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}
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return TUSB_INDEX_INVALID_8;
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}
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// Find a pipe that is opened previously with hcd_edpt_open()
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TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
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// Find a endpoint that is opened previously with hcd_edpt_open()
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// Note: EP0 is bidirectional
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TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
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for (uint8_t i = 0; i < (uint8_t)CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
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const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm;
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// find enabled pipe: note EP0 is bidirectional
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const dwc2_channel_char_t* hcchar_bm = &_hcd_data.edpt[i].hcchar_bm;
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if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr &&
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hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) {
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return i;
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@ -150,12 +175,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened(uint8_t dev_addr, u
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return TUSB_INDEX_INVALID_8;
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}
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// Find a pipe that is opened previously with hcd_edpt_open() and associated with a channel
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TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened_by_channel(const dwc2_channel_t* channel) {
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const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm;
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return pipe_find_opened(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir);
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}
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//--------------------------------------------------------------------
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//
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//--------------------------------------------------------------------
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@ -356,9 +375,9 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
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void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
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(void) rhport;
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for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
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hcd_pipe_t* pipe = &_hcd_data.pipe[i];
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if (pipe->hcchar_bm.enable && pipe->hcchar_bm.dev_addr == dev_addr) {
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tu_memclr(pipe, sizeof(hcd_pipe_t));
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hcd_endpoint_t* edpt = &_hcd_data.edpt[i];
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if (edpt->hcchar_bm.enable && edpt->hcchar_bm.dev_addr == dev_addr) {
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tu_memclr(edpt, sizeof(hcd_endpoint_t));
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}
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}
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}
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@ -368,18 +387,18 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
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//--------------------------------------------------------------------+
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// Open an endpoint
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) {
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) {
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(void) rhport;
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//dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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hcd_devtree_info_t devtree_info;
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hcd_devtree_get_info(dev_addr, &devtree_info);
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// find a free pipe
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// find a free endpoint
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for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) {
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hcd_pipe_t* pipe = &_hcd_data.pipe[i];
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dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm;
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dwc2_channel_split_t* hcsplt_bm = &pipe->hcsplt_bm;
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hcd_endpoint_t* edpt = &_hcd_data.edpt[i];
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dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm;
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dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm;
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if (hcchar_bm->enable == 0) {
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hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep);
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@ -400,7 +419,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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hcsplt_bm->split_compl = 0;
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hcsplt_bm->split_en = 0;
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pipe->next_data_toggle = HCTSIZ_PID_DATA0;
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edpt->next_data_toggle = HCTSIZ_PID_DATA0;
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return true;
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}
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@ -412,48 +431,56 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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const uint8_t ep_num = tu_edpt_number(ep_addr);
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const uint8_t ep_dir = tu_edpt_dir(ep_addr);
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uint8_t pipe_id = pipe_find_opened(dev_addr, ep_num, ep_dir);
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TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe
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hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
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dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm;
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uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
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TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
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hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
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dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm;
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uint8_t ch_id = channel_alloc(dwc2);
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TU_ASSERT(ch_id < 16); // all channel are in used
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hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
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uint8_t ch_id = channel_find_free(dwc2);
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TU_ASSERT(ch_id < 16); // all channel are in use
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dwc2->haintmsk |= TU_BIT(ch_id);
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dwc2_channel_t* channel = &dwc2->channel[ch_id];
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uint32_t hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL |
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HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR;
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if (ep_dir == TUSB_DIR_IN) {
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hcintmsk |= HCINT_NAK;
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uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR;
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if (dma_host_enabled(dwc2)) {
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TU_ASSERT(false); // not yet supported
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} else {
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if (hcchar_bm->ep_dir == TUSB_DIR_OUT) {
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hcintmsk |= HCINT_NYET;
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} else {
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hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR;
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}
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}
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channel->hcintmsk = hcintmsk;
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uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size);
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if (packet_count == 0) {
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packet_count = 1; // zero length packet still count as 1
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}
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channel->hctsiz = (pipe->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen;
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channel->hctsiz = (edpt->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen;
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// Control transfer always start with DATA1 for data and status stage. May has issue with ZLP
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if (pipe->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) {
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pipe->next_data_toggle = HCTSIZ_PID_DATA1;
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if (edpt->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) {
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edpt->next_data_toggle = HCTSIZ_PID_DATA1;
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} else {
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pipe->next_data_toggle = HCTSIZ_PID_DATA0;
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edpt->next_data_toggle = HCTSIZ_PID_DATA0;
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}
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// TODO support split transaction
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channel->hcsplt = pipe->hcsplt;
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channel->hcsplt = edpt->hcsplt;
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hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame
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hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction
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channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet
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channel->hcchar = edpt->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet
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pipe->buffer = buffer;
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pipe->total_bytes = buflen;
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xfer->buffer = buffer;
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xfer->total_bytes = buflen;
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if (dma_host_enabled(dwc2)) {
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channel->hcdma = (uint32_t) buffer;
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@ -466,15 +493,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only
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// call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically.
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if (ep_dir == TUSB_DIR_IN) {
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pipe->pending_data = true;
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xfer->pending_data = true;
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TU_ASSERT(request_queue_avail(dwc2, is_period));
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channel->hcchar |= HCCHAR_CHENA;
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} else {
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channel->hcchar |= HCCHAR_CHENA;
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if (buflen > 0) {
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// To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly.
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// To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly
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// And write packet in the interrupt handler
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pipe->pending_data = true;
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xfer->pending_data = true;
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dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY);
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}
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}
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@ -487,36 +514,37 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// Return true if a queued transfer is aborted, false if there is no transfer to abort
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bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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const uint8_t ep_num = tu_edpt_number(ep_addr);
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const uint8_t ep_dir = tu_edpt_dir(ep_addr);
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const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir);
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TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX);
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hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
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const uint8_t pipe_id = pipe_find_opened(dev_addr, tu_edpt_number(ep_addr), tu_edpt_dir(ep_addr));
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TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX);
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hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
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hcd_int_disable(rhport);
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// hcd_int_disable(rhport);
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// Find enabled channeled and disable it, channel will be de-allocated in the interrupt handler
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const uint8_t ch_id = channel_find_enabled_by_pipe(dwc2, pipe);
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const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir);
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if (ch_id < 16) {
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dwc2_channel_t* channel = &dwc2->channel[ch_id];
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// disable also require request queue
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if (request_queue_avail(dwc2, channel_is_periodic(pipe->hcchar_bm))) {
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if (request_queue_avail(dwc2, channel_is_periodic(edpt->hcchar_bm))) {
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channel->hcchar |= HCCHAR_CHDIS;
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} else {
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TU_BREAKPOINT();
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}
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}
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hcd_int_enable(rhport);
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// hcd_int_enable(rhport);
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return true;
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}
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|
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// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) {
|
||||
uint8_t pipe_id = pipe_find_opened(dev_addr, 0, TUSB_DIR_OUT);
|
||||
TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe
|
||||
hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
|
||||
pipe->next_data_toggle = HCTSIZ_PID_SETUP;
|
||||
uint8_t ep_id = edpt_find_opened(dev_addr, 0, TUSB_DIR_OUT);
|
||||
TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened endpoint
|
||||
hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id];
|
||||
edpt->next_data_toggle = HCTSIZ_PID_SETUP;
|
||||
|
||||
return hcd_edpt_xfer(rhport, dev_addr, 0, (uint8_t*)(uintptr_t) setup_packet, 8);
|
||||
}
|
||||
@ -546,16 +574,14 @@ static void handle_rxflvl_irq(uint8_t rhport) {
|
||||
case GRXSTS_PKTSTS_RX_DATA: {
|
||||
// In packet received
|
||||
const uint16_t byte_count = grxstsp_bm.byte_count;
|
||||
const uint8_t pipe_id = pipe_find_opened_by_channel(channel);
|
||||
TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, );
|
||||
hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
|
||||
hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
|
||||
|
||||
dfifo_read_packet(dwc2, pipe->buffer, byte_count);
|
||||
pipe->buffer += byte_count;
|
||||
dfifo_read_packet(dwc2, xfer->buffer, byte_count);
|
||||
xfer->buffer += byte_count;
|
||||
|
||||
// short packet, minus remaining bytes (xfer_size)
|
||||
if (byte_count < channel->hctsiz_bm.xfer_size) {
|
||||
pipe->total_bytes -= channel->hctsiz_bm.xfer_size;
|
||||
xfer->total_bytes -= channel->hctsiz_bm.xfer_size;
|
||||
}
|
||||
|
||||
break;
|
||||
@ -644,58 +670,89 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in
|
||||
dwc2->hprt = hprt; // clear interrupt
|
||||
}
|
||||
|
||||
// DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER
|
||||
// if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) {
|
||||
// result = XFER_RESULT_FAILED;
|
||||
// }
|
||||
void handle_channel_irq(uint8_t rhport, bool in_isr) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
for (uint8_t ch_id = 0; ch_id < 32; ch_id++) {
|
||||
const bool is_dma = dma_host_enabled(dwc2);
|
||||
const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
|
||||
|
||||
for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { //
|
||||
if (tu_bit_test(dwc2->haint, ch_id)) {
|
||||
dwc2_channel_t* channel = &dwc2->channel[ch_id];
|
||||
hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
|
||||
|
||||
uint32_t hcint = channel->hcint;
|
||||
hcint &= channel->hcintmsk;
|
||||
|
||||
dwc2_channel_char_t hcchar_bm = channel->hcchar_bm;
|
||||
xfer_result_t result = XFER_RESULT_INVALID; // invalid means transfer is not complete
|
||||
xfer_result_t result = XFER_RESULT_INVALID; // invalid means not DONE
|
||||
|
||||
if (hcint & HCINT_XFER_COMPLETE) {
|
||||
result = XFER_RESULT_SUCCESS;
|
||||
}
|
||||
if (hcint & HCINT_STALL) {
|
||||
result = XFER_RESULT_STALLED;
|
||||
}
|
||||
// DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER
|
||||
// if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) {
|
||||
// result = XFER_RESULT_FAILED;
|
||||
// }
|
||||
const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR |
|
||||
HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR);
|
||||
if (xact_err) {
|
||||
result = XFER_RESULT_FAILED;
|
||||
}
|
||||
if (is_dma) {
|
||||
|
||||
if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) {
|
||||
// Channel halted without error, this is a response to channel disable
|
||||
result = XFER_RESULT_INVALID;
|
||||
}
|
||||
} else {
|
||||
if (hcint & HCINT_XFER_COMPLETE) {
|
||||
result = XFER_RESULT_SUCCESS;
|
||||
channel->hcintmsk &= ~HCINT_ACK;
|
||||
channel_dealloc(dwc2, ch_id);
|
||||
} else if (hcint & HCINT_STALL) {
|
||||
result = XFER_RESULT_STALLED;
|
||||
channel->hcintmsk |= HCINT_CHANNEL_HALTED;
|
||||
channel->hcchar_bm.disable = 1;
|
||||
} else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) {
|
||||
if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
|
||||
// rewind buffer
|
||||
} else {
|
||||
if (hcint & HCINT_NAK) {
|
||||
// NAK received, re-enable channel if request queue is available
|
||||
TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), );
|
||||
channel->hcchar |= HCCHAR_CHENA;
|
||||
}
|
||||
}
|
||||
|
||||
if (hcint & HCINT_NAK) {
|
||||
// NAK received, re-enable channel if request queue is available
|
||||
result = XFER_RESULT_INVALID;
|
||||
TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), );
|
||||
channel->hcchar |= HCCHAR_CHENA;
|
||||
}
|
||||
// unmask halted
|
||||
// disable channel
|
||||
if (hcint & HCINT_XACT_ERR) {
|
||||
xfer->err_count++;
|
||||
channel->hcintmsk |= HCINT_ACK;
|
||||
}else {
|
||||
xfer->err_count = 0;
|
||||
}
|
||||
} else if (hcint & HCINT_CHANNEL_HALTED) {
|
||||
if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) {
|
||||
|
||||
// Transfer is complete (success, stalled, failed) or channel is disabled
|
||||
if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) {
|
||||
uint8_t pipe_id = pipe_find_opened_by_channel(channel);
|
||||
TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, );
|
||||
hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
|
||||
const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir);
|
||||
} else {
|
||||
// Re-initialize Channel (Do ping protocol for HS)
|
||||
}
|
||||
} else if (hcint & HCINT_ACK) {
|
||||
// ACK received, reset error count
|
||||
xfer->err_count = 0;
|
||||
channel->hcintmsk &= ~HCINT_ACK;
|
||||
}
|
||||
|
||||
pipe->pending_data = false;
|
||||
dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel
|
||||
// const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR |
|
||||
// HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR);
|
||||
// if (xact_err) {
|
||||
// result = XFER_RESULT_FAILED;
|
||||
// }
|
||||
// if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) {
|
||||
// // Channel halted without error, this is a response to channel disable
|
||||
// result = XFER_RESULT_INVALID;
|
||||
// }
|
||||
|
||||
// notify usbh if transfer is complete (skip if channel is disabled)
|
||||
if (result != XFER_RESULT_INVALID) {
|
||||
hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr);
|
||||
|
||||
// Transfer is complete (success, stalled, failed) or channel is disabled
|
||||
if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) {
|
||||
xfer->pending_data = false;
|
||||
dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel
|
||||
|
||||
// notify usbh if transfer is complete (skip if channel is disabled)
|
||||
const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir);
|
||||
if (result != XFER_RESULT_INVALID) {
|
||||
hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -710,36 +767,33 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
|
||||
|
||||
// find OUT channel with pending data
|
||||
bool ff_written = false;
|
||||
//const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2);
|
||||
for (uint8_t ch_id = 0; ch_id < 32; ch_id++) {
|
||||
//const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
|
||||
for (uint8_t ch_id = 0; ch_id < 32 /* 16 */ ; ch_id++) {
|
||||
if (tu_bit_test(dwc2->haintmsk, ch_id)) {
|
||||
dwc2_channel_t* channel = &dwc2->channel[ch_id];
|
||||
const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm;
|
||||
hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
|
||||
if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
|
||||
uint8_t pipe_id = pipe_find_opened_by_channel(channel);
|
||||
if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) {
|
||||
hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id];
|
||||
if (pipe->pending_data) {
|
||||
const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
|
||||
for (uint16_t i = 0; i < remain_packets; i++) {
|
||||
const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size;
|
||||
const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size);
|
||||
if (xfer->pending_data) {
|
||||
const uint16_t remain_packets = channel->hctsiz_bm.packet_count;
|
||||
for (uint16_t i = 0; i < remain_packets; i++) {
|
||||
const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size;
|
||||
const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size);
|
||||
|
||||
// check if there is enough space in FIFO and request queue.
|
||||
// the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue
|
||||
if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) {
|
||||
break;
|
||||
}
|
||||
|
||||
dfifo_write_packet(dwc2, ch_id, pipe->buffer, xact_bytes);
|
||||
pipe->buffer += xact_bytes;
|
||||
|
||||
if (channel->hctsiz_bm.xfer_size == 0) {
|
||||
pipe->pending_data = false; // all data has been written
|
||||
}
|
||||
|
||||
ff_written = true;
|
||||
// check if there is enough space in FIFO and request queue.
|
||||
// the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue
|
||||
if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) {
|
||||
break;
|
||||
}
|
||||
|
||||
dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes);
|
||||
xfer->buffer += xact_bytes;
|
||||
|
||||
if (channel->hctsiz_bm.xfer_size == 0) {
|
||||
xfer->pending_data = false; // all data has been written
|
||||
}
|
||||
|
||||
ff_written = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user