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https://github.com/hathach/tinyusb.git
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Merge branch 'master' into develop
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commit
c3f4c75cfc
@ -148,6 +148,37 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
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ep->MXPLD = bytes_now;
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ep->MXPLD = bytes_now;
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}
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}
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/* called by dcd_init() as well as by the ISR during a USB bus reset */
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static void bus_reset(void)
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{
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USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
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for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
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{
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USBD->EP[ep_index].CFG = 0;
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USBD->EP[ep_index].CFGP = 0;
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}
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/* allocate the default EP0 endpoints */
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USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
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USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
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xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
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USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
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USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
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xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
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/* USB RAM beyond what we've allocated above is available to the user */
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bufseg_addr = PERIPH_EP2_BUF_BASE;
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/* Reset USB device address */
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USBD->FADDR = 0;
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/* reset EP0_IN flag */
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active_ep0_xfer = false;
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}
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/* centralized location for USBD interrupt enable bit mask */
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/* centralized location for USBD interrupt enable bit mask */
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static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
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static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
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@ -167,25 +198,7 @@ void dcd_init(uint8_t rhport)
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usb_detach();
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usb_detach();
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USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
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bus_reset();
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for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
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{
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USBD->EP[ep_index].CFGP &= ~USBD_CFG_STATE_Msk;
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}
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/* allocate the default EP0 endpoints */
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USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
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USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
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xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
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USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
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USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
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xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
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/* USB RAM beyond what we've allocated above is available to the user */
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bufseg_addr = PERIPH_EP2_BUF_BASE;
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usb_attach();
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usb_attach();
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@ -329,15 +342,7 @@ void USBD_IRQHandler(void)
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/* USB bus reset */
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/* USB bus reset */
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USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
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USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
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/* Reset all endpoints to DATA0 */
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bus_reset();
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for(enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
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USBD->EP[ep_index].CFG &= ~USBD_CFG_DSQSYNC_Msk;
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/* Reset USB device address */
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USBD->FADDR = 0;
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/* reset EP0_IN flag */
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active_ep0_xfer = false;
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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}
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}
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@ -1,4 +1,4 @@
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/*
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/*
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* The MIT License (MIT)
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* The MIT License (MIT)
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*
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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@ -313,6 +313,10 @@ void dcd_init(uint8_t rhport)
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// TODO Force fullspeed on non-highspeed port
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// TODO Force fullspeed on non-highspeed port
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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// dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBSTS = dcd_reg->USBSTS;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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@ -419,6 +423,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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// Enable EP Control
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// Enable EP Control
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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@ -441,10 +449,19 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
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dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
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// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
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// address to 32-byte boundaries.
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
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#endif
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//------------- Prepare qtd -------------//
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//------------- Prepare qtd -------------//
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qtd_init(p_qtd, buffer, total_bytes);
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qtd_init(p_qtd, buffer, total_bytes);
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p_qtd->int_on_complete = true;
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p_qtd->int_on_complete = true;
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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// start transfer
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// start transfer
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DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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@ -484,6 +501,11 @@ void dcd_isr(uint8_t rhport)
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}
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}
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}
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}
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// Make sure we read the latest version of _dcd_data.
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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#endif
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// TODO disconnection does not generate interrupt !!!!!!
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// TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INTR_PORT_CHANGE)
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// if (int_status & INTR_PORT_CHANGE)
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// {
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// {
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