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Merge pull request #217 from xobs/valentyusb-eptri

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WIP: Add Valentyusb eptri
This commit is contained in:
hathach 2019-11-18 12:37:34 +07:00 committed by GitHub
commit c2fb813658
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17 changed files with 1920 additions and 4 deletions
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4
.travis.yml
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@ -16,7 +16,11 @@ install:
- gem install ceedling
before_script:
- wget -O /tmp/riscv-toolchain.tgz https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.3.0-1.1/xpack-riscv-none-embed-gcc-8.3.0-1.1-linux-x64.tgz
- tar -xzf /tmp/riscv-toolchain.tgz
- export PATH=$PWD/xPacks/riscv-none-embed-gcc/8.3.0-1.1/bin:$PATH
- arm-none-eabi-gcc --version
- riscv-none-embed-gcc --version
script:
# Build all examples

4
docs/porting.md
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@ -25,8 +25,6 @@ Unless, you've read ahead, this will fail miserably. Now, lets get it to fail le
One of the first things to change is the `-DCFG_TUSB_MCU` cflag in the `board.mk` file. This is used to tell TinyUSB what platform is being built. So, add an entry to `src/tusb_option.h` and update the CFLAG to match.
Also, add an entry for the board in `hw/bsp/board.h`. The CFLAG is auto-added.
Update `board.mk`'s VENDOR and CHIP_FAMILY values when creating the directory for the struct files. Duplicate one of the other sources from `src/portable` into `src/portable/<vendor>/<chip_family>` and delete all of the implementation internals. We'll cover what everything there does later. For now, get it compiling.
## Implementation
@ -104,7 +102,7 @@ Calls to this look like:
dcd_event_setup_received(0, setup, true);
As before with `dcd_event_bus_signal` the first argument is the USB peripheral number and the third is true to signal its being called from an interrup handler. The middle argument is byte array of length 8 with the contents of the SETUP packet. It can be stack allocated because it is copied into the queue.
As before with `dcd_event_bus_signal` the first argument is the USB peripheral number and the third is true to signal its being called from an interrupt handler. The middle argument is byte array of length 8 with the contents of the SETUP packet. It can be stack allocated because it is copied into the queue.
#### Endpoints

6
examples/make.mk
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@ -2,8 +2,12 @@
# Common make definition for all examples
#
# Compiler
# Compiler
ifeq ($(BOARD), fomu)
CROSS_COMPILE = riscv-none-embed-
else
CROSS_COMPILE = arm-none-eabi-
endif
CC = $(CROSS_COMPILE)gcc
CXX = $(CROSS_COMPILE)g++
OBJCOPY = $(CROSS_COMPILE)objcopy

29
hw/bsp/fomu/board.mk Normal file
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@ -0,0 +1,29 @@
CFLAGS += \
-march=rv32i \
-mabi=ilp32 \
-nostdlib \
-DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
MCU_DIR = hw/mcu/fomu
BSP_DIR = hw/bsp/fomu
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/fomu/fomu.ld
# TODO remove later
SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
SRC_C +=
SRC_S += hw/bsp/fomu/crt0-vexriscv.S
INC += \
$(TOP)/$(BSP_DIR)/include
# For TinyUSB port source
VENDOR = valentyusb
CHIP_FAMILY = eptri
# flash using dfu-util
flash: $(BUILD)/$(BOARD)-firmware.dfu
dfu-util -D $^

83
hw/bsp/fomu/crt0-vexriscv.S Normal file
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@ -0,0 +1,83 @@
.global main
.global isr
.section .text.start
.global _start
_start:
j crt_init
.section .text
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _estack - 4
la a0, trap_entry
csrw mtvec, a0
bss_init:
la a0, _sbss
la a1, _ebss + 4
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
j bss_loop
bss_done:
/* Load DATA */
la t0, _etext
la t1, _srelocate
la t2, _erelocate + 4
3:
lw t3, 0(t0)
sw t3, 0(t1)
/* _edata is aligned to 4 bytes. Use word-xfers. */
addi t0, t0, 4
addi t1, t1, 4
bltu t1, t2, 3b
li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
csrw mie,a0
call main
infinite_loop:
j infinite_loop

117
hw/bsp/fomu/fomu.c Normal file
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@ -0,0 +1,117 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include <stdint.h>
#include <stdbool.h>
#include "common/tusb_common.h"
#include "csr.h"
#include "irq.h"
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void hal_dcd_isr(uint8_t rhport);
void fomu_error(uint32_t line)
{
(void)line;
TU_BREAKPOINT();
}
volatile uint32_t system_ticks = 0;
static void timer_init(void)
{
int t;
timer0_en_write(0);
t = CONFIG_CLOCK_FREQUENCY / 1000; // 1000 kHz tick
timer0_reload_write(t);
timer0_load_write(t);
timer0_en_write(1);
timer0_ev_enable_write(1);
timer0_ev_pending_write(1);
irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT));
}
void isr(void)
{
unsigned int irqs;
irqs = irq_pending() & irq_getmask();
#if CFG_TUSB_RHPORT0_MODE == OPT_MODE_DEVICE
if (irqs & (1 << USB_INTERRUPT)) {
hal_dcd_isr(0);
}
#endif
if (irqs & (1 << TIMER0_INTERRUPT)) {
system_ticks++;
timer0_ev_pending_write(1);
}
}
void board_init(void)
{
irq_setmask(0);
irq_setie(1);
timer_init();
return;
}
void board_led_write(bool state)
{
rgb_ctrl_write(0xff);
rgb_raw_write(state);
}
uint32_t board_button_read(void)
{
return 0;
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf;
(void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
int32_t offset = 0;
for (offset = 0; offset < len; offset++)
if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
messible_in_write(((uint8_t *)buf)[offset]);
return len;
}
#if CFG_TUSB_OS == OPT_OS_NONE
uint32_t board_millis(void)
{
return system_ticks;
}
#endif

104
hw/bsp/fomu/fomu.ld Normal file
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@ -0,0 +1,104 @@
OUTPUT_FORMAT("elf32-littleriscv")
ENTRY(_start)
__DYNAMIC = 0;
MEMORY {
csr : ORIGIN = 0x60000000, LENGTH = 0x01000000
vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
ram : ORIGIN = 0x10000000, LENGTH = 0x00020000
rom : ORIGIN = 0x2001a000, LENGTH = 0x00200000 - 0x1a000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_ftext = .;
*(.text.start)
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > rom
. = ALIGN(4);
_etext = .; /* End of text section */
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
end = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

750
hw/bsp/fomu/include/csr.h Normal file
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@ -0,0 +1,750 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49
//--------------------------------------------------------------------------------
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#ifdef CSR_ACCESSORS_DEFINED
extern void csr_writeb(uint8_t value, unsigned long addr);
extern uint8_t csr_readb(unsigned long addr);
extern void csr_writew(uint16_t value, unsigned long addr);
extern uint16_t csr_readw(unsigned long addr);
extern void csr_writel(uint32_t value, unsigned long addr);
extern uint32_t csr_readl(unsigned long addr);
#else /* ! CSR_ACCESSORS_DEFINED */
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
/* ctrl */
#define CSR_CTRL_BASE 0xe0000000L
#define CSR_CTRL_RESET_ADDR 0xe0000000L
#define CSR_CTRL_RESET_SIZE 1
static inline unsigned char ctrl_reset_read(void) {
unsigned char r = csr_readl(0xe0000000L);
return r;
}
static inline void ctrl_reset_write(unsigned char value) {
csr_writel(value, 0xe0000000L);
}
#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L
#define CSR_CTRL_SCRATCH_SIZE 4
static inline unsigned int ctrl_scratch_read(void) {
unsigned int r = csr_readl(0xe0000004L);
r <<= 8;
r |= csr_readl(0xe0000008L);
r <<= 8;
r |= csr_readl(0xe000000cL);
r <<= 8;
r |= csr_readl(0xe0000010L);
return r;
}
static inline void ctrl_scratch_write(unsigned int value) {
csr_writel(value >> 24, 0xe0000004L);
csr_writel(value >> 16, 0xe0000008L);
csr_writel(value >> 8, 0xe000000cL);
csr_writel(value, 0xe0000010L);
}
#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L
#define CSR_CTRL_BUS_ERRORS_SIZE 4
static inline unsigned int ctrl_bus_errors_read(void) {
unsigned int r = csr_readl(0xe0000014L);
r <<= 8;
r |= csr_readl(0xe0000018L);
r <<= 8;
r |= csr_readl(0xe000001cL);
r <<= 8;
r |= csr_readl(0xe0000020L);
return r;
}
/* messible */
#define CSR_MESSIBLE_BASE 0xe0008000L
#define CSR_MESSIBLE_IN_ADDR 0xe0008000L
#define CSR_MESSIBLE_IN_SIZE 1
static inline unsigned char messible_in_read(void) {
unsigned char r = csr_readl(0xe0008000L);
return r;
}
static inline void messible_in_write(unsigned char value) {
csr_writel(value, 0xe0008000L);
}
#define CSR_MESSIBLE_OUT_ADDR 0xe0008004L
#define CSR_MESSIBLE_OUT_SIZE 1
static inline unsigned char messible_out_read(void) {
unsigned char r = csr_readl(0xe0008004L);
return r;
}
#define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L
#define CSR_MESSIBLE_STATUS_SIZE 1
static inline unsigned char messible_status_read(void) {
unsigned char r = csr_readl(0xe0008008L);
return r;
}
#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0
#define CSR_MESSIBLE_STATUS_FULL_SIZE 1
#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1
#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1
/* picorvspi */
#define CSR_PICORVSPI_BASE 0xe0005000L
#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L
#define CSR_PICORVSPI_CFG1_SIZE 1
static inline unsigned char picorvspi_cfg1_read(void) {
unsigned char r = csr_readl(0xe0005000L);
return r;
}
static inline void picorvspi_cfg1_write(unsigned char value) {
csr_writel(value, 0xe0005000L);
}
#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0
#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4
#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4
#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1
#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5
#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1
#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L
#define CSR_PICORVSPI_CFG2_SIZE 1
static inline unsigned char picorvspi_cfg2_read(void) {
unsigned char r = csr_readl(0xe0005004L);
return r;
}
static inline void picorvspi_cfg2_write(unsigned char value) {
csr_writel(value, 0xe0005004L);
}
#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0
#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4
#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L
#define CSR_PICORVSPI_CFG3_SIZE 1
static inline unsigned char picorvspi_cfg3_read(void) {
unsigned char r = csr_readl(0xe0005008L);
return r;
}
static inline void picorvspi_cfg3_write(unsigned char value) {
csr_writel(value, 0xe0005008L);
}
#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0
#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4
#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4
#define CSR_PICORVSPI_CFG3_CRM_SIZE 1
#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5
#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1
#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6
#define CSR_PICORVSPI_CFG3_DDR_SIZE 1
#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL
#define CSR_PICORVSPI_CFG4_SIZE 1
static inline unsigned char picorvspi_cfg4_read(void) {
unsigned char r = csr_readl(0xe000500cL);
return r;
}
static inline void picorvspi_cfg4_write(unsigned char value) {
csr_writel(value, 0xe000500cL);
}
#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7
#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1
#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L
#define CSR_PICORVSPI_STAT1_SIZE 1
static inline unsigned char picorvspi_stat1_read(void) {
unsigned char r = csr_readl(0xe0005010L);
return r;
}
#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0
#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4
#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L
#define CSR_PICORVSPI_STAT2_SIZE 1
static inline unsigned char picorvspi_stat2_read(void) {
unsigned char r = csr_readl(0xe0005014L);
return r;
}
#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L
#define CSR_PICORVSPI_STAT3_SIZE 1
static inline unsigned char picorvspi_stat3_read(void) {
unsigned char r = csr_readl(0xe0005018L);
return r;
}
#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL
#define CSR_PICORVSPI_STAT4_SIZE 1
static inline unsigned char picorvspi_stat4_read(void) {
unsigned char r = csr_readl(0xe000501cL);
return r;
}
/* reboot */
#define CSR_REBOOT_BASE 0xe0006000L
#define CSR_REBOOT_CTRL_ADDR 0xe0006000L
#define CSR_REBOOT_CTRL_SIZE 1
static inline unsigned char reboot_ctrl_read(void) {
unsigned char r = csr_readl(0xe0006000L);
return r;
}
static inline void reboot_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0006000L);
}
#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0
#define CSR_REBOOT_CTRL_IMAGE_SIZE 2
#define CSR_REBOOT_CTRL_KEY_OFFSET 2
#define CSR_REBOOT_CTRL_KEY_SIZE 6
#define CSR_REBOOT_ADDR_ADDR 0xe0006004L
#define CSR_REBOOT_ADDR_SIZE 4
static inline unsigned int reboot_addr_read(void) {
unsigned int r = csr_readl(0xe0006004L);
r <<= 8;
r |= csr_readl(0xe0006008L);
r <<= 8;
r |= csr_readl(0xe000600cL);
r <<= 8;
r |= csr_readl(0xe0006010L);
return r;
}
static inline void reboot_addr_write(unsigned int value) {
csr_writel(value >> 24, 0xe0006004L);
csr_writel(value >> 16, 0xe0006008L);
csr_writel(value >> 8, 0xe000600cL);
csr_writel(value, 0xe0006010L);
}
/* rgb */
#define CSR_RGB_BASE 0xe0006800L
#define CSR_RGB_DAT_ADDR 0xe0006800L
#define CSR_RGB_DAT_SIZE 1
static inline unsigned char rgb_dat_read(void) {
unsigned char r = csr_readl(0xe0006800L);
return r;
}
static inline void rgb_dat_write(unsigned char value) {
csr_writel(value, 0xe0006800L);
}
#define CSR_RGB_ADDR_ADDR 0xe0006804L
#define CSR_RGB_ADDR_SIZE 1
static inline unsigned char rgb_addr_read(void) {
unsigned char r = csr_readl(0xe0006804L);
return r;
}
static inline void rgb_addr_write(unsigned char value) {
csr_writel(value, 0xe0006804L);
}
#define CSR_RGB_CTRL_ADDR 0xe0006808L
#define CSR_RGB_CTRL_SIZE 1
static inline unsigned char rgb_ctrl_read(void) {
unsigned char r = csr_readl(0xe0006808L);
return r;
}
static inline void rgb_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0006808L);
}
#define CSR_RGB_CTRL_EXE_OFFSET 0
#define CSR_RGB_CTRL_EXE_SIZE 1
#define CSR_RGB_CTRL_CURREN_OFFSET 1
#define CSR_RGB_CTRL_CURREN_SIZE 1
#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2
#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1
#define CSR_RGB_CTRL_RRAW_OFFSET 3
#define CSR_RGB_CTRL_RRAW_SIZE 1
#define CSR_RGB_CTRL_GRAW_OFFSET 4
#define CSR_RGB_CTRL_GRAW_SIZE 1
#define CSR_RGB_CTRL_BRAW_OFFSET 5
#define CSR_RGB_CTRL_BRAW_SIZE 1
#define CSR_RGB_RAW_ADDR 0xe000680cL
#define CSR_RGB_RAW_SIZE 1
static inline unsigned char rgb_raw_read(void) {
unsigned char r = csr_readl(0xe000680cL);
return r;
}
static inline void rgb_raw_write(unsigned char value) {
csr_writel(value, 0xe000680cL);
}
#define CSR_RGB_RAW_R_OFFSET 0
#define CSR_RGB_RAW_R_SIZE 1
#define CSR_RGB_RAW_G_OFFSET 1
#define CSR_RGB_RAW_G_SIZE 1
#define CSR_RGB_RAW_B_OFFSET 2
#define CSR_RGB_RAW_B_SIZE 1
/* timer0 */
#define CSR_TIMER0_BASE 0xe0002800L
#define CSR_TIMER0_LOAD_ADDR 0xe0002800L
#define CSR_TIMER0_LOAD_SIZE 4
static inline unsigned int timer0_load_read(void) {
unsigned int r = csr_readl(0xe0002800L);
r <<= 8;
r |= csr_readl(0xe0002804L);
r <<= 8;
r |= csr_readl(0xe0002808L);
r <<= 8;
r |= csr_readl(0xe000280cL);
return r;
}
static inline void timer0_load_write(unsigned int value) {
csr_writel(value >> 24, 0xe0002800L);
csr_writel(value >> 16, 0xe0002804L);
csr_writel(value >> 8, 0xe0002808L);
csr_writel(value, 0xe000280cL);
}
#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L
#define CSR_TIMER0_RELOAD_SIZE 4
static inline unsigned int timer0_reload_read(void) {
unsigned int r = csr_readl(0xe0002810L);
r <<= 8;
r |= csr_readl(0xe0002814L);
r <<= 8;
r |= csr_readl(0xe0002818L);
r <<= 8;
r |= csr_readl(0xe000281cL);
return r;
}
static inline void timer0_reload_write(unsigned int value) {
csr_writel(value >> 24, 0xe0002810L);
csr_writel(value >> 16, 0xe0002814L);
csr_writel(value >> 8, 0xe0002818L);
csr_writel(value, 0xe000281cL);
}
#define CSR_TIMER0_EN_ADDR 0xe0002820L
#define CSR_TIMER0_EN_SIZE 1
static inline unsigned char timer0_en_read(void) {
unsigned char r = csr_readl(0xe0002820L);
return r;
}
static inline void timer0_en_write(unsigned char value) {
csr_writel(value, 0xe0002820L);
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline unsigned char timer0_update_value_read(void) {
unsigned char r = csr_readl(0xe0002824L);
return r;
}
static inline void timer0_update_value_write(unsigned char value) {
csr_writel(value, 0xe0002824L);
}
#define CSR_TIMER0_VALUE_ADDR 0xe0002828L
#define CSR_TIMER0_VALUE_SIZE 4
static inline unsigned int timer0_value_read(void) {
unsigned int r = csr_readl(0xe0002828L);
r <<= 8;
r |= csr_readl(0xe000282cL);
r <<= 8;
r |= csr_readl(0xe0002830L);
r <<= 8;
r |= csr_readl(0xe0002834L);
return r;
}
#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline unsigned char timer0_ev_status_read(void) {
unsigned char r = csr_readl(0xe0002838L);
return r;
}
static inline void timer0_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0002838L);
}
#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline unsigned char timer0_ev_pending_read(void) {
unsigned char r = csr_readl(0xe000283cL);
return r;
}
static inline void timer0_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe000283cL);
}
#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline unsigned char timer0_ev_enable_read(void) {
unsigned char r = csr_readl(0xe0002840L);
return r;
}
static inline void timer0_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe0002840L);
}
/* touch */
#define CSR_TOUCH_BASE 0xe0005800L
#define CSR_TOUCH_O_ADDR 0xe0005800L
#define CSR_TOUCH_O_SIZE 1
static inline unsigned char touch_o_read(void) {
unsigned char r = csr_readl(0xe0005800L);
return r;
}
static inline void touch_o_write(unsigned char value) {
csr_writel(value, 0xe0005800L);
}
#define CSR_TOUCH_O_O_OFFSET 0
#define CSR_TOUCH_O_O_SIZE 4
#define CSR_TOUCH_OE_ADDR 0xe0005804L
#define CSR_TOUCH_OE_SIZE 1
static inline unsigned char touch_oe_read(void) {
unsigned char r = csr_readl(0xe0005804L);
return r;
}
static inline void touch_oe_write(unsigned char value) {
csr_writel(value, 0xe0005804L);
}
#define CSR_TOUCH_OE_OE_OFFSET 0
#define CSR_TOUCH_OE_OE_SIZE 4
#define CSR_TOUCH_I_ADDR 0xe0005808L
#define CSR_TOUCH_I_SIZE 1
static inline unsigned char touch_i_read(void) {
unsigned char r = csr_readl(0xe0005808L);
return r;
}
#define CSR_TOUCH_I_I_OFFSET 0
#define CSR_TOUCH_I_I_SIZE 4
/* usb */
#define CSR_USB_BASE 0xe0004800L
#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L
#define CSR_USB_PULLUP_OUT_SIZE 1
static inline unsigned char usb_pullup_out_read(void) {
unsigned char r = csr_readl(0xe0004800L);
return r;
}
static inline void usb_pullup_out_write(unsigned char value) {
csr_writel(value, 0xe0004800L);
}
#define CSR_USB_ADDRESS_ADDR 0xe0004804L
#define CSR_USB_ADDRESS_SIZE 1
static inline unsigned char usb_address_read(void) {
unsigned char r = csr_readl(0xe0004804L);
return r;
}
static inline void usb_address_write(unsigned char value) {
csr_writel(value, 0xe0004804L);
}
#define CSR_USB_ADDRESS_ADDR_OFFSET 0
#define CSR_USB_ADDRESS_ADDR_SIZE 7
#define CSR_USB_NEXT_EV_ADDR 0xe0004808L
#define CSR_USB_NEXT_EV_SIZE 1
static inline unsigned char usb_next_ev_read(void) {
unsigned char r = csr_readl(0xe0004808L);
return r;
}
#define CSR_USB_NEXT_EV_IN_OFFSET 0
#define CSR_USB_NEXT_EV_IN_SIZE 1
#define CSR_USB_NEXT_EV_OUT_OFFSET 1
#define CSR_USB_NEXT_EV_OUT_SIZE 1
#define CSR_USB_NEXT_EV_SETUP_OFFSET 2
#define CSR_USB_NEXT_EV_SETUP_SIZE 1
#define CSR_USB_NEXT_EV_RESET_OFFSET 3
#define CSR_USB_NEXT_EV_RESET_SIZE 1
#define CSR_USB_SETUP_DATA_ADDR 0xe000480cL
#define CSR_USB_SETUP_DATA_SIZE 1
static inline unsigned char usb_setup_data_read(void) {
unsigned char r = csr_readl(0xe000480cL);
return r;
}
#define CSR_USB_SETUP_DATA_DATA_OFFSET 0
#define CSR_USB_SETUP_DATA_DATA_SIZE 8
#define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L
#define CSR_USB_SETUP_CTRL_SIZE 1
static inline unsigned char usb_setup_ctrl_read(void) {
unsigned char r = csr_readl(0xe0004810L);
return r;
}
static inline void usb_setup_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0004810L);
}
#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5
#define CSR_USB_SETUP_CTRL_RESET_SIZE 1
#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L
#define CSR_USB_SETUP_STATUS_SIZE 1
static inline unsigned char usb_setup_status_read(void) {
unsigned char r = csr_readl(0xe0004814L);
return r;
}
#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0
#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4
#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4
#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1
#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5
#define CSR_USB_SETUP_STATUS_PEND_SIZE 1
#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6
#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1
#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7
#define CSR_USB_SETUP_STATUS_DATA_SIZE 1
#define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L
#define CSR_USB_SETUP_EV_STATUS_SIZE 1
static inline unsigned char usb_setup_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004818L);
return r;
}
static inline void usb_setup_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004818L);
}
#define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL
#define CSR_USB_SETUP_EV_PENDING_SIZE 1
static inline unsigned char usb_setup_ev_pending_read(void) {
unsigned char r = csr_readl(0xe000481cL);
return r;
}
static inline void usb_setup_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe000481cL);
}
#define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L
#define CSR_USB_SETUP_EV_ENABLE_SIZE 1
static inline unsigned char usb_setup_ev_enable_read(void) {
unsigned char r = csr_readl(0xe0004820L);
return r;
}
static inline void usb_setup_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe0004820L);
}
#define CSR_USB_IN_DATA_ADDR 0xe0004824L
#define CSR_USB_IN_DATA_SIZE 1
static inline unsigned char usb_in_data_read(void) {
unsigned char r = csr_readl(0xe0004824L);
return r;
}
static inline void usb_in_data_write(unsigned char value) {
csr_writel(value, 0xe0004824L);
}
#define CSR_USB_IN_DATA_DATA_OFFSET 0
#define CSR_USB_IN_DATA_DATA_SIZE 8
#define CSR_USB_IN_CTRL_ADDR 0xe0004828L
#define CSR_USB_IN_CTRL_SIZE 1
static inline unsigned char usb_in_ctrl_read(void) {
unsigned char r = csr_readl(0xe0004828L);
return r;
}
static inline void usb_in_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0004828L);
}
#define CSR_USB_IN_CTRL_EPNO_OFFSET 0
#define CSR_USB_IN_CTRL_EPNO_SIZE 4
#define CSR_USB_IN_CTRL_RESET_OFFSET 5
#define CSR_USB_IN_CTRL_RESET_SIZE 1
#define CSR_USB_IN_CTRL_STALL_OFFSET 6
#define CSR_USB_IN_CTRL_STALL_SIZE 1
#define CSR_USB_IN_STATUS_ADDR 0xe000482cL
#define CSR_USB_IN_STATUS_SIZE 1
static inline unsigned char usb_in_status_read(void) {
unsigned char r = csr_readl(0xe000482cL);
return r;
}
#define CSR_USB_IN_STATUS_IDLE_OFFSET 0
#define CSR_USB_IN_STATUS_IDLE_SIZE 1
#define CSR_USB_IN_STATUS_HAVE_OFFSET 4
#define CSR_USB_IN_STATUS_HAVE_SIZE 1
#define CSR_USB_IN_STATUS_PEND_OFFSET 5
#define CSR_USB_IN_STATUS_PEND_SIZE 1
#define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L
#define CSR_USB_IN_EV_STATUS_SIZE 1
static inline unsigned char usb_in_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004830L);
return r;
}
static inline void usb_in_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004830L);
}
#define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L
#define CSR_USB_IN_EV_PENDING_SIZE 1
static inline unsigned char usb_in_ev_pending_read(void) {
unsigned char r = csr_readl(0xe0004834L);
return r;
}
static inline void usb_in_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe0004834L);
}
#define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L
#define CSR_USB_IN_EV_ENABLE_SIZE 1
static inline unsigned char usb_in_ev_enable_read(void) {
unsigned char r = csr_readl(0xe0004838L);
return r;
}
static inline void usb_in_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe0004838L);
}
#define CSR_USB_OUT_DATA_ADDR 0xe000483cL
#define CSR_USB_OUT_DATA_SIZE 1
static inline unsigned char usb_out_data_read(void) {
unsigned char r = csr_readl(0xe000483cL);
return r;
}
#define CSR_USB_OUT_DATA_DATA_OFFSET 0
#define CSR_USB_OUT_DATA_DATA_SIZE 8
#define CSR_USB_OUT_CTRL_ADDR 0xe0004840L
#define CSR_USB_OUT_CTRL_SIZE 1
static inline unsigned char usb_out_ctrl_read(void) {
unsigned char r = csr_readl(0xe0004840L);
return r;
}
static inline void usb_out_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0004840L);
}
#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0
#define CSR_USB_OUT_CTRL_EPNO_SIZE 4
#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4
#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1
#define CSR_USB_OUT_CTRL_RESET_OFFSET 5
#define CSR_USB_OUT_CTRL_RESET_SIZE 1
#define CSR_USB_OUT_CTRL_STALL_OFFSET 6
#define CSR_USB_OUT_CTRL_STALL_SIZE 1
#define CSR_USB_OUT_STATUS_ADDR 0xe0004844L
#define CSR_USB_OUT_STATUS_SIZE 1
static inline unsigned char usb_out_status_read(void) {
unsigned char r = csr_readl(0xe0004844L);
return r;
}
#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0
#define CSR_USB_OUT_STATUS_EPNO_SIZE 4
#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4
#define CSR_USB_OUT_STATUS_HAVE_SIZE 1
#define CSR_USB_OUT_STATUS_PEND_OFFSET 5
#define CSR_USB_OUT_STATUS_PEND_SIZE 1
#define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L
#define CSR_USB_OUT_EV_STATUS_SIZE 1
static inline unsigned char usb_out_ev_status_read(void) {
unsigned char r = csr_readl(0xe0004848L);
return r;
}
static inline void usb_out_ev_status_write(unsigned char value) {
csr_writel(value, 0xe0004848L);
}
#define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL
#define CSR_USB_OUT_EV_PENDING_SIZE 1
static inline unsigned char usb_out_ev_pending_read(void) {
unsigned char r = csr_readl(0xe000484cL);
return r;
}
static inline void usb_out_ev_pending_write(unsigned char value) {
csr_writel(value, 0xe000484cL);
}
#define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L
#define CSR_USB_OUT_EV_ENABLE_SIZE 1
static inline unsigned char usb_out_ev_enable_read(void) {
unsigned char r = csr_readl(0xe0004850L);
return r;
}
static inline void usb_out_ev_enable_write(unsigned char value) {
csr_writel(value, 0xe0004850L);
}
#define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L
#define CSR_USB_OUT_ENABLE_STATUS_SIZE 1
static inline unsigned char usb_out_enable_status_read(void) {
unsigned char r = csr_readl(0xe0004854L);
return r;
}
#define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L
#define CSR_USB_OUT_STALL_STATUS_SIZE 1
static inline unsigned char usb_out_stall_status_read(void) {
unsigned char r = csr_readl(0xe0004858L);
return r;
}
/* version */
#define CSR_VERSION_BASE 0xe0007000L
#define CSR_VERSION_MAJOR_ADDR 0xe0007000L
#define CSR_VERSION_MAJOR_SIZE 1
static inline unsigned char version_major_read(void) {
unsigned char r = csr_readl(0xe0007000L);
return r;
}
#define CSR_VERSION_MINOR_ADDR 0xe0007004L
#define CSR_VERSION_MINOR_SIZE 1
static inline unsigned char version_minor_read(void) {
unsigned char r = csr_readl(0xe0007004L);
return r;
}
#define CSR_VERSION_REVISION_ADDR 0xe0007008L
#define CSR_VERSION_REVISION_SIZE 1
static inline unsigned char version_revision_read(void) {
unsigned char r = csr_readl(0xe0007008L);
return r;
}
#define CSR_VERSION_GITREV_ADDR 0xe000700cL
#define CSR_VERSION_GITREV_SIZE 4
static inline unsigned int version_gitrev_read(void) {
unsigned int r = csr_readl(0xe000700cL);
r <<= 8;
r |= csr_readl(0xe0007010L);
r <<= 8;
r |= csr_readl(0xe0007014L);
r <<= 8;
r |= csr_readl(0xe0007018L);
return r;
}
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL
#define CSR_VERSION_GITEXTRA_SIZE 2
static inline unsigned short int version_gitextra_read(void) {
unsigned short int r = csr_readl(0xe000701cL);
r <<= 8;
r |= csr_readl(0xe0007020L);
return r;
}
#define CSR_VERSION_DIRTY_ADDR 0xe0007024L
#define CSR_VERSION_DIRTY_SIZE 1
static inline unsigned char version_dirty_read(void) {
unsigned char r = csr_readl(0xe0007024L);
return r;
}
#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0
#define CSR_VERSION_DIRTY_DIRTY_SIZE 1
#define CSR_VERSION_MODEL_ADDR 0xe0007028L
#define CSR_VERSION_MODEL_SIZE 1
static inline unsigned char version_model_read(void) {
unsigned char r = csr_readl(0xe0007028L);
return r;
}
#define CSR_VERSION_MODEL_MODEL_OFFSET 0
#define CSR_VERSION_MODEL_MODEL_SIZE 8
#define CSR_VERSION_SEED_ADDR 0xe000702cL
#define CSR_VERSION_SEED_SIZE 4
static inline unsigned int version_seed_read(void) {
unsigned int r = csr_readl(0xe000702cL);
r <<= 8;
r |= csr_readl(0xe0007030L);
r <<= 8;
r |= csr_readl(0xe0007034L);
r <<= 8;
r |= csr_readl(0xe0007038L);
return r;
}
/* constants */
#define TIMER0_INTERRUPT 2
static inline int timer0_interrupt_read(void) {
return 2;
}
#define USB_INTERRUPT 3
static inline int usb_interrupt_read(void) {
return 3;
}
#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870
static inline int config_bitstream_sync_header1_read(void) {
return 2123999870;
}
#define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630
static inline int config_bitstream_sync_header2_read(void) {
return 2125109630;
}
#define CONFIG_CLOCK_FREQUENCY 12000000
static inline int config_clock_frequency_read(void) {
return 12000000;
}
#define CONFIG_CPU_RESET_ADDR 0
static inline int config_cpu_reset_addr_read(void) {
return 0;
}
#define CONFIG_CPU_TYPE "VEXRISCV"
static inline const char * config_cpu_type_read(void) {
return "VEXRISCV";
}
#define CONFIG_CPU_TYPE_VEXRISCV 1
static inline int config_cpu_type_vexriscv_read(void) {
return 1;
}
#define CONFIG_CPU_VARIANT "MIN"
static inline const char * config_cpu_variant_read(void) {
return "MIN";
}
#define CONFIG_CPU_VARIANT_MIN 1
static inline int config_cpu_variant_min_read(void) {
return 1;
}
#define CONFIG_CSR_ALIGNMENT 32
static inline int config_csr_alignment_read(void) {
return 32;
}
#define CONFIG_CSR_DATA_WIDTH 8
static inline int config_csr_data_width_read(void) {
return 8;
}
#endif

33
hw/bsp/fomu/include/hw/common.h Normal file
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@ -0,0 +1,33 @@
#ifndef _HW_COMMON_H_
#define _HW_COMMON_H_
#include <stdint.h>
static inline void csr_writeb(uint8_t value, uint32_t addr)
{
*((volatile uint8_t *)addr) = value;
}
static inline uint8_t csr_readb(uint32_t addr)
{
return *(volatile uint8_t *)addr;
}
static inline void csr_writew(uint16_t value, uint32_t addr)
{
*((volatile uint16_t *)addr) = value;
}
static inline uint16_t csr_readw(uint32_t addr)
{
return *(volatile uint16_t *)addr;
}
static inline void csr_writel(uint32_t value, uint32_t addr)
{
*((volatile uint32_t *)addr) = value;
}
static inline uint32_t csr_readl(uint32_t addr)
{
return *(volatile uint32_t *)addr;
}
#endif /* _HW_COMMON_H_ */

71
hw/bsp/fomu/include/irq.h Normal file
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#ifndef __IRQ_H
#define __IRQ_H
#ifdef __cplusplus
extern "C" {
#endif
#define CSR_MSTATUS_MIE 0x8
#define CSR_IRQ_MASK 0xBC0
#define CSR_IRQ_PENDING 0xFC0
#define CSR_DCACHE_INFO 0xCC0
#define csrr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define csrw(reg, val) ({ \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
else \
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
#define csrs(reg, bit) ({ \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
else \
asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
#define csrc(reg, bit) ({ \
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
else \
asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
static inline unsigned int irq_getie(void)
{
return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
}
static inline void irq_setie(unsigned int ie)
{
if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
}
static inline unsigned int irq_getmask(void)
{
unsigned int mask;
asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
return mask;
}
static inline void irq_setmask(unsigned int mask)
{
asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
}
static inline unsigned int irq_pending(void)
{
unsigned int pending;
asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
return pending;
}
#ifdef __cplusplus
}
#endif
#endif /* __IRQ_H */

1
hw/bsp/fomu/output_format.ld Normal file
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OUTPUT_FORMAT("elf32-littleriscv")

6
hw/bsp/fomu/regions.ld Normal file
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@ -0,0 +1,6 @@
MEMORY {
csr : ORIGIN = 0x60000000, LENGTH = 0x01000000
vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
sram : ORIGIN = 0x10000000, LENGTH = 0x00020000
rom : ORIGIN = 0x00000000, LENGTH = 0x00002000
}

4
src/common/tusb_verify.h
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@ -90,9 +90,13 @@
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
} while(0)
#else
#if defined(__riscv)
#define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
#else
#define TU_BREAKPOINT()
#endif
#endif
/*------------------------------------------------------------------*/
/* Macro Generator

638
src/portable/valentyusb/eptri/dcd_eptri.c Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef DEBUG
#define DEBUG 0
#endif
#ifndef LOG_USB
#define LOG_USB 0
#endif
#include "tusb_option.h"
#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
#include "device/dcd.h"
#include "dcd_eptri.h"
#include "csr.h"
#include "irq.h"
void fomu_error(uint32_t line);
#if LOG_USB
struct usb_log {
uint8_t ep_num;
uint8_t size;
uint8_t data[66];
};
__attribute__((used))
struct usb_log usb_log[128];
__attribute__((used))
uint8_t usb_log_offset;
struct xfer_log {
uint8_t ep_num;
uint16_t size;
};
__attribute__((used))
struct xfer_log xfer_log[64];
__attribute__((used))
uint8_t xfer_log_offset;
__attribute__((used))
struct xfer_log queue_log[64];
__attribute__((used))
uint8_t queue_log_offset;
#endif
//--------------------------------------------------------------------+
// SIE Command
//--------------------------------------------------------------------+
#define EP_SIZE 64
uint16_t volatile rx_buffer_offset[16];
uint8_t volatile * rx_buffer[16];
uint16_t volatile rx_buffer_max[16];
volatile uint8_t tx_ep;
volatile bool tx_active;
volatile uint16_t tx_buffer_offset[16];
uint8_t volatile * tx_buffer[16];
volatile uint16_t tx_buffer_max[16];
volatile uint8_t reset_count;
#if DEBUG
__attribute__((used)) uint8_t volatile * last_tx_buffer;
__attribute__((used)) volatile uint8_t last_tx_ep;
uint8_t setup_packet_bfr[10];
#endif
//--------------------------------------------------------------------+
// PIPE HELPER
//--------------------------------------------------------------------+
static bool advance_tx_ep(void) {
// Move on to the next transmit buffer in a round-robin manner
uint8_t prev_tx_ep = tx_ep;
for (tx_ep = (tx_ep + 1) & 0xf; tx_ep != prev_tx_ep; tx_ep = ((tx_ep + 1) & 0xf)) {
if (tx_buffer[tx_ep])
return true;
}
if (!tx_buffer[tx_ep])
return false;
return true;
}
#if LOG_USB
void xfer_log_append(uint8_t ep_num, uint16_t sz) {
xfer_log[xfer_log_offset].ep_num = ep_num;
xfer_log[xfer_log_offset].size = sz;
xfer_log_offset++;
if (xfer_log_offset >= sizeof(xfer_log)/sizeof(*xfer_log))
xfer_log_offset = 0;
}
void queue_log_append(uint8_t ep_num, uint16_t sz) {
queue_log[queue_log_offset].ep_num = ep_num;
queue_log[queue_log_offset].size = sz;
queue_log_offset++;
if (queue_log_offset >= sizeof(queue_log)/sizeof(*queue_log))
queue_log_offset = 0;
}
#endif
static void tx_more_data(void) {
// Send more data
uint8_t added_bytes;
for (added_bytes = 0; (added_bytes < EP_SIZE) && (tx_buffer_offset[tx_ep] < tx_buffer_max[tx_ep]); added_bytes++) {
#if LOG_USB
usb_log[usb_log_offset].data[added_bytes] = tx_buffer[tx_ep][tx_buffer_offset[tx_ep]];
#endif
usb_in_data_write(tx_buffer[tx_ep][tx_buffer_offset[tx_ep]++]);
}
#if LOG_USB
usb_log[usb_log_offset].ep_num = tu_edpt_addr(tx_ep, TUSB_DIR_IN);
usb_log[usb_log_offset].size = added_bytes;
usb_log_offset++;
if (usb_log_offset >= sizeof(usb_log)/sizeof(*usb_log))
usb_log_offset = 0;
#endif
// Updating the epno queues the data
usb_in_ctrl_write(tx_ep & 0xf);
}
static void process_tx(void) {
#if DEBUG
// If the system isn't idle, then something is very wrong.
uint8_t in_status = usb_in_status_read();
if (!(in_status & (1 << CSR_USB_IN_STATUS_IDLE_OFFSET)))
fomu_error(__LINE__);
#endif
// If the buffer is now empty, search for the next buffer to fill.
if (!tx_buffer[tx_ep]) {
if (advance_tx_ep())
tx_more_data();
else
tx_active = false;
return;
}
if (tx_buffer_offset[tx_ep] >= tx_buffer_max[tx_ep]) {
#if DEBUG
last_tx_buffer = tx_buffer[tx_ep];
last_tx_ep = tx_ep;
#endif
tx_buffer[tx_ep] = NULL;
uint16_t xferred_bytes = tx_buffer_max[tx_ep];
uint8_t xferred_ep = tx_ep;
if (!advance_tx_ep())
tx_active = false;
#if LOG_USB
xfer_log_append(tu_edpt_addr(xferred_ep, TUSB_DIR_IN), xferred_bytes);
#endif
dcd_event_xfer_complete(0, tu_edpt_addr(xferred_ep, TUSB_DIR_IN), xferred_bytes, XFER_RESULT_SUCCESS, true);
if (!tx_active)
return;
}
tx_more_data();
return;
}
static void process_rx(void) {
uint8_t out_status = usb_out_status_read();
#if DEBUG
// If the OUT handler is still waiting to send, don't do anything.
if (!(out_status & (1 << CSR_USB_OUT_STATUS_HAVE_OFFSET)))
fomu_error(__LINE__);
// return;
#endif
uint8_t rx_ep = (out_status >> CSR_USB_OUT_STATUS_EPNO_OFFSET) & 0xf;
// If the destination buffer doesn't exist, don't drain the hardware
// fifo. Note that this can cause deadlocks if the host is waiting
// on some other endpoint's data!
#if DEBUG
if (rx_buffer[rx_ep] == NULL) {
fomu_error(__LINE__);
return;
}
#endif
// Drain the FIFO into the destination buffer
uint32_t total_read = 0;
uint32_t current_offset = rx_buffer_offset[rx_ep];
#if DEBUG
uint8_t test_buffer[256];
memset(test_buffer, 0, sizeof(test_buffer));
if (current_offset > rx_buffer_max[rx_ep])
fomu_error(__LINE__);
#endif
#if LOG_USB
usb_log[usb_log_offset].ep_num = tu_edpt_addr(rx_ep, TUSB_DIR_OUT);
usb_log[usb_log_offset].size = 0;
#endif
while (usb_out_status_read() & (1 << CSR_USB_OUT_STATUS_HAVE_OFFSET)) {
uint8_t c = usb_out_data_read();
#if DEBUG
test_buffer[total_read] = c;
#endif
total_read++;
if ((rx_buffer_offset[rx_ep] + current_offset) < rx_buffer_max[rx_ep]) {
#if LOG_USB
usb_log[usb_log_offset].data[usb_log[usb_log_offset].size++] = c;
#endif
if (rx_buffer[rx_ep] != (volatile uint8_t *)0xffffffff)
rx_buffer[rx_ep][current_offset++] = c;
}
}
#if LOG_USB
usb_log_offset++;
if (usb_log_offset >= sizeof(usb_log)/sizeof(*usb_log))
usb_log_offset = 0;
#endif
#if DEBUG
if (total_read > 66)
fomu_error(__LINE__);
if (total_read < 2)
total_read = 2;
// fomu_error(__LINE__);
#endif
// Strip off the CRC16
rx_buffer_offset[rx_ep] += (total_read - 2);
if (rx_buffer_offset[rx_ep] > rx_buffer_max[rx_ep])
rx_buffer_offset[rx_ep] = rx_buffer_max[rx_ep];
// If there's no more data, complete the transfer to tinyusb
if ((rx_buffer_max[rx_ep] == rx_buffer_offset[rx_ep])
// ZLP with less than the total amount of data
|| ((total_read == 2) && ((rx_buffer_offset[rx_ep] & 63) == 0))
// Short read, but not a full packet
|| (((rx_buffer_offset[rx_ep] & 63) != 0) && (total_read < 66))) {
#if DEBUG
if (rx_buffer[rx_ep] == NULL)
fomu_error(__LINE__);
#endif
// Free up this buffer.
rx_buffer[rx_ep] = NULL;
uint16_t len = rx_buffer_offset[rx_ep];
#if DEBUG
// Validate that all enabled endpoints have buffers,
// and no disabled endpoints have buffers.
uint16_t ep_en_mask = usb_out_enable_status_read();
int i;
for (i = 0; i < 16; i++) {
if ((!!(ep_en_mask & (1 << i))) ^ (!!(rx_buffer[i]))) {
uint8_t new_status = usb_out_status_read();
// Another IRQ came in while we were processing, so ignore this endpoint.
if ((new_status & 0x20) && ((new_status & 0xf) == i))
continue;
fomu_error(__LINE__);
}
}
#endif
#if LOG_USB
xfer_log_append(tu_edpt_addr(rx_ep, TUSB_DIR_OUT), len);
#endif
dcd_event_xfer_complete(0, tu_edpt_addr(rx_ep, TUSB_DIR_OUT), len, XFER_RESULT_SUCCESS, true);
}
else {
// If there's more data, re-enable data reception on this endpoint
usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | rx_ep);
}
// Now that the buffer is drained, clear the pending IRQ.
usb_out_ev_pending_write(usb_out_ev_pending_read());
}
//--------------------------------------------------------------------+
// CONTROLLER API
//--------------------------------------------------------------------+
static void dcd_reset(void)
{
reset_count++;
usb_setup_ev_enable_write(0);
usb_in_ev_enable_write(0);
usb_out_ev_enable_write(0);
usb_address_write(0);
// Reset all three FIFO handlers
usb_setup_ctrl_write(1 << CSR_USB_SETUP_CTRL_RESET_OFFSET);
usb_in_ctrl_write(1 << CSR_USB_IN_CTRL_RESET_OFFSET);
usb_out_ctrl_write(1 << CSR_USB_OUT_CTRL_RESET_OFFSET);
memset((void *)rx_buffer, 0, sizeof(rx_buffer));
memset((void *)rx_buffer_max, 0, sizeof(rx_buffer_max));
memset((void *)rx_buffer_offset, 0, sizeof(rx_buffer_offset));
memset((void *)tx_buffer, 0, sizeof(tx_buffer));
memset((void *)tx_buffer_max, 0, sizeof(tx_buffer_max));
memset((void *)tx_buffer_offset, 0, sizeof(tx_buffer_offset));
tx_ep = 0;
tx_active = false;
// Enable all event handlers and clear their contents
usb_setup_ev_pending_write(0xff);
usb_in_ev_pending_write(0xff);
usb_out_ev_pending_write(0xff);
usb_in_ev_enable_write(1);
usb_out_ev_enable_write(1);
usb_setup_ev_enable_write(3);
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
// Initializes the USB peripheral for device mode and enables it.
void dcd_init(uint8_t rhport)
{
(void) rhport;
usb_pullup_out_write(0);
// Enable all event handlers and clear their contents
usb_setup_ev_pending_write(usb_setup_ev_pending_read());
usb_in_ev_pending_write(usb_in_ev_pending_read());
usb_out_ev_pending_write(usb_out_ev_pending_read());
usb_in_ev_enable_write(1);
usb_out_ev_enable_write(1);
usb_setup_ev_enable_write(3);
// Turn on the external pullup
usb_pullup_out_write(1);
}
// Enables or disables the USB device interrupt(s). May be used to
// prevent concurrency issues when mutating data structures shared
// between main code and the interrupt handler.
void dcd_int_enable(uint8_t rhport)
{
(void) rhport;
irq_setmask(irq_getmask() | (1 << USB_INTERRUPT));
}
void dcd_int_disable(uint8_t rhport)
{
(void) rhport;
irq_setmask(irq_getmask() & ~(1 << USB_INTERRUPT));
}
// Called when the device is given a new bus address.
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
// Respond with ACK status first before changing device address
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
// Wait for the response packet to get sent
while (tx_active)
;
// Activate the new address
usb_address_write(dev_addr);
}
// Called when the device received SET_CONFIG request, you can leave this
// empty if your peripheral does not require any specific action.
void dcd_set_config(uint8_t rhport, uint8_t config_num)
{
(void) rhport;
(void) config_num;
}
// Called to remote wake up host when suspended (e.g hid keyboard)
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
}
//--------------------------------------------------------------------+
// DCD Endpoint Port
//--------------------------------------------------------------------+
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
(void) rhport;
uint8_t ep_num = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
uint8_t ep_dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
return false; // Not supported
if (ep_dir == TUSB_DIR_OUT) {
rx_buffer_offset[ep_num] = 0;
rx_buffer_max[ep_num] = 0;
rx_buffer[ep_num] = NULL;
}
else if (ep_dir == TUSB_DIR_OUT) {
tx_buffer_offset[ep_num] = 0;
tx_buffer_max[ep_num] = 0;
tx_buffer[ep_num] = NULL;
}
return true;
}
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT) {
uint8_t enable = 0;
if (rx_buffer[ep_addr])
enable = 1;
usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
}
else
usb_in_ctrl_write((1 << CSR_USB_IN_CTRL_STALL_OFFSET) | tu_edpt_number(ep_addr));
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT) {
uint8_t enable = 0;
if (rx_buffer[ep_addr])
enable = 1;
usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
}
// IN endpoints will get unstalled when more data is written.
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
{
(void)rhport;
uint8_t ep_num = tu_edpt_number(ep_addr);
uint8_t ep_dir = tu_edpt_dir(ep_addr);
TU_ASSERT(ep_num < 16);
// Give a nonzero buffer when we transmit 0 bytes, so that the
// system doesn't think the endpoint is idle.
if ((buffer == NULL) && (total_bytes == 0)) {
buffer = (uint8_t *)0xffffffff;
}
TU_ASSERT(buffer != NULL);
if (ep_dir == TUSB_DIR_IN) {
// Wait for the tx pipe to free up
uint8_t previous_reset_count = reset_count;
// Continue until the buffer is empty, the system is idle, and the fifo is empty.
while (tx_buffer[ep_num] != NULL)
;
dcd_int_disable(0);
#if LOG_USB
queue_log_append(ep_addr, total_bytes);
#endif
// If a reset happens while we're waiting, abort the transfer
if (previous_reset_count != reset_count)
return true;
TU_ASSERT(tx_buffer[ep_num] == NULL);
tx_buffer_offset[ep_num] = 0;
tx_buffer_max[ep_num] = total_bytes;
tx_buffer[ep_num] = buffer;
// If the current buffer is NULL, then that means the tx logic is idle.
// Update the tx_ep to point to our endpoint number and queue the data.
// Otherwise, let it be and it'll get picked up after the next transfer
// finishes.
if (!tx_active) {
tx_ep = ep_num;
tx_active = true;
tx_more_data();
}
dcd_int_enable(0);
}
else if (ep_dir == TUSB_DIR_OUT) {
while (rx_buffer[ep_num] != NULL)
;
TU_ASSERT(rx_buffer[ep_num] == NULL);
dcd_int_disable(0);
#if LOG_USB
queue_log_append(ep_addr, total_bytes);
#endif
rx_buffer[ep_num] = buffer;
rx_buffer_offset[ep_num] = 0;
rx_buffer_max[ep_num] = total_bytes;
// Enable receiving on this particular endpoint
usb_out_ctrl_write((1 << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | ep_num);
#if DEBUG
uint16_t ep_en_mask = usb_out_enable_status_read();
int i;
for (i = 0; i < 16; i++) {
if ((!!(ep_en_mask & (1 << i))) ^ (!!(rx_buffer[i]))) {
if (rx_buffer[i] && usb_out_ev_pending_read() && (usb_out_status_read() & 0xf) == i)
continue;
fomu_error(__LINE__);
}
}
#endif
dcd_int_enable(0);
}
return true;
}
//--------------------------------------------------------------------+
// ISR
//--------------------------------------------------------------------+
static void handle_out(void)
{
// An "OUT" transaction just completed so we have new data.
// (But only if we can accept the data)
#if DEBUG
if (!usb_out_ev_pending_read())
fomu_error(__LINE__);
if (!usb_out_ev_enable_read())
fomu_error(__LINE__);
#endif
process_rx();
}
static void handle_in(void)
{
#if DEBUG
if (!usb_in_ev_pending_read())
fomu_error(__LINE__);
if (!usb_in_ev_enable_read())
fomu_error(__LINE__);
#endif
usb_in_ev_pending_write(usb_in_ev_pending_read());
process_tx();
}
static void handle_reset(void)
{
#if DEBUG
uint8_t setup_pending = usb_setup_ev_pending_read() & usb_setup_ev_enable_read();
if (!(setup_pending & 2))
fomu_error(__LINE__);
#endif
usb_setup_ev_pending_write(2);
// This event means a bus reset occurred. Reset everything, and
// abandon any further processing.
dcd_reset();
}
static void handle_setup(void)
{
#if !DEBUG
uint8_t setup_packet_bfr[10];
#endif
#if DEBUG
uint8_t setup_pending = usb_setup_ev_pending_read() & usb_setup_ev_enable_read();
if (!(setup_pending & 1))
fomu_error(__LINE__);
#endif
// We got a SETUP packet. Copy it to the setup buffer and clear
// the "pending" bit.
// Setup packets are always 8 bytes, plus two bytes of crc16.
uint32_t setup_length = 0;
#if DEBUG
if (!(usb_setup_status_read() & (1 << CSR_USB_SETUP_STATUS_HAVE_OFFSET)))
fomu_error(__LINE__);
#endif
while (usb_setup_status_read() & (1 << CSR_USB_SETUP_STATUS_HAVE_OFFSET)) {
uint8_t c = usb_setup_data_read();
if (setup_length < sizeof(setup_packet_bfr))
setup_packet_bfr[setup_length] = c;
setup_length++;
}
// If we have 10 bytes, that's a full SETUP packet plus CRC16.
// Otherwise, it was an RX error.
if (setup_length == 10) {
dcd_event_setup_received(0, setup_packet_bfr, true);
}
#if DEBUG
else {
fomu_error(__LINE__);
}
#endif
usb_setup_ev_pending_write(1);
}
void hal_dcd_isr(uint8_t rhport)
{
(void)rhport;
uint8_t next_ev;
while ((next_ev = usb_next_ev_read())) {
switch (next_ev) {
case 1 << CSR_USB_NEXT_EV_IN_OFFSET:
handle_in();
break;
case 1 << CSR_USB_NEXT_EV_OUT_OFFSET:
handle_out();
break;
case 1 << CSR_USB_NEXT_EV_SETUP_OFFSET:
handle_setup();
break;
case 1 << CSR_USB_NEXT_EV_RESET_OFFSET:
handle_reset();
break;
}
}
}
#endif

39
src/portable/valentyusb/eptri/dcd_eptri.h Normal file
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@ -0,0 +1,39 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef _TUSB_DCD_VALENTYUSB_EPTRI_H_
#define _TUSB_DCD_VALENTYUSB_EPTRI_H_
#include "common/tusb_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _TUSB_DCD_VALENTYUSB_EPTRI_H_ */

33
src/portable/valentyusb/eptri/hal_eptri.c Normal file
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@ -0,0 +1,33 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "common/tusb_common.h"
#if (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
// No HAL-specific stuff here!
#endif

2
src/tusb_option.h
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@ -70,6 +70,8 @@
#define OPT_MCU_CXD56 400 ///< SONY CXD56
#define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config
/** @} */
/** \defgroup group_supported_os Supported RTOS