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enable full 224KB flash for ch32v203 with flash enhanced read mode in SystemInit (better with startup).

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add flash with wlink-rs
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hathach 2024-07-10 22:48:06 +07:00
parent 8d5dbb9577
commit c1175b7013
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GPG Key ID: 26FAB84F615C3C52
13 changed files with 75 additions and 93 deletions
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60
.gitignore vendored
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@ -31,62 +31,4 @@ cov-int
__pycache__
cmake-build-*
sdkconfig
# submodules
hw/mcu/allwinner
hw/mcu/bridgetek/ft9xx/ft90x-sdk
hw/mcu/broadcom
hw/mcu/gd/nuclei-sdk
hw/mcu/infineon/mtb-xmclib-cat3
hw/mcu/microchip
hw/mcu/mindmotion/mm32sdk
hw/mcu/nordic/nrfx
hw/mcu/nuvoton
hw/mcu/nxp/lpcopen
hw/mcu/nxp/mcux-sdk
hw/mcu/nxp/nxp_sdk
hw/mcu/raspberry_pi/Pico-PIO-USB
hw/mcu/renesas/rx
hw/mcu/silabs/cmsis-dfp-efm32gg12b
hw/mcu/sony/cxd56/spresense-exported-sdk
hw/mcu/st/cmsis_device_f0
hw/mcu/st/cmsis_device_f1
hw/mcu/st/cmsis_device_f2
hw/mcu/st/cmsis_device_f3
hw/mcu/st/cmsis_device_f4
hw/mcu/st/cmsis_device_f7
hw/mcu/st/cmsis_device_g0
hw/mcu/st/cmsis_device_g4
hw/mcu/st/cmsis_device_h5
hw/mcu/st/cmsis_device_h7
hw/mcu/st/cmsis_device_l0
hw/mcu/st/cmsis_device_l1
hw/mcu/st/cmsis_device_l4
hw/mcu/st/cmsis_device_l5
hw/mcu/st/cmsis_device_u5
hw/mcu/st/cmsis_device_wb
hw/mcu/st/stm32f0xx_hal_driver
hw/mcu/st/stm32f1xx_hal_driver
hw/mcu/st/stm32f2xx_hal_driver
hw/mcu/st/stm32f3xx_hal_driver
hw/mcu/st/stm32f4xx_hal_driver
hw/mcu/st/stm32f7xx_hal_driver
hw/mcu/st/stm32g0xx_hal_driver
hw/mcu/st/stm32g4xx_hal_driver
hw/mcu/st/stm32h5xx_hal_driver
hw/mcu/st/stm32h7xx_hal_driver
hw/mcu/st/stm32l0xx_hal_driver
hw/mcu/st/stm32l1xx_hal_driver
hw/mcu/st/stm32l4xx_hal_driver
hw/mcu/st/stm32l5xx_hal_driver
hw/mcu/st/stm32u5xx_hal_driver
hw/mcu/st/stm32wbxx_hal_driver
hw/mcu/ti
hw/mcu/wch/ch32v20x
hw/mcu/wch/ch32v307
hw/mcu/wch/ch32f20x
lib/CMSIS_5
lib/FreeRTOS-Kernel
lib/lwip
lib/sct_neopixel
tools/uf2
.PVS-Studio

6
examples/build_system/make/rules.mk
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@ -145,6 +145,12 @@ OPENOCD_WCH_OPTION ?=
flash-openocd-wch: $(BUILD)/$(PROJECT).elf
$(OPENOCD_WCH) $(OPENOCD_WCH_OPTION) -c init -c halt -c "flash write_image $<" -c reset -c exit
# --------------- wlink-rs -----------------
# flash with https://github.com/ch32-rs/wlink
WLINK_RS ?= wlink
flash-wlink-rs: $(BUILD)/$(PROJECT).elf
$(WLINK_RS) flash $<
# --------------- dfu-util -----------------
DFU_UTIL_OPTION ?= -a 0
flash-dfu-util: $(BUILD)/$(PROJECT).bin

5
hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
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@ -1,6 +1,8 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 64K)
# 64KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 64K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 20K)
# set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${CH32_FAMILY}_tinyuf2.ld)
@ -8,6 +10,7 @@ set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

4
hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
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@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 64KB zero-wait, 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=20K \

5
hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
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@ -1,11 +1,14 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 32K)
# 32KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 32K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 10K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSI=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

4
hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
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@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSI=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 32KB zero-wait, 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=32K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=10K \

5
hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
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@ -1,11 +1,14 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 64K)
# 64KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 64K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

4
hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
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@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 64KB zero-wait , 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=20K \

48
hw/bsp/ch32v20x/family.c
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@ -62,7 +62,6 @@ void USBWakeUp_IRQHandler(void) {
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
__attribute__((interrupt))
@ -84,7 +83,6 @@ uint32_t SysTick_Config(uint32_t ticks) {
uint32_t board_millis(void) {
return system_ticks;
}
#endif
void board_init(void) {
@ -140,29 +138,29 @@ void board_init(void) {
}
void board_reset_to_bootloader(void) {
board_led_write(true);
__disable_irq();
#if CFG_TUD_ENABLED
tud_deinit(0);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
#endif
SysTick->CTLR = 0;
for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
NVIC_DisableIRQ(i);
}
__enable_irq();
// define function pointer to BOOT ROM address
void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
bootloader_entry();
board_led_write(false);
// board_led_write(true);
//
// __disable_irq();
//
// #if CFG_TUD_ENABLED
// tud_deinit(0);
// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
// #endif
//
// SysTick->CTLR = 0;
// for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
// NVIC_DisableIRQ(i);
// }
//
// __enable_irq();
//
// // define function pointer to BOOT ROM address
// void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
//
// bootloader_entry();
//
// board_led_write(false);
// while(1) { }
}

1
hw/bsp/ch32v20x/family.cmake
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@ -131,6 +131,7 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_openocd_wch(${TARGET})
family_flash_wlink_rs(${TARGET})
#family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
#family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})

3
hw/bsp/ch32v20x/family.mk
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@ -60,4 +60,5 @@ INC += \
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
flash: flash-openocd-wch
flash: flash-wlink-rs
#flash: flash-openocd-wch

11
hw/bsp/ch32v20x/system_ch32v20x.c
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@ -19,9 +19,9 @@
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_HSE HSE_VALUE
//#define SYSCLK_FREQ_48MHz_HSE 48000000
// #define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
// #define SYSCLK_FREQ_72MHz_HSE 72000000
// #define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
@ -109,6 +109,13 @@ static void SetSysClockTo144_HSI( void );
*/
void SystemInit (void)
{
// Enable Flash enhance read mode for full 224KB
#if defined(CH32_FLASH_ENHANCE_READ_MODE) && CH32_FLASH_ENHANCE_READ_MODE == 1
FLASH_Unlock_Fast();
FLASH->CTLR |= (1 << 24);
FLASH_Lock_Fast();
#endif
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;

12
hw/bsp/family_support.cmake
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@ -455,6 +455,18 @@ function(family_flash_openocd_wch TARGET)
family_flash_openocd(${TARGET})
endfunction()
# Add flash with https://github.com/ch32-rs/wlink
function(family_flash_wlink_rs TARGET)
if (NOT DEFINED WLINK_RS)
set(WLINK_RS wlink)
endif ()
add_custom_target(${TARGET}-wlink-rs
DEPENDS ${TARGET}
COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}>
)
endfunction()
# Add flash pycod target
function(family_flash_pyocd TARGET)
if (NOT DEFINED PYOC)