mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
hcd dwc2 add dcache support, usbh correctly use cache line size with TUH_EPBUF_DEF
This commit is contained in:
parent
62f0e87bf1
commit
be25aa31f6
@ -18,7 +18,8 @@ list(APPEND compile_definitions
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if (target STREQUAL esp32p4)
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# P4 change alignment to 64 (DCache line size) for possible DMA configuration
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list(APPEND compile_definitions
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CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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)
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endif ()
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@ -103,15 +103,15 @@ typedef struct {
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// clean/flush data cache: write cache -> memory.
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// Required before an DMA TX transfer to make sure data is in memory
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bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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bool hcd_dcache_clean(void const* addr, uint32_t data_size);
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// invalidate data cache: mark cache as invalid, next read will read from memory
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// Required BOTH before and after an DMA RX transfer
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bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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bool hcd_dcache_invalidate(void const* addr, uint32_t data_size);
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// clean and invalidate data cache
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// Required before an DMA transfer where memory is both read/write by DMA
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bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size);
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//--------------------------------------------------------------------+
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// Controller API
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@ -65,6 +65,21 @@ TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_is
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(void) in_isr;
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}
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TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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return false;
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}
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TU_ATTR_WEAK bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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return false;
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}
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TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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return false;
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}
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//--------------------------------------------------------------------+
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// USBH-HCD common data structure
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//--------------------------------------------------------------------+
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@ -249,14 +264,10 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
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OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
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static osal_queue_t _usbh_q;
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CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
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static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
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// Control transfers: since most controllers do not support multiple control transfers
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// on multiple devices concurrently and control transfers are not used much except for
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// enumeration, we will only execute control transfers one at a time.
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CFG_TUH_MEM_SECTION struct {
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CFG_TUH_MEM_ALIGN tusb_control_request_t request;
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static struct {
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uint8_t* buffer;
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tuh_xfer_cb_t complete_cb;
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uintptr_t user_data;
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@ -264,7 +275,14 @@ CFG_TUH_MEM_SECTION struct {
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uint8_t daddr;
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volatile uint8_t stage;
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volatile uint16_t actual_len;
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}_ctrl_xfer;
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} _ctrl_xfer;
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typedef struct {
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TUH_EPBUF_TYPE_DEF(request, tusb_control_request_t);
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TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE);
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} usbh_epbuf_t;
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CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf;
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//------------- Helper Function -------------//
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@ -475,7 +493,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
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switch (event.event_id) {
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case HCD_EVENT_DEVICE_ATTACH:
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// due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one.
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// due to the shared control buffer, we must complete enumerating one device before enumerating another one.
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// TODO better to have an separated queue for newly attached devices
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if (_dev0.enumerating) {
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// Some device can cause multiple duplicated attach events
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@ -622,10 +640,10 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
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_ctrl_xfer.daddr = daddr;
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_ctrl_xfer.actual_len = 0;
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_ctrl_xfer.request = (*xfer->setup);
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_ctrl_xfer.buffer = xfer->buffer;
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_ctrl_xfer.complete_cb = xfer->complete_cb;
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_ctrl_xfer.user_data = xfer->user_data;
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_usbh_epbuf.request = (*xfer->setup);
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}
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(void) osal_mutex_unlock(_usbh_mutex);
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@ -639,7 +657,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
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TU_LOG_BUF_USBH(xfer->setup, 8);
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if (xfer->complete_cb) {
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TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
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TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_usbh_epbuf.request) );
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}else {
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// blocking if complete callback is not provided
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// change callback to internal blocking, and result as user argument
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@ -649,7 +667,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
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_ctrl_xfer.user_data = (uintptr_t) &result;
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_ctrl_xfer.complete_cb = _control_blocking_complete_cb;
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TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
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TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_usbh_epbuf.request) );
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while (result == XFER_RESULT_INVALID) {
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// Note: this can be called within an callback ie. part of tuh_task()
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@ -681,7 +699,7 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) {
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TU_LOG_USBH("\r\n");
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// duplicate xfer since user can execute control transfer within callback
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tusb_control_request_t const request = _ctrl_xfer.request;
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tusb_control_request_t const request = _usbh_epbuf.request;
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tuh_xfer_t xfer_temp = {
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.daddr = daddr,
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.ep_addr = 0,
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@ -704,7 +722,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
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(void) ep_addr;
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const uint8_t rhport = usbh_get_rhport(daddr);
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tusb_control_request_t const * request = &_ctrl_xfer.request;
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tusb_control_request_t const * request = &_usbh_epbuf.request;
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if (XFER_RESULT_SUCCESS != result) {
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TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
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@ -817,7 +835,7 @@ uint8_t usbh_get_rhport(uint8_t dev_addr) {
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}
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uint8_t *usbh_get_enum_buf(void) {
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return _usbh_ctrl_buf;
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return _usbh_epbuf.ctrl;
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}
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void usbh_int_set(bool enabled) {
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@ -1279,7 +1297,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
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// Enumeration Process
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// is a lengthy process with a series of control transfer to configure
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// newly attached device.
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// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating
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// NOTE: due to the shared control buffer, we must complete enumerating
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// one device before enumerating another one.
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//--------------------------------------------------------------------+
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@ -1347,7 +1365,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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case ENUM_HUB_CLEAR_RESET_1: {
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hub_port_status_response_t port_status;
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memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
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memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
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if (!port_status.status.connection) {
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// device unplugged while delaying, nothing else to do
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@ -1368,13 +1386,13 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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case ENUM_HUB_GET_STATUS_2:
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tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS);
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TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
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TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
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process_enumeration, ENUM_HUB_CLEAR_RESET_2),);
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break;
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case ENUM_HUB_CLEAR_RESET_2: {
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hub_port_status_response_t port_status;
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memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
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memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
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// Acknowledge Port Reset Change if Reset Successful
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if (port_status.change.reset) {
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@ -1392,7 +1410,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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// Get first 8 bytes of device descriptor for Control Endpoint size
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TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
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TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8,
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TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8,
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process_enumeration, ENUM_SET_ADDR),);
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break;
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}
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@ -1443,13 +1461,13 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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// Get full device descriptor
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TU_LOG_USBH("Get Device Descriptor\r\n");
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TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t),
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TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t),
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process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),);
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break;
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}
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case ENUM_GET_9BYTE_CONFIG_DESC: {
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tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
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tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
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usbh_device_t* dev = get_device(daddr);
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TU_ASSERT(dev,);
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@ -1459,18 +1477,18 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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dev->i_product = desc_device->iProduct;
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dev->i_serial = desc_device->iSerialNumber;
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// if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
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// if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_epbuf.ctrl);
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// Get 9-byte for total length
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uint8_t const config_idx = CONFIG_NUM - 1;
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TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
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TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9,
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TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
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process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
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break;
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}
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case ENUM_GET_FULL_CONFIG_DESC: {
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uint8_t const* desc_config = _usbh_ctrl_buf;
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uint8_t const* desc_config = _usbh_epbuf.ctrl;
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// Use offsetof to avoid pointer to the odd/misaligned address
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uint16_t const total_len = tu_le16toh(
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@ -1482,7 +1500,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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// Get full configuration descriptor
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uint8_t const config_idx = CONFIG_NUM - 1;
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TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
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TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len,
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TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len,
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process_enumeration, ENUM_SET_CONFIG),);
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break;
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}
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@ -1500,7 +1518,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
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// Parse configuration & set up drivers
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// driver_open() must not make any usb transfer
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TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),);
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TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
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// Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
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// Since driver can perform control transfer within its set_config, this is done asynchronously.
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@ -1561,7 +1579,7 @@ static bool enum_new_device(hcd_event_t* event) {
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tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS);
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// ENUM_HUB_GET_STATUS
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TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
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TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
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process_enumeration, ENUM_HUB_CLEAR_RESET_1));
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}
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#endif // hub
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@ -1589,7 +1607,7 @@ static uint8_t get_new_address(bool is_hub) {
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}
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static bool enum_request_set_addr(void) {
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tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
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tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
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// Get new address
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uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
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@ -31,7 +31,7 @@
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#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
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#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
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#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE)
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#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
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#endif
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@ -28,6 +28,10 @@
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#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2)
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#if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE)
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#error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
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#endif
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// Debug level for DWC2
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#define DWC2_DEBUG 2
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@ -132,6 +136,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
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return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
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}
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#if CFG_TUH_MEM_DCACHE_ENABLE
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bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
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TU_VERIFY(addr && data_size);
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return dwc2_dcache_clean(addr, data_size);
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}
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bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
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TU_VERIFY(addr && data_size);
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return dwc2_dcache_invalidate(addr, data_size);
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}
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bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
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TU_VERIFY(addr && data_size);
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return dwc2_dcache_clean_invalidate(addr, data_size);
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}
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#endif
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// Allocate a channel for new transfer
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TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) {
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const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
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@ -555,6 +576,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) {
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if (hcchar_bm->ep_dir == TUSB_DIR_IN) {
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channel_send_in_token(dwc2, channel);
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} else {
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hcd_dcache_clean(edpt->buffer, edpt->buflen);
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channel->hcchar |= HCCHAR_CHENA;
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}
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} else {
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@ -1119,13 +1141,17 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) {
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const uint32_t hcint = channel->hcint;
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channel->hcint = hcint; // clear interrupt
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bool is_done;
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bool is_done = false;
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if (is_dma) {
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#if CFG_TUH_DWC2_DMA_ENABLE
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if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
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is_done = handle_channel_out_dma(dwc2, ch_id, hcint);
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} else {
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is_done = handle_channel_in_dma(dwc2, ch_id, hcint);
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if (is_done && (channel->hcdma > xfer->xferred_bytes)) {
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// hcdma is increased by word --> need to align4
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hcd_dcache_invalidate((void*) tu_align4(channel->hcdma - xfer->xferred_bytes), xfer->xferred_bytes);
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}
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}
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#endif
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} else {
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