mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-19 15:40:41 +00:00
clean up IAR ending warning
This commit is contained in:
hathach
parent
0f0d9d127b
commit
bb8602ce41
@ -1,74 +1,74 @@
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||||
/**************************************************************************/
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/*!
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@file board_ea4357.h
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@author hathach (tinyusb.org)
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@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
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||||
*/
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/**************************************************************************/
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/** \ingroup TBD
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* \defgroup TBD
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* \brief TBD
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*
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* @{
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*/
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#ifndef _TUSB_BOARD_EA4357_H_
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#define _TUSB_BOARD_EA4357_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "LPC43xx.h"
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#include "lpc43xx_scu.h"
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#include "lpc43xx_cgu.h"
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#include "lpc43xx_gpio.h"
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#include "lpc43xx_uart.h"
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#include "lpc43xx_i2c.h"
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#include "../oem_base_board/pca9532.h" // LEDs
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//#include "../oem_board/nand.h"a
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//#define CFG_PRINTF_TARGET PRINTF_TARGET_SWO
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#define CFG_PRINTF_TARGET PRINTF_TARGET_UART // FIXME keil's cmsis rtx does not work with UART (work with SWO)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_BOARD_EA4357_H_ */
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/** @} */
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/**************************************************************************/
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/*!
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@file board_ea4357.h
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@author hathach (tinyusb.org)
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@section LICENSE
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|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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/** \ingroup TBD
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* \defgroup TBD
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* \brief TBD
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*
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* @{
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*/
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#ifndef _TUSB_BOARD_EA4357_H_
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#define _TUSB_BOARD_EA4357_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "LPC43xx.h"
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#include "lpc43xx_scu.h"
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#include "lpc43xx_cgu.h"
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#include "lpc43xx_gpio.h"
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#include "lpc43xx_uart.h"
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#include "lpc43xx_i2c.h"
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#include "../oem_base_board/pca9532.h" // LEDs
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//#include "../oem_board/nand.h"a
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//#define CFG_PRINTF_TARGET PRINTF_TARGET_SWO
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#define CFG_PRINTF_TARGET PRINTF_TARGET_UART // FIXME keil's cmsis rtx does not work with UART (work with SWO)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_BOARD_EA4357_H_ */
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/** @} */
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@ -1,65 +1,65 @@
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/**************************************************************************/
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/*!
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@file board_lpcxpresso1347.h
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
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||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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/** \ingroup TBD
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* \defgroup TBD
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* \brief TBD
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*
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* @{
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*/
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#ifndef _TUSB_BOARD_LPCXPRESSO1347_H_
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#define _TUSB_BOARD_LPCXPRESSO1347_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "LPC13Uxx.h"
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#include "lpc13uxx/LPC13Uxx_DriverLib/inc/gpio.h"
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#include "lpc13uxx/LPC13Uxx_DriverLib/inc/uart.h"
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#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_BOARD_LPCXPRESSO1347_H_ */
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/** @} */
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/**************************************************************************/
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/*!
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@file board_lpcxpresso1347.h
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@author hathach (tinyusb.org)
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@section LICENSE
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|
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Software License Agreement (BSD License)
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||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
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||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
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||||
*/
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/**************************************************************************/
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/** \ingroup TBD
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* \defgroup TBD
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* \brief TBD
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*
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* @{
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*/
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#ifndef _TUSB_BOARD_LPCXPRESSO1347_H_
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#define _TUSB_BOARD_LPCXPRESSO1347_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "LPC13Uxx.h"
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#include "lpc13uxx/LPC13Uxx_DriverLib/inc/gpio.h"
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#include "lpc13uxx/LPC13Uxx_DriverLib/inc/uart.h"
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#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_BOARD_LPCXPRESSO1347_H_ */
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/** @} */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,64 +1,64 @@
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/**************************************************************************//**
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* @file system_LPC13Uxx.h
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
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* for the NXP LPC13Uxx Device Series
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* @version V1.10
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* @date 24. November 2010
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*
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* @note
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __SYSTEM_LPC13Uxx_H
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#define __SYSTEM_LPC13Uxx_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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* Update SystemCoreClock variable
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*
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* @param none
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* @return none
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*
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_LPC13Uxx_H */
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/**************************************************************************//**
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* @file system_LPC13Uxx.h
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
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* for the NXP LPC13Uxx Device Series
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* @version V1.10
|
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* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC13Uxx_H
|
||||
#define __SYSTEM_LPC13Uxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC13Uxx_H */
|
||||
|
||||
@ -1,437 +1,437 @@
|
||||
/******************************************************************************
|
||||
* @file system_LPC13Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
/******************************************************************************
|
||||
* @file system_LPC13Uxx.c
|
||||
* @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC13xx Device Series
|
||||
* @version V1.10
|
||||
* @date 24. November 2010
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC13Uxx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Oscillator Control Register (SYSOSCCTRL)
|
||||
// <o1.0> BYPASS: System Oscillator Bypass Enable
|
||||
// <i> If enabled then PLL input (sys_osc_clk) is fed
|
||||
// <i> directly from XTALIN and XTALOUT pins.
|
||||
// <o1.9> FREQRANGE: System Oscillator Frequency Range
|
||||
// <i> Determines frequency range for Low-power oscillator.
|
||||
// <0=> 1 - 20 MHz
|
||||
// <1=> 15 - 25 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
|
||||
// <o2.0..4> DIVSEL: Select Divider for Fclkana
|
||||
// <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
|
||||
// <0-31>
|
||||
// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
|
||||
// <0=> Undefined
|
||||
// <1=> 0.5 MHz
|
||||
// <2=> 0.8 MHz
|
||||
// <3=> 1.1 MHz
|
||||
// <4=> 1.4 MHz
|
||||
// <5=> 1.6 MHz
|
||||
// <6=> 1.8 MHz
|
||||
// <7=> 2.0 MHz
|
||||
// <8=> 2.2 MHz
|
||||
// <9=> 2.4 MHz
|
||||
// <10=> 2.6 MHz
|
||||
// <11=> 2.7 MHz
|
||||
// <12=> 2.9 MHz
|
||||
// <13=> 3.1 MHz
|
||||
// <14=> 3.2 MHz
|
||||
// <15=> 3.4 MHz
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Control Register (SYSPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o3.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o3.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
|
||||
// <o4.0..1> SEL: System PLL Clock Source
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o5.0..1> SEL: Clock Source for Main Clock
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> Input Clock to System PLL
|
||||
// <2=> WDT Oscillator
|
||||
// <3=> System PLL Clock Out
|
||||
// </h>
|
||||
//
|
||||
// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
|
||||
// <o6.0..7> DIV: System AHB Clock Divider
|
||||
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Control Register (USBPLLCTRL)
|
||||
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
|
||||
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
|
||||
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
|
||||
// <o7.0..4> MSEL: Feedback Divider Selection
|
||||
// <i> M = MSEL + 1
|
||||
// <0-31>
|
||||
// <o7.5..6> PSEL: Post Divider Selection
|
||||
// <0=> P = 1
|
||||
// <1=> P = 2
|
||||
// <2=> P = 4
|
||||
// <3=> P = 8
|
||||
// </h>
|
||||
//
|
||||
// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
|
||||
// <o8.0..1> SEL: USB PLL Clock Source
|
||||
// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
|
||||
// <0=> IRC Oscillator
|
||||
// <1=> System Oscillator
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Source Select Register (USBCLKSEL)
|
||||
// <o9.0..1> SEL: System PLL Clock Source
|
||||
// <0=> USB PLL out
|
||||
// <1=> Main clock
|
||||
// <2=> Reserved
|
||||
// <3=> Reserved
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Divider Register (USBCLKDIV)
|
||||
// <o10.0..7> DIV: USB Clock Divider
|
||||
// <i> Divides USB clock to 48 MHz.
|
||||
// <i> 0 = is disabled
|
||||
// <0-255>
|
||||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
|
||||
#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define USBCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define USBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
|
||||
#error "SYSOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
|
||||
#error "WDTOSCCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
|
||||
#error "SYSPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
|
||||
#error "SYSPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
|
||||
#error "MAINCLKSEL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
|
||||
#error "SYSAHBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
|
||||
#error "USBPLLCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
|
||||
#error "USBPLLCTRL: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
|
||||
#error "USBCLKSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
|
||||
#error "USBCLKDIV: Value out of range!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define __XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
|
||||
#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
|
||||
#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
#if (__FREQSEL == 0)
|
||||
#define __WDT_OSC_CLK ( 0) /* undefined */
|
||||
#elif (__FREQSEL == 1)
|
||||
#define __WDT_OSC_CLK ( 500000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 2)
|
||||
#define __WDT_OSC_CLK ( 800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 3)
|
||||
#define __WDT_OSC_CLK (1100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 4)
|
||||
#define __WDT_OSC_CLK (1400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 5)
|
||||
#define __WDT_OSC_CLK (1600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 6)
|
||||
#define __WDT_OSC_CLK (1800000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 7)
|
||||
#define __WDT_OSC_CLK (2000000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 8)
|
||||
#define __WDT_OSC_CLK (2200000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 9)
|
||||
#define __WDT_OSC_CLK (2400000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 10)
|
||||
#define __WDT_OSC_CLK (2600000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 11)
|
||||
#define __WDT_OSC_CLK (2700000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 12)
|
||||
#define __WDT_OSC_CLK (2900000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 13)
|
||||
#define __WDT_OSC_CLK (3100000 / __DIVSEL)
|
||||
#elif (__FREQSEL == 14)
|
||||
#define __WDT_OSC_CLK (3200000 / __DIVSEL)
|
||||
#else
|
||||
#define __WDT_OSC_CLK (3400000 / __DIVSEL)
|
||||
#endif
|
||||
|
||||
/* sys_pllclkin calculation */
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
|
||||
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
|
||||
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
|
||||
#else
|
||||
#define __SYS_PLLCLKIN (0)
|
||||
#endif
|
||||
|
||||
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
|
||||
|
||||
/* main clock calculation */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 0)
|
||||
#define __MAIN_CLOCK (__IRC_OSC_CLK)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 1)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKIN)
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 2)
|
||||
#if (__FREQSEL == 0)
|
||||
#error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
|
||||
#else
|
||||
#define __MAIN_CLOCK (__WDT_OSC_CLK)
|
||||
#endif
|
||||
#elif ((MAINCLKSEL_Val & 0x03) == 3)
|
||||
#define __MAIN_CLOCK (__SYS_PLLCLKOUT)
|
||||
#else
|
||||
#define __MAIN_CLOCK (0)
|
||||
#endif
|
||||
|
||||
#define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
|
||||
|
||||
#else
|
||||
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
|
||||
#endif // CLOCK_SETUP
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
uint32_t wdt_osc = 0;
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
|
||||
case 0: wdt_osc = 0; break;
|
||||
case 1: wdt_osc = 500000; break;
|
||||
case 2: wdt_osc = 800000; break;
|
||||
case 3: wdt_osc = 1100000; break;
|
||||
case 4: wdt_osc = 1400000; break;
|
||||
case 5: wdt_osc = 1600000; break;
|
||||
case 6: wdt_osc = 1800000; break;
|
||||
case 7: wdt_osc = 2000000; break;
|
||||
case 8: wdt_osc = 2200000; break;
|
||||
case 9: wdt_osc = 2400000; break;
|
||||
case 10: wdt_osc = 2600000; break;
|
||||
case 11: wdt_osc = 2700000; break;
|
||||
case 12: wdt_osc = 2900000; break;
|
||||
case 13: wdt_osc = 3100000; break;
|
||||
case 14: wdt_osc = 3200000; break;
|
||||
case 15: wdt_osc = 3400000; break;
|
||||
}
|
||||
wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
|
||||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
} else {
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
}
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
case 3: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void SystemInit (void) {
|
||||
volatile uint32_t i;
|
||||
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
|
||||
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
|
||||
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
|
||||
#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
|
||||
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
|
||||
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
#endif
|
||||
|
||||
#if (((MAINCLKSEL_Val & 0x03) == 2) )
|
||||
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
|
||||
for (i = 0; i < 200; i++) __NOP();
|
||||
#endif
|
||||
|
||||
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
|
||||
|
||||
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
|
||||
|
||||
#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
|
||||
|
||||
/* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
|
||||
LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
|
||||
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
|
||||
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
|
||||
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
|
||||
|
||||
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
|
||||
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
|
||||
|
||||
#else /* USB clock is not used */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
|
||||
LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* System clock to the IOCON needs to be enabled or
|
||||
most of the I/O related peripherals won't work. */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
|
||||
|
||||
}
|
||||
|
||||
@ -1,64 +1,64 @@
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __GPIO_H
|
||||
#define __GPIO_H
|
||||
|
||||
#define CHANNEL0 0
|
||||
#define CHANNEL1 1
|
||||
#define CHANNEL2 2
|
||||
#define CHANNEL3 3
|
||||
#define CHANNEL4 4
|
||||
#define CHANNEL5 5
|
||||
#define CHANNEL6 6
|
||||
#define CHANNEL7 7
|
||||
|
||||
#define PORT0 0
|
||||
#define PORT1 1
|
||||
|
||||
#define GROUP0 0
|
||||
#define GROUP1 1
|
||||
|
||||
void PIN_INT0_IRQHandler(void);
|
||||
void PIN_INT1_IRQHandler(void);
|
||||
void PIN_INT2_IRQHandler(void);
|
||||
void PIN_INT3_IRQHandler(void);
|
||||
void PIN_INT4_IRQHandler(void);
|
||||
void PIN_INT5_IRQHandler(void);
|
||||
void PIN_INT6_IRQHandler(void);
|
||||
void PIN_INT7_IRQHandler(void);
|
||||
void GINT0_IRQHandler(void);
|
||||
void GINT1_IRQHandler(void);
|
||||
void GPIOInit( void );
|
||||
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event );
|
||||
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
|
||||
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
|
||||
uint32_t GPIOPinIntStatus( uint32_t channelNum );
|
||||
void GPIOPinIntClear( uint32_t channelNum );
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern );
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
|
||||
|
||||
#endif /* end __GPIO_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
/****************************************************************************
|
||||
* $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for GPIO.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __GPIO_H
|
||||
#define __GPIO_H
|
||||
|
||||
#define CHANNEL0 0
|
||||
#define CHANNEL1 1
|
||||
#define CHANNEL2 2
|
||||
#define CHANNEL3 3
|
||||
#define CHANNEL4 4
|
||||
#define CHANNEL5 5
|
||||
#define CHANNEL6 6
|
||||
#define CHANNEL7 7
|
||||
|
||||
#define PORT0 0
|
||||
#define PORT1 1
|
||||
|
||||
#define GROUP0 0
|
||||
#define GROUP1 1
|
||||
|
||||
void PIN_INT0_IRQHandler(void);
|
||||
void PIN_INT1_IRQHandler(void);
|
||||
void PIN_INT2_IRQHandler(void);
|
||||
void PIN_INT3_IRQHandler(void);
|
||||
void PIN_INT4_IRQHandler(void);
|
||||
void PIN_INT5_IRQHandler(void);
|
||||
void PIN_INT6_IRQHandler(void);
|
||||
void PIN_INT7_IRQHandler(void);
|
||||
void GINT0_IRQHandler(void);
|
||||
void GINT1_IRQHandler(void);
|
||||
void GPIOInit( void );
|
||||
void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
|
||||
uint32_t sense, uint32_t event );
|
||||
void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
|
||||
void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
|
||||
uint32_t GPIOPinIntStatus( uint32_t channelNum );
|
||||
void GPIOPinIntClear( uint32_t channelNum );
|
||||
void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
|
||||
uint32_t sense, uint32_t *eventPattern );
|
||||
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
|
||||
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
|
||||
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
|
||||
|
||||
#endif /* end __GPIO_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
||||
@ -1,72 +1,72 @@
|
||||
/****************************************************************************
|
||||
* $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for UART configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define AUTOBAUD_ENABLE 0
|
||||
#define FDR_CALIBRATION 0
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR (0x01<<0)
|
||||
#define IER_THRE (0x01<<1)
|
||||
#define IER_RLS (0x01<<2)
|
||||
#define IER_ABEO (0x01<<8)
|
||||
#define IER_ABTO (0x01<<9)
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
#define IIR_ABEO (0x01<<8)
|
||||
#define IIR_ABTO (0x01<<9)
|
||||
|
||||
#define LSR_RDR (0x01<<0)
|
||||
#define LSR_OE (0x01<<1)
|
||||
#define LSR_PE (0x01<<2)
|
||||
#define LSR_FE (0x01<<3)
|
||||
#define LSR_BI (0x01<<4)
|
||||
#define LSR_THRE (0x01<<5)
|
||||
#define LSR_TEMT (0x01<<6)
|
||||
#define LSR_RXFE (0x01<<7)
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void USART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
void print_string( uint8_t *str_ptr );
|
||||
uint8_t get_key( void );
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
/****************************************************************************
|
||||
* $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423 $
|
||||
* Project: NXP LPC13Uxx software example
|
||||
*
|
||||
* Description:
|
||||
* This file contains definition and prototype for UART configuration.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef __UART_H
|
||||
#define __UART_H
|
||||
|
||||
#define AUTOBAUD_ENABLE 0
|
||||
#define FDR_CALIBRATION 0
|
||||
#define RS485_ENABLED 0
|
||||
#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */
|
||||
#define MODEM_TEST 0
|
||||
|
||||
#define IER_RBR (0x01<<0)
|
||||
#define IER_THRE (0x01<<1)
|
||||
#define IER_RLS (0x01<<2)
|
||||
#define IER_ABEO (0x01<<8)
|
||||
#define IER_ABTO (0x01<<9)
|
||||
|
||||
#define IIR_PEND 0x01
|
||||
#define IIR_RLS 0x03
|
||||
#define IIR_RDA 0x02
|
||||
#define IIR_CTI 0x06
|
||||
#define IIR_THRE 0x01
|
||||
#define IIR_ABEO (0x01<<8)
|
||||
#define IIR_ABTO (0x01<<9)
|
||||
|
||||
#define LSR_RDR (0x01<<0)
|
||||
#define LSR_OE (0x01<<1)
|
||||
#define LSR_PE (0x01<<2)
|
||||
#define LSR_FE (0x01<<3)
|
||||
#define LSR_BI (0x01<<4)
|
||||
#define LSR_THRE (0x01<<5)
|
||||
#define LSR_TEMT (0x01<<6)
|
||||
#define LSR_RXFE (0x01<<7)
|
||||
|
||||
#define BUFSIZE 0x40
|
||||
|
||||
/* RS485 mode definition. */
|
||||
#define RS485_NMMEN (0x1<<0)
|
||||
#define RS485_RXDIS (0x1<<1)
|
||||
#define RS485_AADEN (0x1<<2)
|
||||
#define RS485_SEL (0x1<<3)
|
||||
#define RS485_DCTRL (0x1<<4)
|
||||
#define RS485_OINV (0x1<<5)
|
||||
|
||||
void ModemInit( void );
|
||||
void UARTInit(uint32_t Baudrate);
|
||||
void USART_IRQHandler(void);
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length);
|
||||
void print_string( uint8_t *str_ptr );
|
||||
uint8_t get_key( void );
|
||||
|
||||
#endif /* end __UART_H */
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,437 +1,437 @@
|
||||
/****************************************************************************
|
||||
* $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267 $
|
||||
* Project: NXP LPC13Uxx UART example
|
||||
*
|
||||
* Description:
|
||||
* This file contains UART code example which include UART
|
||||
* initialization, UART interrupt handler, and related APIs for
|
||||
* UART access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "type.h"
|
||||
#include "uart.h"
|
||||
|
||||
volatile uint32_t UARTStatus;
|
||||
volatile uint8_t UARTTxEmpty = 1;
|
||||
volatile uint8_t UARTBuffer[BUFSIZE];
|
||||
volatile uint32_t UARTCount = 0;
|
||||
|
||||
#if AUTOBAUD_ENABLE
|
||||
volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: USART_IRQHandler
|
||||
**
|
||||
** Descriptions: USART interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void USART_IRQHandler(void)
|
||||
{
|
||||
uint8_t IIRValue, LSRValue;
|
||||
uint8_t Dummy = Dummy;
|
||||
|
||||
IIRValue = LPC_USART->IIR;
|
||||
|
||||
IIRValue >>= 1; /* skip pending bit in IIR */
|
||||
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
if (IIRValue == IIR_RLS) /* Receive Line Status */
|
||||
{
|
||||
LSRValue = LPC_USART->LSR;
|
||||
/* Receive Line Status */
|
||||
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
|
||||
{
|
||||
/* There are errors or break interrupt */
|
||||
/* Read LSR will clear the interrupt */
|
||||
UARTStatus = LSRValue;
|
||||
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
|
||||
interrupt, then bail out */
|
||||
return;
|
||||
}
|
||||
if (LSRValue & LSR_RDR) /* Receive Data Ready */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_RDA) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
|
||||
{
|
||||
/* Character Time-out indicator */
|
||||
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
|
||||
}
|
||||
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
|
||||
{
|
||||
/* THRE interrupt */
|
||||
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
|
||||
valid data in U0THR or not */
|
||||
if (LSRValue & LSR_THRE)
|
||||
{
|
||||
UARTTxEmpty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTTxEmpty = 0;
|
||||
}
|
||||
}
|
||||
#if AUTOBAUD_ENABLE
|
||||
if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABEO;
|
||||
/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABEO;
|
||||
UARTAutoBaud = 1;
|
||||
}
|
||||
else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABTO;
|
||||
AutoBaudTimeout = 1;
|
||||
/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABTO;
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#if MODEM_TEST
|
||||
/*****************************************************************************
|
||||
** Function name: ModemInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port as modem, setup pin select.
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void ModemInit( void )
|
||||
{
|
||||
|
||||
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
|
||||
LPC_IOCON->PIO0_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_17 |= 0x01; /* UART RTS */
|
||||
#if 1
|
||||
LPC_IOCON->PIO1_13 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_13 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_15 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_15 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_16 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_16 |= 0x01; /* UART RI */
|
||||
|
||||
#else
|
||||
LPC_IOCON->PIO1_19 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_19 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_20 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_20 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_21 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_21 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_22 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_22 |= 0x01; /* UART RI */
|
||||
#endif
|
||||
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Function: uart_set_divisors
|
||||
*
|
||||
* Purpose: Determines best dividers to get a target clock rate
|
||||
*
|
||||
* Processing:
|
||||
* See function.
|
||||
*
|
||||
* Parameters:
|
||||
* UARTClk : UART clock
|
||||
* baudrate : Desired UART baud rate
|
||||
*
|
||||
* Outputs:
|
||||
* baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
|
||||
*
|
||||
* Returns: Error status.
|
||||
*
|
||||
* Notes: None
|
||||
*
|
||||
**********************************************************************/
|
||||
uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
|
||||
{
|
||||
uint32_t uClk;
|
||||
uint32_t calcBaudrate = 0;
|
||||
uint32_t temp = 0;
|
||||
|
||||
uint32_t mulFracDiv, dividerAddFracDiv;
|
||||
uint32_t diviser = 0 ;
|
||||
uint32_t mulFracDivOptimal = 1;
|
||||
uint32_t dividerAddOptimal = 0;
|
||||
uint32_t diviserOptimal = 0;
|
||||
|
||||
uint32_t relativeError = 0;
|
||||
uint32_t relativeOptimalError = 100000;
|
||||
|
||||
/* get UART block clock */
|
||||
uClk = UARTClk >> 4; /* div by 16 */
|
||||
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
|
||||
* The formula is :
|
||||
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
|
||||
* It involves floating point calculations. That's the reason the formulae are adjusted with
|
||||
* Multiply and divide method.*/
|
||||
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
|
||||
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
|
||||
for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
|
||||
{
|
||||
for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
|
||||
{
|
||||
temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
|
||||
diviser = temp / baudrate;
|
||||
if ((temp % baudrate) > (baudrate / 2))
|
||||
diviser++;
|
||||
|
||||
if (diviser > 2 && diviser < 65536)
|
||||
{
|
||||
calcBaudrate = temp / diviser;
|
||||
|
||||
if (calcBaudrate <= baudrate)
|
||||
relativeError = baudrate - calcBaudrate;
|
||||
else
|
||||
relativeError = calcBaudrate - baudrate;
|
||||
|
||||
if ((relativeError < relativeOptimalError))
|
||||
{
|
||||
mulFracDivOptimal = mulFracDiv ;
|
||||
dividerAddOptimal = dividerAddFracDiv;
|
||||
diviserOptimal = diviser;
|
||||
relativeOptimalError = relativeError;
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
}
|
||||
} /* End of if */
|
||||
} /* end of inner for loop */
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
} /* end of outer for loop */
|
||||
|
||||
if (relativeOptimalError < (baudrate / 30))
|
||||
{
|
||||
/* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
|
||||
/* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
|
||||
LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
|
||||
LPC_USART->DLL = diviserOptimal & 0xFF;
|
||||
|
||||
/* Initialise the Fractional Divider Register */
|
||||
LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
|
||||
return( TRUE );
|
||||
}
|
||||
return ( FALSE );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
#if !AUTOBAUD_ENABLE
|
||||
uint32_t Fdiv;
|
||||
#endif
|
||||
volatile uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(USART_IRQn);
|
||||
/* Select only one location from below. */
|
||||
#if 1
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
|
||||
LPC_IOCON->PIO1_13 &= ~0x07;
|
||||
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_18 &= ~0x07;
|
||||
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_27 &= ~0x07;
|
||||
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
#if !AUTOBAUD_ENABLE
|
||||
#if FDR_CALIBRATION
|
||||
if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
|
||||
{
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
}
|
||||
#else
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
#endif
|
||||
#endif
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(USART_IRQn);
|
||||
|
||||
#if TX_INTERRUPT
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#if AUTOBAUD_ENABLE
|
||||
LPC_USART->IER |= IER_ABEO | IER_ABTO;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if !TX_INTERRUPT
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#else
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: print_string
|
||||
**
|
||||
** Descriptions: print out string on the terminal
|
||||
**
|
||||
** parameters: pointer to the string end with NULL char.
|
||||
** Returned value: none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
void print_string( uint8_t *str_ptr )
|
||||
{
|
||||
while(*str_ptr != 0x00)
|
||||
{
|
||||
while((LPC_USART->LSR & 0x60) != 0x60);
|
||||
LPC_USART->THR = *str_ptr;
|
||||
str_ptr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: get_key
|
||||
**
|
||||
** Descriptions: Get a character from the terminal
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: character, zero is none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint8_t get_key( void )
|
||||
{
|
||||
uint8_t dummy;
|
||||
|
||||
while ( !(LPC_USART->LSR & 0x01) );
|
||||
dummy = LPC_USART->RBR;
|
||||
if ((dummy>=65) && (dummy<=90))
|
||||
{
|
||||
/* convert capital to non-capital character, A2a, B2b, C2c. */
|
||||
dummy +=32;
|
||||
}
|
||||
/* echo */
|
||||
LPC_USART->THR = dummy;
|
||||
return(dummy);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
/****************************************************************************
|
||||
* $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267 $
|
||||
* Project: NXP LPC13Uxx UART example
|
||||
*
|
||||
* Description:
|
||||
* This file contains UART code example which include UART
|
||||
* initialization, UART interrupt handler, and related APIs for
|
||||
* UART access.
|
||||
*
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
****************************************************************************/
|
||||
#include "LPC13Uxx.h"
|
||||
#include "type.h"
|
||||
#include "uart.h"
|
||||
|
||||
volatile uint32_t UARTStatus;
|
||||
volatile uint8_t UARTTxEmpty = 1;
|
||||
volatile uint8_t UARTBuffer[BUFSIZE];
|
||||
volatile uint32_t UARTCount = 0;
|
||||
|
||||
#if AUTOBAUD_ENABLE
|
||||
volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: USART_IRQHandler
|
||||
**
|
||||
** Descriptions: USART interrupt handler
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void USART_IRQHandler(void)
|
||||
{
|
||||
uint8_t IIRValue, LSRValue;
|
||||
uint8_t Dummy = Dummy;
|
||||
|
||||
IIRValue = LPC_USART->IIR;
|
||||
|
||||
IIRValue >>= 1; /* skip pending bit in IIR */
|
||||
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
||||
if (IIRValue == IIR_RLS) /* Receive Line Status */
|
||||
{
|
||||
LSRValue = LPC_USART->LSR;
|
||||
/* Receive Line Status */
|
||||
if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
|
||||
{
|
||||
/* There are errors or break interrupt */
|
||||
/* Read LSR will clear the interrupt */
|
||||
UARTStatus = LSRValue;
|
||||
Dummy = LPC_USART->RBR; /* Dummy read on RX to clear
|
||||
interrupt, then bail out */
|
||||
return;
|
||||
}
|
||||
if (LSRValue & LSR_RDR) /* Receive Data Ready */
|
||||
{
|
||||
/* If no error on RLS, normal ready, save into the data buffer. */
|
||||
/* Note: read RBR will clear the interrupt */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_RDA) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
UARTBuffer[UARTCount++] = LPC_USART->RBR;
|
||||
if (UARTCount == BUFSIZE)
|
||||
{
|
||||
UARTCount = 0; /* buffer overflow */
|
||||
}
|
||||
}
|
||||
else if (IIRValue == IIR_CTI) /* Character timeout indicator */
|
||||
{
|
||||
/* Character Time-out indicator */
|
||||
UARTStatus |= 0x100; /* Bit 9 as the CTI error */
|
||||
}
|
||||
else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */
|
||||
{
|
||||
/* THRE interrupt */
|
||||
LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if
|
||||
valid data in U0THR or not */
|
||||
if (LSRValue & LSR_THRE)
|
||||
{
|
||||
UARTTxEmpty = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UARTTxEmpty = 0;
|
||||
}
|
||||
}
|
||||
#if AUTOBAUD_ENABLE
|
||||
if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABEO;
|
||||
/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABEO;
|
||||
UARTAutoBaud = 1;
|
||||
}
|
||||
else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
|
||||
{
|
||||
LPC_USART->IER &= ~IIR_ABTO;
|
||||
AutoBaudTimeout = 1;
|
||||
/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
|
||||
LPC_USART->ACR |= IIR_ABTO;
|
||||
}
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
#if MODEM_TEST
|
||||
/*****************************************************************************
|
||||
** Function name: ModemInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port as modem, setup pin select.
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void ModemInit( void )
|
||||
{
|
||||
|
||||
LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */
|
||||
LPC_IOCON->PIO0_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_17 |= 0x01; /* UART RTS */
|
||||
#if 1
|
||||
LPC_IOCON->PIO1_13 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_13 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_15 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_15 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_16 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_16 |= 0x01; /* UART RI */
|
||||
|
||||
#else
|
||||
LPC_IOCON->PIO1_19 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_19 |= 0x01; /* UART DTR */
|
||||
LPC_IOCON->PIO1_20 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_20 |= 0x01; /* UART DSR */
|
||||
LPC_IOCON->PIO1_21 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_21 |= 0x01; /* UART DCD */
|
||||
LPC_IOCON->PIO1_22 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_22 |= 0x01; /* UART RI */
|
||||
#endif
|
||||
LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Function: uart_set_divisors
|
||||
*
|
||||
* Purpose: Determines best dividers to get a target clock rate
|
||||
*
|
||||
* Processing:
|
||||
* See function.
|
||||
*
|
||||
* Parameters:
|
||||
* UARTClk : UART clock
|
||||
* baudrate : Desired UART baud rate
|
||||
*
|
||||
* Outputs:
|
||||
* baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
|
||||
*
|
||||
* Returns: Error status.
|
||||
*
|
||||
* Notes: None
|
||||
*
|
||||
**********************************************************************/
|
||||
uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
|
||||
{
|
||||
uint32_t uClk;
|
||||
uint32_t calcBaudrate = 0;
|
||||
uint32_t temp = 0;
|
||||
|
||||
uint32_t mulFracDiv, dividerAddFracDiv;
|
||||
uint32_t diviser = 0 ;
|
||||
uint32_t mulFracDivOptimal = 1;
|
||||
uint32_t dividerAddOptimal = 0;
|
||||
uint32_t diviserOptimal = 0;
|
||||
|
||||
uint32_t relativeError = 0;
|
||||
uint32_t relativeOptimalError = 100000;
|
||||
|
||||
/* get UART block clock */
|
||||
uClk = UARTClk >> 4; /* div by 16 */
|
||||
/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
|
||||
* The formula is :
|
||||
* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
|
||||
* It involves floating point calculations. That's the reason the formulae are adjusted with
|
||||
* Multiply and divide method.*/
|
||||
/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
|
||||
* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
|
||||
for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
|
||||
{
|
||||
for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
|
||||
{
|
||||
temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
|
||||
diviser = temp / baudrate;
|
||||
if ((temp % baudrate) > (baudrate / 2))
|
||||
diviser++;
|
||||
|
||||
if (diviser > 2 && diviser < 65536)
|
||||
{
|
||||
calcBaudrate = temp / diviser;
|
||||
|
||||
if (calcBaudrate <= baudrate)
|
||||
relativeError = baudrate - calcBaudrate;
|
||||
else
|
||||
relativeError = calcBaudrate - baudrate;
|
||||
|
||||
if ((relativeError < relativeOptimalError))
|
||||
{
|
||||
mulFracDivOptimal = mulFracDiv ;
|
||||
dividerAddOptimal = dividerAddFracDiv;
|
||||
diviserOptimal = diviser;
|
||||
relativeOptimalError = relativeError;
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
}
|
||||
} /* End of if */
|
||||
} /* end of inner for loop */
|
||||
if (relativeError == 0)
|
||||
break;
|
||||
} /* end of outer for loop */
|
||||
|
||||
if (relativeOptimalError < (baudrate / 30))
|
||||
{
|
||||
/* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
|
||||
/* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
|
||||
LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
|
||||
LPC_USART->DLL = diviserOptimal & 0xFF;
|
||||
|
||||
/* Initialise the Fractional Divider Register */
|
||||
LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
|
||||
return( TRUE );
|
||||
}
|
||||
return ( FALSE );
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTInit
|
||||
**
|
||||
** Descriptions: Initialize UART0 port, setup pin select,
|
||||
** clock, parity, stop bits, FIFO, etc.
|
||||
**
|
||||
** parameters: UART baudrate
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTInit(uint32_t baudrate)
|
||||
{
|
||||
#if !AUTOBAUD_ENABLE
|
||||
uint32_t Fdiv;
|
||||
#endif
|
||||
volatile uint32_t regVal;
|
||||
|
||||
UARTTxEmpty = 1;
|
||||
UARTCount = 0;
|
||||
|
||||
NVIC_DisableIRQ(USART_IRQn);
|
||||
/* Select only one location from below. */
|
||||
#if 1
|
||||
LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */
|
||||
LPC_IOCON->PIO0_19 &= ~0x07;
|
||||
LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_14 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_14 |= 0x03; /* UART RXD */
|
||||
LPC_IOCON->PIO1_13 &= ~0x07;
|
||||
LPC_IOCON->PIO1_13 |= 0x03; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_17 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_17 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_18 &= ~0x07;
|
||||
LPC_IOCON->PIO1_18 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
#if 0
|
||||
LPC_IOCON->PIO1_26 &= ~0x07; /* UART I/O config */
|
||||
LPC_IOCON->PIO1_26 |= 0x02; /* UART RXD */
|
||||
LPC_IOCON->PIO1_27 &= ~0x07;
|
||||
LPC_IOCON->PIO1_27 |= 0x02; /* UART TXD */
|
||||
#endif
|
||||
|
||||
/* Enable UART clock */
|
||||
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
|
||||
LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */
|
||||
|
||||
LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
||||
#if !AUTOBAUD_ENABLE
|
||||
#if FDR_CALIBRATION
|
||||
if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
|
||||
{
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
}
|
||||
#else
|
||||
Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ; /*baud rate */
|
||||
LPC_USART->DLM = Fdiv / 256;
|
||||
LPC_USART->DLL = Fdiv % 256;
|
||||
LPC_USART->FDR = 0x10; /* Default */
|
||||
#endif
|
||||
#endif
|
||||
LPC_USART->LCR = 0x03; /* DLAB = 0 */
|
||||
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
||||
|
||||
/* Read to clear the line status. */
|
||||
regVal = LPC_USART->LSR;
|
||||
|
||||
/* Ensure a clean start, no data in either TX or RX FIFO. */
|
||||
while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
||||
while ( LPC_USART->LSR & LSR_RDR )
|
||||
{
|
||||
regVal = LPC_USART->RBR; /* Dump data from RX FIFO */
|
||||
}
|
||||
|
||||
/* Enable the UART Interrupt */
|
||||
NVIC_EnableIRQ(USART_IRQn);
|
||||
|
||||
#if TX_INTERRUPT
|
||||
LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
||||
#else
|
||||
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
|
||||
#endif
|
||||
#if AUTOBAUD_ENABLE
|
||||
LPC_USART->IER |= IER_ABEO | IER_ABTO;
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: UARTSend
|
||||
**
|
||||
** Descriptions: Send a block of data to the UART 0 port based
|
||||
** on the data length
|
||||
**
|
||||
** parameters: buffer pointer, and data length
|
||||
** Returned value: None
|
||||
**
|
||||
*****************************************************************************/
|
||||
void UARTSend(uint8_t *BufferPtr, uint32_t Length)
|
||||
{
|
||||
|
||||
while ( Length != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
#if !TX_INTERRUPT
|
||||
while ( !(LPC_USART->LSR & LSR_THRE) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
#else
|
||||
/* Below flag is set inside the interrupt handler when THRE occurs. */
|
||||
while ( !(UARTTxEmpty & 0x01) );
|
||||
LPC_USART->THR = *BufferPtr;
|
||||
UARTTxEmpty = 0; /* not empty in the THR until it shifts out */
|
||||
#endif
|
||||
BufferPtr++;
|
||||
Length--;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: print_string
|
||||
**
|
||||
** Descriptions: print out string on the terminal
|
||||
**
|
||||
** parameters: pointer to the string end with NULL char.
|
||||
** Returned value: none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
void print_string( uint8_t *str_ptr )
|
||||
{
|
||||
while(*str_ptr != 0x00)
|
||||
{
|
||||
while((LPC_USART->LSR & 0x60) != 0x60);
|
||||
LPC_USART->THR = *str_ptr;
|
||||
str_ptr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
** Function name: get_key
|
||||
**
|
||||
** Descriptions: Get a character from the terminal
|
||||
**
|
||||
** parameters: None
|
||||
** Returned value: character, zero is none.
|
||||
**
|
||||
*****************************************************************************/
|
||||
uint8_t get_key( void )
|
||||
{
|
||||
uint8_t dummy;
|
||||
|
||||
while ( !(LPC_USART->LSR & 0x01) );
|
||||
dummy = LPC_USART->RBR;
|
||||
if ((dummy>=65) && (dummy<=90))
|
||||
{
|
||||
/* convert capital to non-capital character, A2a, B2b, C2c. */
|
||||
dummy +=32;
|
||||
}
|
||||
/* echo */
|
||||
LPC_USART->THR = dummy;
|
||||
return(dummy);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,277 +1,277 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_cgu.h 2011-06-02
|
||||
*//**
|
||||
* @file llpc43xx_cgu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock Generation and Clock Control firmware
|
||||
* library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CGU CGU (Clock Generation Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_CGU_H_
|
||||
#define lpc43xx_CGU_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private Macros -------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Private_Macros CGU Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Branch clocks from CGU_BASE_SAFE */
|
||||
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
|
||||
|
||||
/** Check bit at specific position is clear or not */
|
||||
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
|
||||
/** Check bit at specific position is set or not */
|
||||
#define ISBITSET(x,bit) (x&(1<<bit))
|
||||
/** Set mask */
|
||||
#define ISMASKSET(x,mask) (x&mask)
|
||||
|
||||
/** CGU number of clock source */
|
||||
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU control mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU control enable mask bit */
|
||||
#define CGU_CTRL_EN_MASK 1
|
||||
/** CGU control clock-source mask bit */
|
||||
#define CGU_CTRL_SRC_MASK (0xF<<24)
|
||||
/** CGU control auto block mask bit */
|
||||
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU PLL1 mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU PLL1 feedback select mask bit */
|
||||
#define CGU_PLL1_FBSEL_MASK (1<<6)
|
||||
/** CGU PLL1 Input clock bypass control mask bit */
|
||||
#define CGU_PLL1_BYPASS_MASK (1<<1)
|
||||
/** CGU PLL1 direct CCO output mask bit */
|
||||
#define CGU_PLL1_DIRECT_MASK (1<<7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Types CGU Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief CGU enumeration
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU clock source enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
/* Clock Source */
|
||||
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
|
||||
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
|
||||
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
|
||||
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
|
||||
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
|
||||
CGU_CLKSRC_TCK, /**< TCK clock source */
|
||||
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
|
||||
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
|
||||
CGU_CLKSRC_PLL0_AUDIO,
|
||||
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
|
||||
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
|
||||
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
|
||||
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
|
||||
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
|
||||
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
|
||||
|
||||
/* Base */
|
||||
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
|
||||
CGU_BASE_USB0, /**< USB0 base clock */
|
||||
CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
|
||||
CGU_BASE_USB1, /**< USB1 base clock */
|
||||
CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
|
||||
CGU_BASE_SPIFI, /**< SPIFI base clock */
|
||||
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
|
||||
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
|
||||
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
|
||||
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
|
||||
CGU_BASE_LCD, /**< LCD base clock */
|
||||
CGU_BASE_ENET_CSR,
|
||||
CGU_BASE_SDIO, /**< SDIO base clock */
|
||||
CGU_BASE_SSP0, /**< SSP0 base clock */
|
||||
CGU_BASE_SSP1, /**< SSP1 base clock */
|
||||
CGU_BASE_UART0, /**< UART0 base clock */
|
||||
CGU_BASE_UART1, /**< UART1 base clock */
|
||||
CGU_BASE_UART2, /**< UART2 base clock */
|
||||
CGU_BASE_UART3, /**< UART3 base clock */
|
||||
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
|
||||
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
|
||||
CGU_BASE_OUT0,
|
||||
CGU_BASE_OUT1,
|
||||
CGU_ENTITY_NUM /**< Number or clock source entity */
|
||||
} CGU_ENTITY_T;
|
||||
|
||||
/*
|
||||
* @brief CGU PPL0 mode enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PLL0_MODE_1d = 0,
|
||||
CGU_PLL0_MODE_1c,
|
||||
CGU_PLL0_MODE_1b,
|
||||
CGU_PLL0_MODE_1a
|
||||
}CGU_PLL0_MODE;
|
||||
|
||||
/*
|
||||
* @brief CGU peripheral enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
|
||||
CGU_PERIPHERAL_ADC1, /**< ADC1 */
|
||||
CGU_PERIPHERAL_AES, /**< AES */
|
||||
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
|
||||
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
|
||||
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
|
||||
CGU_PERIPHERAL_CAN, /**< CAN */
|
||||
CGU_PERIPHERAL_CREG, /**< CREG */
|
||||
CGU_PERIPHERAL_DAC, /**< DAC */
|
||||
CGU_PERIPHERAL_DMA, /**< DMA */
|
||||
CGU_PERIPHERAL_EMC, /**< EMC */
|
||||
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
|
||||
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
|
||||
CGU_PERIPHERAL_GPIO, /**< GPIO */
|
||||
CGU_PERIPHERAL_I2C0, /**< I2C0 */
|
||||
CGU_PERIPHERAL_I2C1, /**< I2C1 */
|
||||
CGU_PERIPHERAL_I2S, /**< I2S */
|
||||
CGU_PERIPHERAL_LCD, /**< LCD */
|
||||
CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
|
||||
CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
|
||||
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
|
||||
CGU_PERIPHERAL_QEI, /**< QEI */
|
||||
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
|
||||
CGU_PERIPHERAL_SCT, /**< SCT */
|
||||
CGU_PERIPHERAL_SCU, /**< SCU */
|
||||
CGU_PERIPHERAL_SDIO, /**< SDIO */
|
||||
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
|
||||
CGU_PERIPHERAL_SSP0, /**< SSP0 */
|
||||
CGU_PERIPHERAL_SSP1, /**< SSP1 */
|
||||
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
|
||||
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
|
||||
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
|
||||
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
|
||||
CGU_PERIPHERAL_UART0, /**< UART0 */
|
||||
CGU_PERIPHERAL_UART1, /**< UART1 */
|
||||
CGU_PERIPHERAL_UART2, /**< UART2 */
|
||||
CGU_PERIPHERAL_UART3, /**< UART3 */
|
||||
CGU_PERIPHERAL_USB0, /**< USB0 */
|
||||
CGU_PERIPHERAL_USB1, /**< USB1 */
|
||||
CGU_PERIPHERAL_WWDT, /**< WWDT */
|
||||
CGU_PERIPHERAL_NUM
|
||||
} CGU_PERIPHERAL_T;
|
||||
|
||||
/**
|
||||
* @brief CGU error status enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_ERROR_SUCCESS = 0,
|
||||
CGU_ERROR_CONNECT_TOGETHER,
|
||||
CGU_ERROR_INVALID_ENTITY,
|
||||
CGU_ERROR_INVALID_CLOCK_SOURCE,
|
||||
CGU_ERROR_INVALID_PARAM,
|
||||
CGU_ERROR_FREQ_OUTOF_RANGE
|
||||
} CGU_ERROR;
|
||||
|
||||
/********************************************************************//**
|
||||
* @brief CGU structure definitions
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU peripheral clock structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RegBaseEntity; /**< Base register address */
|
||||
uint16_t RegBranchOffset; /**< Branch register offset */
|
||||
uint8_t PerBaseEntity; /**< Base peripheral address */
|
||||
uint16_t PerBranchOffset; /**< Base peripheral offset */
|
||||
uint8_t next; /**< Pointer to next structure */
|
||||
} CGU_PERIPHERAL_S;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Functions CGU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Clock generate initialize/de-initialize */
|
||||
uint32_t CGU_Init(void);
|
||||
uint32_t CGU_DeInit(void);
|
||||
|
||||
/** Clock Generator and Clock Control */
|
||||
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
|
||||
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
|
||||
|
||||
/** Clock Source and Base Clock operation */
|
||||
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
|
||||
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
|
||||
uint32_t CGU_SetPLL0(void);
|
||||
uint32_t CGU_SetPLL0audio(void);
|
||||
uint32_t CGU_SetPLL1(uint32_t mult);
|
||||
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
|
||||
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
|
||||
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
|
||||
void CGU_UpdateClock(void);
|
||||
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_CGU_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_cgu.h 2011-06-02
|
||||
*//**
|
||||
* @file llpc43xx_cgu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock Generation and Clock Control firmware
|
||||
* library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CGU CGU (Clock Generation Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_CGU_H_
|
||||
#define lpc43xx_CGU_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private Macros -------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Private_Macros CGU Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Branch clocks from CGU_BASE_SAFE */
|
||||
#define CGU_ENTITY_NONE CGU_ENTITY_NUM
|
||||
|
||||
/** Check bit at specific position is clear or not */
|
||||
#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
|
||||
/** Check bit at specific position is set or not */
|
||||
#define ISBITSET(x,bit) (x&(1<<bit))
|
||||
/** Set mask */
|
||||
#define ISMASKSET(x,mask) (x&mask)
|
||||
|
||||
/** CGU number of clock source */
|
||||
#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU control mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU control enable mask bit */
|
||||
#define CGU_CTRL_EN_MASK 1
|
||||
/** CGU control clock-source mask bit */
|
||||
#define CGU_CTRL_SRC_MASK (0xF<<24)
|
||||
/** CGU control auto block mask bit */
|
||||
#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CGU PLL1 mask bit definitions
|
||||
**********************************************************************/
|
||||
/** CGU PLL1 feedback select mask bit */
|
||||
#define CGU_PLL1_FBSEL_MASK (1<<6)
|
||||
/** CGU PLL1 Input clock bypass control mask bit */
|
||||
#define CGU_PLL1_BYPASS_MASK (1<<1)
|
||||
/** CGU PLL1 direct CCO output mask bit */
|
||||
#define CGU_PLL1_DIRECT_MASK (1<<7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Types CGU Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief CGU enumeration
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU clock source enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
/* Clock Source */
|
||||
CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
|
||||
CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
|
||||
CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
|
||||
CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
|
||||
CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
|
||||
CGU_CLKSRC_TCK, /**< TCK clock source */
|
||||
CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
|
||||
CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
|
||||
CGU_CLKSRC_PLL0_AUDIO,
|
||||
CGU_CLKSRC_PLL1, /**< PLL1 clock source */
|
||||
CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
|
||||
CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
|
||||
CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
|
||||
CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
|
||||
CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
|
||||
|
||||
/* Base */
|
||||
CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
|
||||
CGU_BASE_USB0, /**< USB0 base clock */
|
||||
CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
|
||||
CGU_BASE_USB1, /**< USB1 base clock */
|
||||
CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
|
||||
CGU_BASE_SPIFI, /**< SPIFI base clock */
|
||||
CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
|
||||
CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
|
||||
CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
|
||||
CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
|
||||
CGU_BASE_LCD, /**< LCD base clock */
|
||||
CGU_BASE_ENET_CSR,
|
||||
CGU_BASE_SDIO, /**< SDIO base clock */
|
||||
CGU_BASE_SSP0, /**< SSP0 base clock */
|
||||
CGU_BASE_SSP1, /**< SSP1 base clock */
|
||||
CGU_BASE_UART0, /**< UART0 base clock */
|
||||
CGU_BASE_UART1, /**< UART1 base clock */
|
||||
CGU_BASE_UART2, /**< UART2 base clock */
|
||||
CGU_BASE_UART3, /**< UART3 base clock */
|
||||
CGU_BASE_CLKOUT, /**< CLKOUT base clock */
|
||||
CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
|
||||
CGU_BASE_OUT0,
|
||||
CGU_BASE_OUT1,
|
||||
CGU_ENTITY_NUM /**< Number or clock source entity */
|
||||
} CGU_ENTITY_T;
|
||||
|
||||
/*
|
||||
* @brief CGU PPL0 mode enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PLL0_MODE_1d = 0,
|
||||
CGU_PLL0_MODE_1c,
|
||||
CGU_PLL0_MODE_1b,
|
||||
CGU_PLL0_MODE_1a
|
||||
}CGU_PLL0_MODE;
|
||||
|
||||
/*
|
||||
* @brief CGU peripheral enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
|
||||
CGU_PERIPHERAL_ADC1, /**< ADC1 */
|
||||
CGU_PERIPHERAL_AES, /**< AES */
|
||||
// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
|
||||
CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
|
||||
CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
|
||||
CGU_PERIPHERAL_CAN, /**< CAN */
|
||||
CGU_PERIPHERAL_CREG, /**< CREG */
|
||||
CGU_PERIPHERAL_DAC, /**< DAC */
|
||||
CGU_PERIPHERAL_DMA, /**< DMA */
|
||||
CGU_PERIPHERAL_EMC, /**< EMC */
|
||||
CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
|
||||
CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
|
||||
CGU_PERIPHERAL_GPIO, /**< GPIO */
|
||||
CGU_PERIPHERAL_I2C0, /**< I2C0 */
|
||||
CGU_PERIPHERAL_I2C1, /**< I2C1 */
|
||||
CGU_PERIPHERAL_I2S, /**< I2S */
|
||||
CGU_PERIPHERAL_LCD, /**< LCD */
|
||||
CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
|
||||
CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
|
||||
CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
|
||||
CGU_PERIPHERAL_QEI, /**< QEI */
|
||||
CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
|
||||
CGU_PERIPHERAL_SCT, /**< SCT */
|
||||
CGU_PERIPHERAL_SCU, /**< SCU */
|
||||
CGU_PERIPHERAL_SDIO, /**< SDIO */
|
||||
CGU_PERIPHERAL_SPIFI, /**< SPIFI */
|
||||
CGU_PERIPHERAL_SSP0, /**< SSP0 */
|
||||
CGU_PERIPHERAL_SSP1, /**< SSP1 */
|
||||
CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
|
||||
CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
|
||||
CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
|
||||
CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
|
||||
CGU_PERIPHERAL_UART0, /**< UART0 */
|
||||
CGU_PERIPHERAL_UART1, /**< UART1 */
|
||||
CGU_PERIPHERAL_UART2, /**< UART2 */
|
||||
CGU_PERIPHERAL_UART3, /**< UART3 */
|
||||
CGU_PERIPHERAL_USB0, /**< USB0 */
|
||||
CGU_PERIPHERAL_USB1, /**< USB1 */
|
||||
CGU_PERIPHERAL_WWDT, /**< WWDT */
|
||||
CGU_PERIPHERAL_NUM
|
||||
} CGU_PERIPHERAL_T;
|
||||
|
||||
/**
|
||||
* @brief CGU error status enumerate definition
|
||||
*/
|
||||
typedef enum {
|
||||
CGU_ERROR_SUCCESS = 0,
|
||||
CGU_ERROR_CONNECT_TOGETHER,
|
||||
CGU_ERROR_INVALID_ENTITY,
|
||||
CGU_ERROR_INVALID_CLOCK_SOURCE,
|
||||
CGU_ERROR_INVALID_PARAM,
|
||||
CGU_ERROR_FREQ_OUTOF_RANGE
|
||||
} CGU_ERROR;
|
||||
|
||||
/********************************************************************//**
|
||||
* @brief CGU structure definitions
|
||||
**********************************************************************/
|
||||
/*
|
||||
* @brief CGU peripheral clock structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RegBaseEntity; /**< Base register address */
|
||||
uint16_t RegBranchOffset; /**< Branch register offset */
|
||||
uint8_t PerBaseEntity; /**< Base peripheral address */
|
||||
uint16_t PerBranchOffset; /**< Base peripheral offset */
|
||||
uint8_t next; /**< Pointer to next structure */
|
||||
} CGU_PERIPHERAL_S;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CGU_Public_Functions CGU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Clock generate initialize/de-initialize */
|
||||
uint32_t CGU_Init(void);
|
||||
uint32_t CGU_DeInit(void);
|
||||
|
||||
/** Clock Generator and Clock Control */
|
||||
uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
|
||||
uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
|
||||
|
||||
/** Clock Source and Base Clock operation */
|
||||
uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
|
||||
uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
|
||||
uint32_t CGU_SetPLL0(void);
|
||||
uint32_t CGU_SetPLL0audio(void);
|
||||
uint32_t CGU_SetPLL1(uint32_t mult);
|
||||
uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
|
||||
uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
|
||||
uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
|
||||
void CGU_UpdateClock(void);
|
||||
uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_CGU_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@ -1,116 +1,116 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_gpio.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_gpio.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for GPIO firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO GPIO (General Purpose I/O)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_GPIO_H_
|
||||
#define lpc43xx_GPIO_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Macros GPIO Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Types GPIO Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Functions GPIO Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* GPIO style ------------------------------- */
|
||||
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
uint32_t GPIO_ReadValue(uint8_t portNum);
|
||||
|
||||
#ifdef GPIO_INT
|
||||
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
|
||||
#endif
|
||||
|
||||
|
||||
/* FIO (word-accessible) style ------------------------------- */
|
||||
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
uint32_t FIO_ReadValue(uint8_t portNum);
|
||||
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
|
||||
|
||||
#ifdef GPIO_INT
|
||||
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_GPIO_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_gpio.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_gpio.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for GPIO firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO GPIO (General Purpose I/O)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_GPIO_H_
|
||||
#define lpc43xx_GPIO_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Macros GPIO Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Types GPIO Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Functions GPIO Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* GPIO style ------------------------------- */
|
||||
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
uint32_t GPIO_ReadValue(uint8_t portNum);
|
||||
|
||||
#ifdef GPIO_INT
|
||||
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
|
||||
#endif
|
||||
|
||||
|
||||
/* FIO (word-accessible) style ------------------------------- */
|
||||
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
uint32_t FIO_ReadValue(uint8_t portNum);
|
||||
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
|
||||
|
||||
#ifdef GPIO_INT
|
||||
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_GPIO_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@ -1,388 +1,388 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_i2c.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_i2c.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for I2C firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup I2C I2C (Inter-Integrated Circuit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_I2C_H_
|
||||
#define lpc43xx_I2C_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*******************************************************************//**
|
||||
* I2C Control Set register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
|
||||
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
|
||||
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
|
||||
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
|
||||
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
|
||||
|
||||
/*******************************************************************//**
|
||||
* I2C Control Clear register description
|
||||
*********************************************************************/
|
||||
/** Assert acknowledge Clear bit */
|
||||
#define I2C_I2CONCLR_AAC ((1<<2))
|
||||
/** I2C interrupt Clear bit */
|
||||
#define I2C_I2CONCLR_SIC ((1<<3))
|
||||
/** START flag Clear bit */
|
||||
#define I2C_I2CONCLR_STAC ((1<<5))
|
||||
/** I2C interface Disable bit */
|
||||
#define I2C_I2CONCLR_I2ENC ((1<<6))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Status Code definition (I2C Status register)
|
||||
*********************************************************************/
|
||||
/* Return Code in I2C status register */
|
||||
#define I2C_STAT_CODE_BITMASK ((0xF8))
|
||||
|
||||
/* I2C return status code definitions ----------------------------- */
|
||||
|
||||
/** No relevant information */
|
||||
#define I2C_I2STAT_NO_INF ((0xF8))
|
||||
|
||||
/* Master transmit mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_RESTART ((0x10))
|
||||
/** SLA+W has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
|
||||
/** SLA+W has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
|
||||
/** Arbitration lost in SLA+R/W or Data bytes */
|
||||
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
|
||||
|
||||
/* Master receive mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_RESTART ((0x10))
|
||||
/** Arbitration lost */
|
||||
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
|
||||
/** SLA+R has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
|
||||
/** SLA+R has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
|
||||
/** Data has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
|
||||
/** Data has been received, NACK has been return */
|
||||
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
|
||||
|
||||
/* Slave receive mode -------------------------------------------- */
|
||||
/** Own slave address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
|
||||
/** Own SLA+W has been received, ACK returned */
|
||||
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
|
||||
|
||||
/** General call address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
|
||||
|
||||
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
|
||||
/** General call address has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
|
||||
|
||||
/** Previously addressed with own SLV address;
|
||||
* Data has been received, ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
|
||||
/** Previously addressed with own SLA;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
|
||||
/** A STOP condition or repeated START condition has
|
||||
* been received while still addressed as SLV/REC
|
||||
* (Slave Receive) or SLV/TRX (Slave Transmit) */
|
||||
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
|
||||
|
||||
/** Slave transmit mode */
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
|
||||
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
|
||||
/** Last data byte in I2DAT has been transmitted (AA = 0);
|
||||
ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
|
||||
|
||||
/** Time out in case of using I2C slave mode */
|
||||
#define I2C_SLAVE_TIME_OUT 0x10000UL
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data register definition
|
||||
*********************************************************************/
|
||||
/** Mask for I2DAT register*/
|
||||
#define I2C_I2DAT_BITMASK ((0xFF))
|
||||
|
||||
/** Idle data value will be send out in slave mode in case of the actual
|
||||
* expecting data requested from the master is greater than its sending data
|
||||
* length that can be supported */
|
||||
#define I2C_I2DAT_IDLE_CHAR (0xFF)
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Monitor mode control register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
|
||||
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
|
||||
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
|
||||
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data buffer register description
|
||||
*********************************************************************/
|
||||
/** I2C Data buffer register bit mask */
|
||||
#define I2DATA_BUFFER_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Slave Address registers definition
|
||||
*********************************************************************/
|
||||
/** General Call enable bit */
|
||||
#define I2C_I2ADR_GC ((1<<0))
|
||||
/** I2C Slave Address registers bit mask */
|
||||
#define I2C_I2ADR_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Mask Register definition
|
||||
*********************************************************************/
|
||||
/** I2C Mask Register mask field */
|
||||
#define I2C_I2MASK_MASK(n) ((n&0xFE))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL HIGH duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL HIGH duty cycle Register bit mask */
|
||||
#define I2C_I2SCLH_BITMASK ((0xFFFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL LOW duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL LOW duty cycle Register bit mask */
|
||||
#define I2C_I2SCLL_BITMASK ((0xFFFF))
|
||||
|
||||
/* I2C status values */
|
||||
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
|
||||
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
|
||||
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
|
||||
|
||||
/*********************************************************************//**
|
||||
* I2C monitor control configuration defines
|
||||
**********************************************************************/
|
||||
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
|
||||
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
|
||||
|
||||
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
|
||||
/* Macros check I2C slave address */
|
||||
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
|
||||
|
||||
/** Macro to determine if it is valid SSP port number */
|
||||
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|
||||
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
|
||||
|
||||
/* Macros check I2C monitor configuration type */
|
||||
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Types I2C Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Own slave address setting structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
|
||||
should be in range from 0..3
|
||||
*/
|
||||
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
|
||||
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
|
||||
when I2C control being in Slave mode, should be:
|
||||
- ENABLE: Enable General Call function.
|
||||
- DISABLE: Disable General Call function.
|
||||
*/
|
||||
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
|
||||
which is set to '1' will cause an automatic compare on
|
||||
the corresponding bit of the received address when it
|
||||
is compared to the SlaveAddr_7bit value associated with this
|
||||
mask register. In other words, bits in SlaveAddr_7bit value
|
||||
which are masked are not taken into account in determining
|
||||
an address match
|
||||
*/
|
||||
} I2C_OWNSLAVEADDR_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Master transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
|
||||
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
|
||||
is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
|
||||
is not used*/
|
||||
uint32_t tx_count; /**< Current Transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
|
||||
is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is
|
||||
not used */
|
||||
uint32_t rx_count; /**< Current Receive data counter */
|
||||
uint32_t retransmissions_max; /**< Max Re-Transmission value */
|
||||
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to Call back function when transmission complete
|
||||
used in interrupt transfer mode */
|
||||
} I2C_M_SETUP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Slave transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
|
||||
uint32_t tx_count; /**< Current transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
|
||||
uint32_t rx_count; /**< Current receive data counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to call-back function when transmission complete
|
||||
used by interrupt transfer mode */
|
||||
} I2C_S_SETUP_Type;
|
||||
|
||||
/**
|
||||
* @brief Transfer option type definitions
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
|
||||
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
|
||||
} I2C_TRANSFER_OPT_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Functions I2C Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I2C Init/DeInit functions ---------- */
|
||||
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
|
||||
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
|
||||
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
|
||||
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* I2C transfer data functions -------- */
|
||||
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
|
||||
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
|
||||
|
||||
/* I2C Monitor functions ---------------*/
|
||||
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
|
||||
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
|
||||
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
|
||||
|
||||
/* I2C Interrupt handler functions ------*/
|
||||
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
|
||||
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
|
||||
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_I2C_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_i2c.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_i2c.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for I2C firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup I2C I2C (Inter-Integrated Circuit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef lpc43xx_I2C_H_
|
||||
#define lpc43xx_I2C_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC43xx.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*******************************************************************//**
|
||||
* I2C Control Set register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
|
||||
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
|
||||
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
|
||||
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
|
||||
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
|
||||
|
||||
/*******************************************************************//**
|
||||
* I2C Control Clear register description
|
||||
*********************************************************************/
|
||||
/** Assert acknowledge Clear bit */
|
||||
#define I2C_I2CONCLR_AAC ((1<<2))
|
||||
/** I2C interrupt Clear bit */
|
||||
#define I2C_I2CONCLR_SIC ((1<<3))
|
||||
/** START flag Clear bit */
|
||||
#define I2C_I2CONCLR_STAC ((1<<5))
|
||||
/** I2C interface Disable bit */
|
||||
#define I2C_I2CONCLR_I2ENC ((1<<6))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Status Code definition (I2C Status register)
|
||||
*********************************************************************/
|
||||
/* Return Code in I2C status register */
|
||||
#define I2C_STAT_CODE_BITMASK ((0xF8))
|
||||
|
||||
/* I2C return status code definitions ----------------------------- */
|
||||
|
||||
/** No relevant information */
|
||||
#define I2C_I2STAT_NO_INF ((0xF8))
|
||||
|
||||
/* Master transmit mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_RESTART ((0x10))
|
||||
/** SLA+W has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
|
||||
/** SLA+W has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
|
||||
/** Arbitration lost in SLA+R/W or Data bytes */
|
||||
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
|
||||
|
||||
/* Master receive mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_START ((0x08))
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_RESTART ((0x10))
|
||||
/** Arbitration lost */
|
||||
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
|
||||
/** SLA+R has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
|
||||
/** SLA+R has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
|
||||
/** Data has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
|
||||
/** Data has been received, NACK has been return */
|
||||
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
|
||||
|
||||
/* Slave receive mode -------------------------------------------- */
|
||||
/** Own slave address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
|
||||
/** Own SLA+W has been received, ACK returned */
|
||||
//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
|
||||
|
||||
/** General call address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
|
||||
|
||||
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
|
||||
/** General call address has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
|
||||
|
||||
/** Previously addressed with own SLV address;
|
||||
* Data has been received, ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
|
||||
/** Previously addressed with own SLA;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
|
||||
/** A STOP condition or repeated START condition has
|
||||
* been received while still addressed as SLV/REC
|
||||
* (Slave Receive) or SLV/TRX (Slave Transmit) */
|
||||
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
|
||||
|
||||
/** Slave transmit mode */
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
|
||||
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
|
||||
/** Last data byte in I2DAT has been transmitted (AA = 0);
|
||||
ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
|
||||
|
||||
/** Time out in case of using I2C slave mode */
|
||||
#define I2C_SLAVE_TIME_OUT 0x10000UL
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data register definition
|
||||
*********************************************************************/
|
||||
/** Mask for I2DAT register*/
|
||||
#define I2C_I2DAT_BITMASK ((0xFF))
|
||||
|
||||
/** Idle data value will be send out in slave mode in case of the actual
|
||||
* expecting data requested from the master is greater than its sending data
|
||||
* length that can be supported */
|
||||
#define I2C_I2DAT_IDLE_CHAR (0xFF)
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Monitor mode control register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
|
||||
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
|
||||
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
|
||||
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data buffer register description
|
||||
*********************************************************************/
|
||||
/** I2C Data buffer register bit mask */
|
||||
#define I2DATA_BUFFER_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Slave Address registers definition
|
||||
*********************************************************************/
|
||||
/** General Call enable bit */
|
||||
#define I2C_I2ADR_GC ((1<<0))
|
||||
/** I2C Slave Address registers bit mask */
|
||||
#define I2C_I2ADR_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Mask Register definition
|
||||
*********************************************************************/
|
||||
/** I2C Mask Register mask field */
|
||||
#define I2C_I2MASK_MASK(n) ((n&0xFE))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL HIGH duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL HIGH duty cycle Register bit mask */
|
||||
#define I2C_I2SCLH_BITMASK ((0xFFFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL LOW duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL LOW duty cycle Register bit mask */
|
||||
#define I2C_I2SCLL_BITMASK ((0xFFFF))
|
||||
|
||||
/* I2C status values */
|
||||
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
|
||||
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
|
||||
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
|
||||
|
||||
/*********************************************************************//**
|
||||
* I2C monitor control configuration defines
|
||||
**********************************************************************/
|
||||
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
|
||||
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
|
||||
|
||||
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
|
||||
/* Macros check I2C slave address */
|
||||
#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
|
||||
|
||||
/** Macro to determine if it is valid SSP port number */
|
||||
#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
|
||||
|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
|
||||
|
||||
/* Macros check I2C monitor configuration type */
|
||||
#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Types I2C Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Own slave address setting structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
|
||||
should be in range from 0..3
|
||||
*/
|
||||
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
|
||||
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
|
||||
when I2C control being in Slave mode, should be:
|
||||
- ENABLE: Enable General Call function.
|
||||
- DISABLE: Disable General Call function.
|
||||
*/
|
||||
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
|
||||
which is set to '1' will cause an automatic compare on
|
||||
the corresponding bit of the received address when it
|
||||
is compared to the SlaveAddr_7bit value associated with this
|
||||
mask register. In other words, bits in SlaveAddr_7bit value
|
||||
which are masked are not taken into account in determining
|
||||
an address match
|
||||
*/
|
||||
} I2C_OWNSLAVEADDR_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Master transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
|
||||
uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
|
||||
is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
|
||||
is not used*/
|
||||
uint32_t tx_count; /**< Current Transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
|
||||
is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is
|
||||
not used */
|
||||
uint32_t rx_count; /**< Current Receive data counter */
|
||||
uint32_t retransmissions_max; /**< Max Re-Transmission value */
|
||||
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to Call back function when transmission complete
|
||||
used in interrupt transfer mode */
|
||||
} I2C_M_SETUP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Slave transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */
|
||||
uint32_t tx_count; /**< Current transmit data counter */
|
||||
uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */
|
||||
uint32_t rx_count; /**< Current receive data counter */
|
||||
uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to call-back function when transmission complete
|
||||
used by interrupt transfer mode */
|
||||
} I2C_S_SETUP_Type;
|
||||
|
||||
/**
|
||||
* @brief Transfer option type definitions
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
|
||||
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
|
||||
} I2C_TRANSFER_OPT_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Functions I2C Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I2C Init/DeInit functions ---------- */
|
||||
void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
|
||||
void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
|
||||
//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
|
||||
void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* I2C transfer data functions -------- */
|
||||
Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
|
||||
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
|
||||
uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
|
||||
|
||||
/* I2C Monitor functions ---------------*/
|
||||
void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
|
||||
void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
|
||||
BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
|
||||
|
||||
/* I2C Interrupt handler functions ------*/
|
||||
void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
|
||||
void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
|
||||
void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* lpc43xx_I2C_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@ -1,136 +1,136 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_scu.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_scu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SCU firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors’
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SCU SCU (System Control Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup SCT_Private_Macros SCT Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Port offset definition */
|
||||
#define PORT_OFFSET 0x80
|
||||
/** Pin offset definition */
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin mode defines, following partly a definition from older chip architectures */
|
||||
#define MD_PUP (0x0 << 3)
|
||||
#define MD_BUK (0x1 << 3)
|
||||
#define MD_PLN (0x2 << 3)
|
||||
#define MD_PDN (0x3 << 3)
|
||||
#define MD_EHS (0x1 << 5)
|
||||
#define MD_EZI (0x1 << 6)
|
||||
#define MD_ZI (0x1 << 7)
|
||||
#define MD_EHD0 (0x1 << 8)
|
||||
#define MD_EHD1 (0x1 << 9)
|
||||
#define MD_EHD2 (0x3 << 8)
|
||||
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
|
||||
|
||||
|
||||
/* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
|
||||
/* Defines for SFSPx_y pin configuration registers */
|
||||
#define PDN_ENABLE (1 << 3) // Pull-down enable
|
||||
#define PDN_DISABLE (0 << 3) // Pull-down disable
|
||||
#define PUP_ENABLE (0 << 4) // Pull-up enable
|
||||
#define PUP_DISABLE (1 << 4) // Pull-up disable
|
||||
#define SLEWRATE_SLOW (0 << 5) // Slew rate for low noise with medium speed
|
||||
#define SLEWRATE_FAST (1 << 5) // Slew rate for medium noise with fast speed
|
||||
#define INBUF_ENABLE (1 << 6) // Input buffer
|
||||
#define INBUF_DISABLE (0 << 6) // Input buffer
|
||||
#define FILTER_ENABLE (0 << 7) // Glitch filter (for signals below 30MHz)
|
||||
#define FILTER_DISABLE (1 << 7) // No glitch filter (for signals above 30MHz)
|
||||
#define DRIVE_8MA (1 << 8) // Drive strength of 8mA
|
||||
#define DRIVE_14MA (1 << 9) // Drive strength of 14mA
|
||||
#define DRIVE_20MA (3 << 8) // Drive strength of 20mA
|
||||
|
||||
|
||||
/* Configuration examples for various I/O pins */
|
||||
#define EMC_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define LCD_PINCONFIG (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_IN (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_OUT (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define GPIO_PUP (PUP_ENABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_PDN (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define UART_RX_TX (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define SSP_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
|
||||
/* Pin function */
|
||||
#define FUNC0 0x0 /** Function 0 */
|
||||
#define FUNC1 0x1 /** Function 1 */
|
||||
#define FUNC2 0x2 /** Function 2 */
|
||||
#define FUNC3 0x3 /** Function 3 */
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
|
||||
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SCU_Public_Functions SCU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* $Id$ lpc43xx_scu.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc43xx_scu.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SCU firmware library on lpc43xx
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors’
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SCU SCU (System Control Unit)
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __SCU_H
|
||||
#define __SCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup SCT_Private_Macros SCT Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Port offset definition */
|
||||
#define PORT_OFFSET 0x80
|
||||
/** Pin offset definition */
|
||||
#define PIN_OFFSET 0x04
|
||||
|
||||
/* Pin mode defines, following partly a definition from older chip architectures */
|
||||
#define MD_PUP (0x0 << 3)
|
||||
#define MD_BUK (0x1 << 3)
|
||||
#define MD_PLN (0x2 << 3)
|
||||
#define MD_PDN (0x3 << 3)
|
||||
#define MD_EHS (0x1 << 5)
|
||||
#define MD_EZI (0x1 << 6)
|
||||
#define MD_ZI (0x1 << 7)
|
||||
#define MD_EHD0 (0x1 << 8)
|
||||
#define MD_EHD1 (0x1 << 9)
|
||||
#define MD_EHD2 (0x3 << 8)
|
||||
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
|
||||
|
||||
|
||||
/* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
|
||||
/* Defines for SFSPx_y pin configuration registers */
|
||||
#define PDN_ENABLE (1 << 3) // Pull-down enable
|
||||
#define PDN_DISABLE (0 << 3) // Pull-down disable
|
||||
#define PUP_ENABLE (0 << 4) // Pull-up enable
|
||||
#define PUP_DISABLE (1 << 4) // Pull-up disable
|
||||
#define SLEWRATE_SLOW (0 << 5) // Slew rate for low noise with medium speed
|
||||
#define SLEWRATE_FAST (1 << 5) // Slew rate for medium noise with fast speed
|
||||
#define INBUF_ENABLE (1 << 6) // Input buffer
|
||||
#define INBUF_DISABLE (0 << 6) // Input buffer
|
||||
#define FILTER_ENABLE (0 << 7) // Glitch filter (for signals below 30MHz)
|
||||
#define FILTER_DISABLE (1 << 7) // No glitch filter (for signals above 30MHz)
|
||||
#define DRIVE_8MA (1 << 8) // Drive strength of 8mA
|
||||
#define DRIVE_14MA (1 << 9) // Drive strength of 14mA
|
||||
#define DRIVE_20MA (3 << 8) // Drive strength of 20mA
|
||||
|
||||
|
||||
/* Configuration examples for various I/O pins */
|
||||
#define EMC_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define LCD_PINCONFIG (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_IN (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define CLK_OUT (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
#define GPIO_PUP (PUP_ENABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_PDN (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define UART_RX_TX (PUP_DISABLE | PDN_ENABLE | SLEWRATE_SLOW | INBUF_ENABLE | FILTER_ENABLE )
|
||||
#define SSP_IO (PUP_ENABLE | PDN_ENABLE | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
|
||||
|
||||
|
||||
/* Pin function */
|
||||
#define FUNC0 0x0 /** Function 0 */
|
||||
#define FUNC1 0x1 /** Function 1 */
|
||||
#define FUNC2 0x2 /** Function 2 */
|
||||
#define FUNC3 0x3 /** Function 3 */
|
||||
#define FUNC4 0x4
|
||||
#define FUNC5 0x5
|
||||
#define FUNC6 0x6
|
||||
#define FUNC7 0x7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )
|
||||
#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SCU_Public_Functions SCU Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end __SCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,216 +1,216 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_types.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_types.h
|
||||
* @brief Contains the NXP ABL typedefs for C standard types.
|
||||
* It is intended to be used in ISO C conforming development
|
||||
* environments and checks for this insofar as it is possible
|
||||
* to do so.
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors’
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Type group ----------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types LPC_Types
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC_TYPES_H
|
||||
#define LPC_TYPES_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Boolean Type definition
|
||||
*/
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
|
||||
|
||||
/**
|
||||
* @brief Flag Status and Interrupt Flag Status type definition
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
|
||||
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
|
||||
|
||||
/**
|
||||
* @brief Functional State Definition
|
||||
*/
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
|
||||
|
||||
/**
|
||||
* @ Status type definition
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
|
||||
|
||||
|
||||
/**
|
||||
* Read/Write transfer type mode (Block or non-block)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NONE_BLOCKING = 0, /**< None Blocking type */
|
||||
BLOCKING, /**< Blocking type */
|
||||
} TRANSFER_BLOCK_Type;
|
||||
|
||||
|
||||
/** Pointer to Function returning Void (any number of parameters) */
|
||||
typedef void (*PFV)();
|
||||
|
||||
/** Pointer to Function returning int32_t (any number of parameters) */
|
||||
typedef int32_t(*PFI)();
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* _BIT(n) sets the bit at position "n"
|
||||
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "(_BIT(3) | _BIT(7))".
|
||||
*/
|
||||
#undef _BIT
|
||||
/* Set bit macro */
|
||||
#define _BIT(n) (1<<(n))
|
||||
|
||||
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
|
||||
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
|
||||
*/
|
||||
#undef _SBF
|
||||
/* Set bit field macro */
|
||||
#define _SBF(f,v) ((v)<<(f))
|
||||
|
||||
/* _BITMASK constructs a symbol with 'field_width' least significant
|
||||
* bits set.
|
||||
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
|
||||
* The symbol is intended to be used to limit the bit field width
|
||||
* thusly:
|
||||
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
|
||||
* If "any_expression" results in a value that is larger than can be
|
||||
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
|
||||
* used with the _SBF example above, the example would be written:
|
||||
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
|
||||
* This ensures that the value written to a_reg is no wider than
|
||||
* 16 bits, and makes the code easier to read and understand.
|
||||
*/
|
||||
#undef _BITMASK
|
||||
/* Bitmask creation macro */
|
||||
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
|
||||
|
||||
/* NULL pointer */
|
||||
#ifndef NULL
|
||||
#define NULL ((void*) 0)
|
||||
#endif
|
||||
|
||||
/* Number of elements in an array */
|
||||
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
|
||||
|
||||
/* Static data/function define */
|
||||
#define STATIC static
|
||||
/* External data/function define */
|
||||
#define EXTERN extern
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Old Type Definition compatibility ------------------------------------------ */
|
||||
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** SMA type for character type */
|
||||
typedef char CHAR;
|
||||
|
||||
/** SMA type for 8 bit unsigned value */
|
||||
typedef uint8_t UNS_8;
|
||||
|
||||
/** SMA type for 8 bit signed value */
|
||||
typedef int8_t INT_8;
|
||||
|
||||
/** SMA type for 16 bit unsigned value */
|
||||
typedef uint16_t UNS_16;
|
||||
|
||||
/** SMA type for 16 bit signed value */
|
||||
typedef int16_t INT_16;
|
||||
|
||||
/** SMA type for 32 bit unsigned value */
|
||||
typedef uint32_t UNS_32;
|
||||
|
||||
/** SMA type for 32 bit signed value */
|
||||
typedef int32_t INT_32;
|
||||
|
||||
/** SMA type for 64 bit signed value */
|
||||
typedef int64_t INT_64;
|
||||
|
||||
/** SMA type for 64 bit unsigned value */
|
||||
typedef uint64_t UNS_64;
|
||||
|
||||
/** 32 bit boolean type */
|
||||
typedef Bool BOOL_32;
|
||||
|
||||
/** 16 bit boolean type */
|
||||
typedef Bool BOOL_16;
|
||||
|
||||
/** 8 bit boolean type */
|
||||
typedef Bool BOOL_8;
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#define INLINE __inline
|
||||
#else
|
||||
#define INLINE inline
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* LPC_TYPES_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_types.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_types.h
|
||||
* @brief Contains the NXP ABL typedefs for C standard types.
|
||||
* It is intended to be used in ISO C conforming development
|
||||
* environments and checks for this insofar as it is possible
|
||||
* to do so.
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors’
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Type group ----------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types LPC_Types
|
||||
* @ingroup LPC4300CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef LPC_TYPES_H
|
||||
#define LPC_TYPES_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Boolean Type definition
|
||||
*/
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
|
||||
|
||||
/**
|
||||
* @brief Flag Status and Interrupt Flag Status type definition
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
|
||||
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
|
||||
|
||||
/**
|
||||
* @brief Functional State Definition
|
||||
*/
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
|
||||
|
||||
/**
|
||||
* @ Status type definition
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
|
||||
|
||||
|
||||
/**
|
||||
* Read/Write transfer type mode (Block or non-block)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NONE_BLOCKING = 0, /**< None Blocking type */
|
||||
BLOCKING, /**< Blocking type */
|
||||
} TRANSFER_BLOCK_Type;
|
||||
|
||||
|
||||
/** Pointer to Function returning Void (any number of parameters) */
|
||||
typedef void (*PFV)();
|
||||
|
||||
/** Pointer to Function returning int32_t (any number of parameters) */
|
||||
typedef int32_t(*PFI)();
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* _BIT(n) sets the bit at position "n"
|
||||
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "(_BIT(3) | _BIT(7))".
|
||||
*/
|
||||
#undef _BIT
|
||||
/* Set bit macro */
|
||||
#define _BIT(n) (1<<(n))
|
||||
|
||||
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
|
||||
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
|
||||
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
|
||||
*/
|
||||
#undef _SBF
|
||||
/* Set bit field macro */
|
||||
#define _SBF(f,v) ((v)<<(f))
|
||||
|
||||
/* _BITMASK constructs a symbol with 'field_width' least significant
|
||||
* bits set.
|
||||
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
|
||||
* The symbol is intended to be used to limit the bit field width
|
||||
* thusly:
|
||||
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
|
||||
* If "any_expression" results in a value that is larger than can be
|
||||
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
|
||||
* used with the _SBF example above, the example would be written:
|
||||
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
|
||||
* This ensures that the value written to a_reg is no wider than
|
||||
* 16 bits, and makes the code easier to read and understand.
|
||||
*/
|
||||
#undef _BITMASK
|
||||
/* Bitmask creation macro */
|
||||
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
|
||||
|
||||
/* NULL pointer */
|
||||
#ifndef NULL
|
||||
#define NULL ((void*) 0)
|
||||
#endif
|
||||
|
||||
/* Number of elements in an array */
|
||||
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
|
||||
|
||||
/* Static data/function define */
|
||||
#define STATIC static
|
||||
/* External data/function define */
|
||||
#define EXTERN extern
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Old Type Definition compatibility ------------------------------------------ */
|
||||
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** SMA type for character type */
|
||||
typedef char CHAR;
|
||||
|
||||
/** SMA type for 8 bit unsigned value */
|
||||
typedef uint8_t UNS_8;
|
||||
|
||||
/** SMA type for 8 bit signed value */
|
||||
typedef int8_t INT_8;
|
||||
|
||||
/** SMA type for 16 bit unsigned value */
|
||||
typedef uint16_t UNS_16;
|
||||
|
||||
/** SMA type for 16 bit signed value */
|
||||
typedef int16_t INT_16;
|
||||
|
||||
/** SMA type for 32 bit unsigned value */
|
||||
typedef uint32_t UNS_32;
|
||||
|
||||
/** SMA type for 32 bit signed value */
|
||||
typedef int32_t INT_32;
|
||||
|
||||
/** SMA type for 64 bit signed value */
|
||||
typedef int64_t INT_64;
|
||||
|
||||
/** SMA type for 64 bit unsigned value */
|
||||
typedef uint64_t UNS_64;
|
||||
|
||||
/** 32 bit boolean type */
|
||||
typedef Bool BOOL_32;
|
||||
|
||||
/** 16 bit boolean type */
|
||||
typedef Bool BOOL_16;
|
||||
|
||||
/** 8 bit boolean type */
|
||||
typedef Bool BOOL_8;
|
||||
|
||||
#ifdef __CC_ARM
|
||||
#define INLINE __inline
|
||||
#else
|
||||
#define INLINE inline
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* LPC_TYPES_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@ -1,50 +1,50 @@
|
||||
/**********************************************************************
|
||||
* $Id$ system_lpc43xx.h 2011-06-02
|
||||
*//**
|
||||
* @file system_lpc43xx.h
|
||||
* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_lpc43xx_H
|
||||
#define __SYSTEM_lpc43xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_lpc43xx_H */
|
||||
/**********************************************************************
|
||||
* $Id$ system_lpc43xx.h 2011-06-02
|
||||
*//**
|
||||
* @file system_lpc43xx.h
|
||||
* @brief Cortex-M3 Device System Header File for NXP lpc43xx Series.
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_lpc43xx_H
|
||||
#define __SYSTEM_lpc43xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_lpc43xx_H */
|
||||
|
||||
@ -219,7 +219,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagError</name>
|
||||
<state></state>
|
||||
<state>Pa050</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCObjPrefix</name>
|
||||
@ -3906,7 +3906,7 @@
|
||||
</option>
|
||||
<option>
|
||||
<name>CCDiagError</name>
|
||||
<state></state>
|
||||
<state>Pa050</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCObjPrefix</name>
|
||||
|
||||
@ -1,77 +1,77 @@
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc43xx.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \file
|
||||
* \brief TBD
|
||||
*
|
||||
* \note TBD
|
||||
*/
|
||||
|
||||
/** \ingroup TBD
|
||||
* \defgroup TBD
|
||||
* \brief TBD
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_HAL_LPC43XX_H_
|
||||
#define _TUSB_HAL_LPC43XX_H_
|
||||
|
||||
#include "LPC43xx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline void hal_interrupt_enable(uint8_t coreid)
|
||||
{
|
||||
NVIC_EnableIRQ(coreid ? USB1_IRQn : USB0_IRQn);
|
||||
}
|
||||
|
||||
static inline void hal_interrupt_disable(uint8_t coreid)
|
||||
{
|
||||
NVIC_DisableIRQ(coreid ? USB1_IRQn : USB0_IRQn);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HAL_LPC43XX_H_ */
|
||||
|
||||
/** @} */
|
||||
/**************************************************************************/
|
||||
/*!
|
||||
@file hal_lpc43xx.h
|
||||
@author hathach (tinyusb.org)
|
||||
|
||||
@section LICENSE
|
||||
|
||||
Software License Agreement (BSD License)
|
||||
|
||||
Copyright (c) 2013, hathach (tinyusb.org)
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
1. Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holders nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
||||
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is part of the tinyusb stack.
|
||||
*/
|
||||
/**************************************************************************/
|
||||
|
||||
/** \file
|
||||
* \brief TBD
|
||||
*
|
||||
* \note TBD
|
||||
*/
|
||||
|
||||
/** \ingroup TBD
|
||||
* \defgroup TBD
|
||||
* \brief TBD
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_HAL_LPC43XX_H_
|
||||
#define _TUSB_HAL_LPC43XX_H_
|
||||
|
||||
#include "LPC43xx.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline void hal_interrupt_enable(uint8_t coreid)
|
||||
{
|
||||
NVIC_EnableIRQ(coreid ? USB1_IRQn : USB0_IRQn);
|
||||
}
|
||||
|
||||
static inline void hal_interrupt_disable(uint8_t coreid)
|
||||
{
|
||||
NVIC_DisableIRQ(coreid ? USB1_IRQn : USB0_IRQn);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_HAL_LPC43XX_H_ */
|
||||
|
||||
/** @} */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user