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update/rename ghwcfg registers
This commit is contained in:
hathach
parent
47233f863a
commit
bb2d1dd0c1
@ -538,13 +538,10 @@ static void reset_core(dwc2_regs_t* dwc2) {
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static bool phy_hs_supported(dwc2_regs_t* dwc2) {
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(void) dwc2;
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#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
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// note: esp32 incorrect report its hs_phy_type as utmi
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return false;
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#elif !TUD_OPT_HIGH_SPEED
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#if !TUD_OPT_HIGH_SPEED
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return false;
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#else
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return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
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return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
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#endif
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}
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@ -555,7 +552,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
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dwc2->gusbcfg |= GUSBCFG_PHYSEL;
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// MCU specific PHY init before reset
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dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
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dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// Reset core after selecting PHY
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reset_core(dwc2);
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@ -566,7 +563,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// set max speed
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dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
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@ -578,7 +575,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// De-select FS PHY
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gusbcfg &= ~GUSBCFG_PHYSEL;
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if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
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TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
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// Select ULPI
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@ -599,7 +596,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
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// Set 16-bit interface if supported
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if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
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if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
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}
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// Apply config
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@ -615,7 +612,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// - 9 if using 8-bit PHY interface
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// - 5 if using 16-bit PHY interface
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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dwc2->gusbcfg = gusbcfg;
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// MCU specific PHY update post reset
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@ -628,7 +625,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
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// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
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if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
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dcfg |= DCFG_XCVRDLY;
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}
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@ -640,7 +637,7 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
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print_dwc2_info(dwc2);
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#endif
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// For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
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// For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
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(void) dwc2;
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#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
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uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
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@ -1,55 +1,58 @@
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| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F407 HS | STM32F412 FS | STM32F429 HS | STM32F723 FS | STM32F723 HS | STM32F767 FS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 |
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|:----------------------------|:----------------|:-------------|:--------------|:------------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------|
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| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
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| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
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| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
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| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
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| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
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| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
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| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
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| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
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| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
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| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
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| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
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| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
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| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
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| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
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| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
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| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
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| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
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| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
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| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
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| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
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| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
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| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
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| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
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| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
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| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 11 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
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| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
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| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
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| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 |
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|:---------------------------|:----------------|:-------------|:--------------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------|
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| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
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| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
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| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
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| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
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| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
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| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
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| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 |
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| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
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| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 |
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| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 |
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| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 |
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| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - nptx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
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| - ptx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
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| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
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| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
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| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
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| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
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| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
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| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |
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| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
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| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
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| - dfifo_depth | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 |
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| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
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| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - enhanced_lpm_support | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
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| - phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 |
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| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
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| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
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| - num_dev_in_eps | 7 | 6 | 4 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 |
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| - dma_desc_enable | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
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| - dma_desc_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
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@ -47,9 +47,9 @@ class GHWCFG2(ctypes.LittleEndianStructure):
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("enable_dynamic_fifo", ctypes.c_uint32, 1),
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("mul_cpu_int", ctypes.c_uint32, 1),
|
||||
("reserved21", ctypes.c_uint32, 1),
|
||||
("nperiod_tx_q_depth", ctypes.c_uint32, 2),
|
||||
("host_period_tx_q_depth", ctypes.c_uint32, 2),
|
||||
("dev_token_q_depth", ctypes.c_uint32, 5),
|
||||
("nptx_q_depth", ctypes.c_uint32, 2),
|
||||
("ptx_q_depth", ctypes.c_uint32, 2),
|
||||
("token_q_depth", ctypes.c_uint32, 5),
|
||||
("otg_enable_ic_usb", ctypes.c_uint32, 1)
|
||||
]
|
||||
|
||||
@ -67,31 +67,34 @@ class GHWCFG3(ctypes.LittleEndianStructure):
|
||||
("otg_enable_hsic", ctypes.c_uint32, 1),
|
||||
("battery_charger_support", ctypes.c_uint32, 1),
|
||||
("lpm_mode", ctypes.c_uint32, 1),
|
||||
("total_fifo_size", ctypes.c_uint32, 16)
|
||||
("dfifo_depth", ctypes.c_uint32, 16)
|
||||
]
|
||||
|
||||
|
||||
class GHWCFG4(ctypes.LittleEndianStructure):
|
||||
_fields_ = [
|
||||
("num_dev_period_in_ep", ctypes.c_uint32, 4),
|
||||
("power_optimized", ctypes.c_uint32, 1),
|
||||
("partial_powerdown", ctypes.c_uint32, 1),
|
||||
("ahb_freq_min", ctypes.c_uint32, 1),
|
||||
("hibernation", ctypes.c_uint32, 1),
|
||||
("reserved7", ctypes.c_uint32, 3),
|
||||
("service_interval_mode", ctypes.c_uint32, 1),
|
||||
("ipg_isoc_en", ctypes.c_uint32, 1),
|
||||
("acg_enable", ctypes.c_uint32, 1),
|
||||
("reserved13", ctypes.c_uint32, 1),
|
||||
("utmi_phy_data_width", ctypes.c_uint32, 2),
|
||||
("dev_ctrl_ep_num", ctypes.c_uint32, 4),
|
||||
("iddg_filter_enabled", ctypes.c_uint32, 1),
|
||||
("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("a_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("b_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("extended_hibernation", ctypes.c_uint32, 1),
|
||||
("reserved8", ctypes.c_uint32, 1),
|
||||
("enhanced_lpm_support1", ctypes.c_uint32, 1),
|
||||
("service_interval_flow", ctypes.c_uint32, 1),
|
||||
("ipg_isoc_support", ctypes.c_uint32, 1),
|
||||
("acg_support", ctypes.c_uint32, 1),
|
||||
("enhanced_lpm_support", ctypes.c_uint32, 1),
|
||||
("phy_data_width", ctypes.c_uint32, 2),
|
||||
("ctrl_ep_num", ctypes.c_uint32, 4),
|
||||
("iddg_filter", ctypes.c_uint32, 1),
|
||||
("vbus_valid_filter", ctypes.c_uint32, 1),
|
||||
("a_valid_filter", ctypes.c_uint32, 1),
|
||||
("b_valid_filter", ctypes.c_uint32, 1),
|
||||
("session_end_filter", ctypes.c_uint32, 1),
|
||||
("dedicated_fifos", ctypes.c_uint32, 1),
|
||||
("num_dev_in_eps", ctypes.c_uint32, 4),
|
||||
("dma_desc_enable", ctypes.c_uint32, 1),
|
||||
("dma_dynamic", ctypes.c_uint32, 1)
|
||||
("dma_desc_dynamic", ctypes.c_uint32, 1)
|
||||
]
|
||||
|
||||
|
||||
|
||||
@ -142,7 +142,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
|
||||
// - dwc2 3.30a (H5) use USB_HS_PHYC
|
||||
// - dwc2 4.11a (U5) use femtoPHY
|
||||
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
if (hs_phy_type == HS_PHY_TYPE_NONE) {
|
||||
if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
|
||||
// Enable on-chip FS PHY
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
|
||||
|
||||
@ -175,7 +175,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
#endif
|
||||
|
||||
// Enable on-chip HS PHY
|
||||
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
|
||||
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
|
||||
#ifdef USB_HS_PHYC
|
||||
// Enable UTMI HS PHY
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
|
||||
@ -218,7 +218,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
// MCU specific PHY update, it is called AFTER init() and core reset
|
||||
static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
// used to set turnaround time for fullspeed, nothing to do in highspeed mode
|
||||
if (hs_phy_type == HS_PHY_TYPE_NONE) {
|
||||
if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
|
||||
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
|
||||
uint32_t turnaround;
|
||||
|
||||
|
||||
@ -87,186 +87,220 @@ typedef struct
|
||||
#endif
|
||||
|
||||
enum {
|
||||
HS_PHY_TYPE_NONE = 0 , // not supported
|
||||
HS_PHY_TYPE_UTMI , // internal PHY (mostly)
|
||||
HS_PHY_TYPE_ULPI , // external PHY
|
||||
HS_PHY_TYPE_UTMI_ULPI ,
|
||||
GHWCFG2_OPMODE_HNP_SRP = 0,
|
||||
GHWCFG2_OPMODE_SRP = 1,
|
||||
GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
|
||||
GHWCFG2_OPMODE_SRP_DEVICE = 3,
|
||||
GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4,
|
||||
GHWCFG2_OPMODE_SRP_HOST = 5,
|
||||
GHWCFG2_OPMODE_NON_OTG_HOST = 6,
|
||||
};
|
||||
|
||||
enum {
|
||||
FS_PHY_TYPE_NONE = 0, // not supported
|
||||
FS_PHY_TYPE_DEDICATED,
|
||||
FS_PHY_TYPE_UTMI,
|
||||
FS_PHY_TYPE_ULPI,
|
||||
};
|
||||
|
||||
enum {
|
||||
GHWCFG2_ARCH_SLAVE_ONLY = 0,
|
||||
GHWCFG2_ARCH_EXTERNAL_DMA, // 1
|
||||
GHWCFG2_ARCH_INTERNAL_DMA, // 2
|
||||
GHWCFG2_ARCH_EXTERNAL_DMA = 1,
|
||||
GHWCFG2_ARCH_INTERNAL_DMA = 2,
|
||||
};
|
||||
|
||||
enum {
|
||||
GHWCFG2_HSPHY_NOT_SUPPORTED = 0,
|
||||
GHWCFG2_HSPHY_UTMI = 1, // internal PHY (mostly)
|
||||
GHWCFG2_HSPHY_ULPI = 2, // external PHY (mostly)
|
||||
GHWCFG2_HSPHY_UTMI_ULPI = 3, // both
|
||||
|
||||
};
|
||||
|
||||
enum {
|
||||
GHWCFG2_FSPHY_NOT_SUPPORTED = 0,
|
||||
GHWCFG2_FSPHY_DEDICATED = 1, // have dedicated FS PHY
|
||||
GHWCFG2_FSPHY_UTMI = 2, // shared with UTMI+
|
||||
GHWCFG2_FSPHY_ULPI = 3, // shared with ULPI
|
||||
};
|
||||
|
||||
enum {
|
||||
GHWCFFG4_PHY_DATA_WIDTH_8 = 0,
|
||||
GHWCFFG4_PHY_DATA_WIDTH_16 = 1,
|
||||
GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
// Register bitfield definitions
|
||||
//--------------------------------------------------------------------
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
|
||||
uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
|
||||
uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
|
||||
uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
|
||||
uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
|
||||
uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
|
||||
uint32_t num_host_ch : 4; // Number of host channel
|
||||
uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
|
||||
uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
|
||||
uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
|
||||
uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
|
||||
uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
|
||||
uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
|
||||
} dwc2_ghwcfg2_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
|
||||
uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
|
||||
uint32_t otg_enable : 1; // 1 is OTG capable
|
||||
uint32_t i2c_enable : 1; // I2C interface is available
|
||||
uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
|
||||
uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
|
||||
uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
|
||||
uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
|
||||
uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
|
||||
uint32_t battery_charger_support : 1; // support battery charger
|
||||
uint32_t lpm_mode : 1; // LPC mode
|
||||
uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
|
||||
}dwc2_ghwcfg3_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
|
||||
uint32_t power_optimized : 1; // Partial Power Down Enabled
|
||||
uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
|
||||
uint32_t hibernation : 1; // Hibernation feature is enabled
|
||||
uint32_t reserved7 : 3;
|
||||
uint32_t service_interval_mode : 1; // Service Interval supported
|
||||
uint32_t ipg_isoc_en : 1; // IPG ISOC supported
|
||||
uint32_t acg_enable : 1; // ACG enabled
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
|
||||
uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
|
||||
uint32_t iddg_filter_enabled : 1;
|
||||
uint32_t vbus_valid_filter_enabled : 1;
|
||||
uint32_t a_valid_filter_enabled : 1;
|
||||
uint32_t b_valid_filter_enabled : 1;
|
||||
uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
|
||||
uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
|
||||
uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
|
||||
uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
|
||||
}dwc2_ghwcfg4_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t ses_req_scs : 1; // 0: Session request success
|
||||
uint32_t ses_req : 1; // 1: Session request
|
||||
uint32_t vbval_ov_en : 1; // 2: VBUS valid override enable
|
||||
uint32_t vbval_ov_val : 1; // 3: VBUS valid override value
|
||||
uint32_t aval_ov_en : 1; // 4: A-peripheral session valid override enable
|
||||
uint32_t aval_ov_al : 1; // 5: A-peripheral session valid override value
|
||||
uint32_t bval_ov_en : 1; // 6: B-peripheral session valid override enable
|
||||
uint32_t bval_ov_val : 1; // 7: B-peripheral session valid override value
|
||||
uint32_t hng_scs : 1; // 8: Host negotiation success
|
||||
uint32_t hnp_rq : 1; // 9: HNP (host negotiation protocol) request
|
||||
uint32_t host_set_hnp_en : 1; // 10: Host set HNP enable
|
||||
uint32_t dev_hnp_en : 1; // 11: Device HNP enabled
|
||||
uint32_t embedded_host_en : 1; // 12: Embedded host enable
|
||||
uint32_t rsv13_14 : 2; // 13..14: Reserved
|
||||
uint32_t dbnc_filter_bypass : 1; // 15: Debounce filter bypass
|
||||
uint32_t cid_status : 1; // 16: Connector ID status
|
||||
uint32_t dbnc_done : 1; // 17: Debounce done
|
||||
uint32_t ases_valid : 1; // 18: A-session valid
|
||||
uint32_t bses_valid : 1; // 19: B-session valid
|
||||
uint32_t otg_ver : 1; // 20: OTG version 0: v1.3, 1: v2.0
|
||||
uint32_t current_mode : 1; // 21: Current mode of operation 0: device, 1: host
|
||||
uint32_t mult_val_id_bc : 5; // 22..26: Multi-valued input pin ID battery charger
|
||||
uint32_t chirp_en : 1; // 27: Chirp detection enable
|
||||
uint32_t rsv28_30 : 3; // 28..30: Reserved
|
||||
uint32_t test_mode_corr_eusb2 : 1; // 31: Test mode control for eUSB2 PHY
|
||||
uint32_t ses_req_scs : 1; // 0 Session request success
|
||||
uint32_t ses_req : 1; // 1 Session request
|
||||
uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable
|
||||
uint32_t vbval_ov_val : 1; // 3 VBUS valid override value
|
||||
uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable
|
||||
uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value
|
||||
uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable
|
||||
uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value
|
||||
uint32_t hng_scs : 1; // 8 Host negotiation success
|
||||
uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request
|
||||
uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable
|
||||
uint32_t dev_hnp_en : 1; // 11 Device HNP enabled
|
||||
uint32_t embedded_host_en : 1; // 12 Embedded host enable
|
||||
uint32_t rsv13_14 : 2; // 13.14 Reserved
|
||||
uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass
|
||||
uint32_t cid_status : 1; // 16 Connector ID status
|
||||
uint32_t dbnc_done : 1; // 17 Debounce done
|
||||
uint32_t ases_valid : 1; // 18 A-session valid
|
||||
uint32_t bses_valid : 1; // 19 B-session valid
|
||||
uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0
|
||||
uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host
|
||||
uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger
|
||||
uint32_t chirp_en : 1; // 27 Chirp detection enable
|
||||
uint32_t rsv28_30 : 3; // 28.30: Reserved
|
||||
uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY
|
||||
} dwc2_gotgctl_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t rsv0_1 : 2; // 0..1 : Reserved
|
||||
uint32_t ses_end_det : 1; // 2 : Session end detected
|
||||
uint32_t rsv3_7 : 5; // 3..7 : Reserved
|
||||
uint32_t srs_status_change : 1; // 8 : Session request success status change
|
||||
uint32_t hns_status_change : 1; // 9 : Host negotiation success status change
|
||||
uint32_t rsv10_16 : 7; // 10..16 : Reserved
|
||||
uint32_t hng_det : 1; // 17 : Host negotiation detected
|
||||
uint32_t adev_timeout_change : 1; // 18 : A-device timeout change
|
||||
uint32_t dbnc_done : 1; // 19 : Debounce done
|
||||
uint32_t mult_val_lp_change : 1; // 20 : Multi-valued input pin change
|
||||
uint32_t rsv21_31 :11; // 21..31 : Reserved
|
||||
uint32_t rsv0_1 : 2; // 0..1 Reserved
|
||||
uint32_t ses_end_det : 1; // 2 Session end detected
|
||||
uint32_t rsv3_7 : 5; // 3..7 Reserved
|
||||
uint32_t srs_status_change : 1; // 8 Session request success status change
|
||||
uint32_t hns_status_change : 1; // 9 Host negotiation success status change
|
||||
uint32_t rsv10_16 : 7; // 10..16 Reserved
|
||||
uint32_t hng_det : 1; // 17 Host negotiation detected
|
||||
uint32_t adev_timeout_change : 1; // 18 A-device timeout change
|
||||
uint32_t dbnc_done : 1; // 19 Debounce done
|
||||
uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change
|
||||
uint32_t rsv21_31 :11; // 21..31 Reserved
|
||||
} dwc2_gotgint_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t gintmask : 1; // 0: Global interrupt mask
|
||||
uint32_t hbst_len : 4; // 1..4: Burst length/type
|
||||
uint32_t dma_en : 1; // 5: DMA enable
|
||||
uint32_t rsv6 : 1; // 6: Reserved
|
||||
uint32_t nptxf_empty_lvl : 1; // 7: Non-periodic Tx FIFO empty level
|
||||
uint32_t ptxf_empty_lvl : 1; // 8: Periodic Tx FIFO empty level
|
||||
uint32_t rsv9_20 : 12; // 9..20: Reserved
|
||||
uint32_t remote_mem_support : 1; // 21: Remote memory support
|
||||
uint32_t notify_all_dma_write : 1; // 22: Notify all DMA writes
|
||||
uint32_t ahb_single : 1; // 23: AHB single
|
||||
uint32_t inv_desc_endian : 1; // 24: Inverse descriptor endian
|
||||
uint32_t rsv25_31 : 7; // 25..31: Reserved
|
||||
uint32_t gintmask : 1; // 0 Global interrupt mask
|
||||
uint32_t hbst_len : 4; // 1..4 Burst length/type
|
||||
uint32_t dma_en : 1; // 5 DMA enable
|
||||
uint32_t rsv6 : 1; // 6 Reserved
|
||||
uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level
|
||||
uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level
|
||||
uint32_t rsv9_20 : 12; // 9.20: Reserved
|
||||
uint32_t remote_mem_support : 1; // 21 Remote memory support
|
||||
uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes
|
||||
uint32_t ahb_single : 1; // 23 AHB single
|
||||
uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian
|
||||
uint32_t rsv25_31 : 7; // 25..31 Reserved
|
||||
} dwc2_gahbcfg_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t timeout_cal : 3; /* 0..2: Timeout calibration.
|
||||
uint32_t timeout_cal : 3; /* 0..2 Timeout calibration.
|
||||
The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
|
||||
timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field
|
||||
based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
|
||||
- High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times
|
||||
- Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */
|
||||
uint32_t phy_if : 1; // 3: PHY interface. 0: 8 bits, 1: 16 bits
|
||||
uint32_t ulpi_utmi_sel : 1; // 4: ULPI/UTMI select. 0: UTMI+, 1: ULPI
|
||||
uint32_t fs_intf_sel : 1; // 5: Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
|
||||
uint32_t phy_sel : 1; // 6: HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
|
||||
uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits
|
||||
uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI
|
||||
uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
|
||||
uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
|
||||
uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit
|
||||
uint32_t srp_capable : 1; // 8: SRP-capable
|
||||
uint32_t hnp_capable : 1; // 9: HNP-capable
|
||||
uint32_t srp_capable : 1; // 8 SRP-capable
|
||||
uint32_t hnp_capable : 1; // 9 HNP-capable
|
||||
uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+
|
||||
uint32_t rsv14 : 1; // 14: Reserved
|
||||
uint32_t phy_low_power_clk_sel : 1; /* 15: PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
|
||||
uint32_t rsv14 : 1; // 14 Reserved
|
||||
uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
|
||||
In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs.
|
||||
- 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit)
|
||||
- 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */
|
||||
uint32_t otg_i2c_sel : 1; // 16: OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
|
||||
uint32_t ulpi_fsls : 1; /* 17: ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
|
||||
uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
|
||||
uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
|
||||
valid only when the FS serial transceiver is selected on the ULPI PHY. */
|
||||
uint32_t ulpi_auto_resume : 1; // 18: ULPI Auto-resume
|
||||
uint32_t ulpi_clk_sus_m : 1; // 19: ULPI Clock SuspendM
|
||||
uint32_t ulpi_ext_vbus_drv : 1; // 20: ULPI External VBUS Drive
|
||||
uint32_t ulpi_int_vbus_indicator : 1; // 21: ULPI Internal VBUS Indicator
|
||||
uint32_t term_sel_dl_pulse : 1; // 22: TermSel DLine pulsing
|
||||
uint32_t indicator_complement : 1; // 23: Indicator complement
|
||||
uint32_t indicator_pass_through : 1; // 24: Indicator pass through
|
||||
uint32_t ulpi_if_protect_disable : 1; // 25: ULPI interface protect disable
|
||||
uint32_t ic_usb_capable : 1; // 26: IC_USB Capable
|
||||
uint32_t ic_usb_traf_ctl : 1; // 27: IC_USB Traffic Control
|
||||
uint32_t tx_end_delay : 1; // 28: TX end delay
|
||||
uint32_t force_host_mode : 1; // 29: Force host mode
|
||||
uint32_t force_dev_mode : 1; // 30: Force device mode
|
||||
uint32_t corrupt_tx_pkt : 1; // 31: Corrupt Tx packet. 0: normal, 1: debug
|
||||
uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume
|
||||
uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM
|
||||
uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive
|
||||
uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator
|
||||
uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing
|
||||
uint32_t indicator_complement : 1; // 23 Indicator complement
|
||||
uint32_t indicator_pass_through : 1; // 24 Indicator pass through
|
||||
uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable
|
||||
uint32_t ic_usb_capable : 1; // 26 IC_USB Capable
|
||||
uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control
|
||||
uint32_t tx_end_delay : 1; // 28 TX end delay
|
||||
uint32_t force_host_mode : 1; // 29 Force host mode
|
||||
uint32_t force_dev_mode : 1; // 30 Force device mode
|
||||
uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug
|
||||
} dwc2_gusbcfg_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t core_soft_rst : 1; // 0 Core Soft Reset
|
||||
uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset
|
||||
uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host)
|
||||
uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush
|
||||
uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush
|
||||
uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush
|
||||
uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number
|
||||
uint32_t rsv11_28 :18; // 11..28 Reserved
|
||||
uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a
|
||||
uint32_t dma_req : 1; // 30 DMA Request
|
||||
uint32_t ahb_idle : 1; // 31 AHB Idle
|
||||
} dwc2_grstctl_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode
|
||||
uint32_t arch : 2; // 3..4 Slave/External/Internal DMA
|
||||
uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split
|
||||
uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
|
||||
uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
|
||||
uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0)
|
||||
uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control)
|
||||
uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel
|
||||
uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled
|
||||
uint32_t mul_cpu_int : 1; // 20 Multi-Processor Interrupt Enabled
|
||||
uint32_t reserved21 : 1; // 21 reserved
|
||||
uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
|
||||
uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
|
||||
uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30
|
||||
uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation
|
||||
} dwc2_ghwcfg2_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits)
|
||||
uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits)
|
||||
uint32_t otg_enable : 1; // 7 OTG capable
|
||||
uint32_t i2c_enable : 1; // 8 I2C interface is available
|
||||
uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available
|
||||
uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count
|
||||
uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset
|
||||
uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller
|
||||
uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
|
||||
uint32_t battery_charger_support : 1; // s14 upport battery charger
|
||||
uint32_t lpm_mode : 1; // 15 LPM mode
|
||||
uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
|
||||
}dwc2_ghwcfg3_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
|
||||
|
||||
typedef struct TU_ATTR_PACKED {
|
||||
uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints
|
||||
uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled
|
||||
uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz
|
||||
uint32_t hibernation : 1; // 6 Hibernation feature is enabled
|
||||
uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled
|
||||
uint32_t reserved8 : 1; // 8 Reserved
|
||||
uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1
|
||||
uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported
|
||||
uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported
|
||||
uint32_t acg_support : 1; // 12 Active clock gating is supported
|
||||
uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support
|
||||
uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
|
||||
uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0
|
||||
uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled
|
||||
uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled
|
||||
uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled
|
||||
uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled
|
||||
uint32_t session_end_filter : 1; // 24 Session End Filter Enabled
|
||||
uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint
|
||||
uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0
|
||||
uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled
|
||||
uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA
|
||||
}dwc2_ghwcfg4_t;
|
||||
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
|
||||
|
||||
// Host Channel
|
||||
typedef struct {
|
||||
volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
|
||||
@ -317,32 +351,32 @@ typedef struct {
|
||||
volatile uint32_t grxstsr; // 01c Receive Status Debug Read
|
||||
volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
|
||||
volatile uint32_t grxfsiz; // 024 Receive FIFO Size
|
||||
union {
|
||||
union {
|
||||
volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
|
||||
volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
|
||||
};
|
||||
};
|
||||
volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
|
||||
volatile uint32_t gi2cctl; // 030 I2C Address
|
||||
volatile uint32_t gpvndctl; // 034 PHY Vendor Control
|
||||
union {
|
||||
union {
|
||||
volatile uint32_t ggpio; // 038 General Purpose IO
|
||||
volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
|
||||
};
|
||||
};
|
||||
volatile uint32_t guid; // 03C User (Application programmable) ID
|
||||
volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
|
||||
volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
|
||||
union {
|
||||
union {
|
||||
volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
|
||||
volatile dwc2_ghwcfg2_t ghwcfg2_bm;
|
||||
};
|
||||
union {
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
|
||||
volatile dwc2_ghwcfg3_t ghwcfg3_bm;
|
||||
};
|
||||
union {
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
|
||||
volatile dwc2_ghwcfg4_t ghwcfg4_bm;
|
||||
};
|
||||
};
|
||||
volatile uint32_t glpmcfg; // 054 Core LPM Configuration
|
||||
volatile uint32_t gpwrdn; // 058 Power Down
|
||||
volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
|
||||
@ -352,7 +386,7 @@ union {
|
||||
volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
|
||||
uint32_t reserved140[176]; // 140..3FF
|
||||
|
||||
//------------- Host -------------//
|
||||
//------------ Host -------------//
|
||||
volatile uint32_t hcfg; // 400 Host Configuration
|
||||
volatile uint32_t hfir; // 404 Host Frame Interval
|
||||
volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
|
||||
@ -369,7 +403,7 @@ union {
|
||||
dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
|
||||
uint32_t reserved700[64]; // 700..7FF
|
||||
|
||||
//------------- Device -------------//
|
||||
//------------- Device -----------//
|
||||
volatile uint32_t dcfg; // 800 Device Configuration
|
||||
volatile uint32_t dctl; // 804 Device Control
|
||||
volatile uint32_t dsts; // 808 Device Status (RO)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user