mirror of
https://github.com/hathach/tinyusb.git
synced 2025-04-15 20:42:23 +00:00
update to dcd ip3511 to add work-around for lpc54628 usb hs errata USB.1 and USB.2
msc is mounted, but device couldn't work reliably and got constant reset due to other errata probably.
This commit is contained in:
hathach
parent
6d877c3170
commit
b8b01c1075
4
.idea/cmake.xml
generated
4
.idea/cmake.xml
generated
@ -30,7 +30,8 @@
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<configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
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<configuration PROFILE_NAME="lpc54628" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="lpc55s69" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
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<configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
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@ -51,6 +52,7 @@
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<configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
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<configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
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<configuration PROFILE_NAME="lpc54628 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT -DPORT=0" />
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</configurations>
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</component>
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</project>
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@ -70,13 +70,11 @@
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void USB0_IRQHandler(void)
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{
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void USB0_IRQHandler(void) {
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tud_int_handler(0);
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}
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void USB1_IRQHandler(void)
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{
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void USB1_IRQHandler(void) {
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tud_int_handler(1);
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}
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@ -59,6 +59,7 @@ function(add_board_target BOARD_TARGET)
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BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
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BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
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CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
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#CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
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)
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endif ()
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@ -159,11 +159,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) {
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
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//------------- Align -------------//
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
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{
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) {
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return value & ((uint32_t) ~(alignment-1));
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}
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4 (uint32_t value) { return (value & 0xFFFFFFFCUL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8 (uint32_t value) { return (value & 0xFFFFFFF8UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
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TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
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@ -58,6 +58,7 @@
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// NXP
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//--------------------------------------------------------------------+
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#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 5
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#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
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@ -66,14 +67,17 @@
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#define TUP_OHCI_RHPORTS 2
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#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 5
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#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
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#elif TU_CHECK_MCU(OPT_MCU_LPC54)
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// TODO USB0 has 5, USB1 has 6
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 6
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#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
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#elif TU_CHECK_MCU(OPT_MCU_LPC55)
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// TODO USB0 has 5, USB1 has 6
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#define TUP_USBIP_IP3511
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#define TUP_DCD_ENDPOINT_MAX 6
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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@ -34,18 +34,13 @@
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* - LPC54114
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* - LPC55s69
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*/
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#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
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CFG_TUSB_MCU == OPT_MCU_LPC13XX || \
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CFG_TUSB_MCU == OPT_MCU_LPC15XX || \
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CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
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CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
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CFG_TUSB_MCU == OPT_MCU_LPC55XX)
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#if CFG_TUD_ENABLED && defined(TUP_USBIP_IP3511)
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
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#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
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// LPCOpen
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#include "chip.h"
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#else
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@ -80,7 +75,7 @@ typedef struct {
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enum {
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NBYTES_ISO_FS_MAX = 1023, // FS ISO
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NBYTES_ISO_HS_MAX = 1024, // HS ISO
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NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
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NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt. TODO some FS can do burst with higher size e.g 1024. Need to test
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NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
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};
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@ -90,26 +85,36 @@ enum {
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};
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enum {
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CMDSTAT_DEVICE_ADDR_MASK = TU_BIT(7 )-1,
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CMDSTAT_DEVICE_ENABLE_MASK = TU_BIT(7 ),
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CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
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CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
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CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
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// 23-22 is link speed (only available for HighSpeed port)
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CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
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CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
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CMDSTAT_RESET_CHANGE_MASK = TU_BIT(26),
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CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
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DEVCMDSTAT_DEVICE_ADDR_MASK = TU_BIT(7 )-1,
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DEVCMDSTAT_DEVICE_ENABLE_MASK = TU_BIT(7 ),
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DEVCMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
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DEVCMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
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DEVCMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
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// 23-22 is link speed (only available for HighSpeed port)
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DEVCMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
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DEVCMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
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DEVCMDSTAT_RESET_CHANGE_MASK = TU_BIT(26),
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DEVCMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
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};
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enum {
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CMDSTAT_SPEED_SHIFT = 22
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DEVCMDSTAT_SPEED_SHIFT = 22
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};
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//--------------------------------------------------------------------+
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// Endpoint Command/Status List
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//--------------------------------------------------------------------+
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// EP Command/Status field definition
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enum {
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EPCS_TYPE = TU_BIT(26),
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EPCS_RF_TV = TU_BIT(27),
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EPCS_TOGGLE_RESET = TU_BIT(28),
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EPCS_STALL = TU_BIT(29),
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EPCS_DISABLED = TU_BIT(30),
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EPCS_ACTIVE = TU_BIT(31),
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};
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// Endpoint Command/Status
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typedef union TU_ATTR_PACKED
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{
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@ -133,8 +138,8 @@ typedef union TU_ATTR_PACKED
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volatile struct {
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uint32_t TU_RESERVED : 26;
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uint32_t is_iso : 1 ;
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uint32_t toggle_mode : 1 ;
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uint32_t type : 1 ;
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uint32_t rf_tv : 1 ; // rate feedback or toggle value
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uint32_t toggle_reset : 1 ;
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uint32_t stall : 1 ;
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uint32_t disable : 1 ;
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@ -180,6 +185,7 @@ typedef struct
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CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
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// Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
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// TODO find way to save memory
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CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
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//--------------------------------------------------------------------+
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@ -188,59 +194,73 @@ CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const tusb_speed_t max_speed; // max link speed
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_pairs; // Max bi-directional Endpoints
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dcd_registers_t* regs; // registers
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const bool is_highspeed; // max link speed
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_pairs; // Max bi-directional Endpoints
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}dcd_controller_t;
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#ifdef INCLUDE_FSL_DEVICE_REGISTERS
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) USB0_BASE , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM },
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static const dcd_controller_t _dcd_controller[] = {
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{ .regs = (dcd_registers_t*) USB0_BASE , .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM },
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#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
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{ .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
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{ .regs = (dcd_registers_t*) USBHSD_BASE, .is_highspeed = true, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
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#endif
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};
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#else
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static const dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
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static const dcd_controller_t _dcd_controller[] = {
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = 5 },
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};
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#endif
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#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
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#define IP3511_HAS_HIGHSPEED
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#endif
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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static inline uint16_t get_buf_offset(void const * buffer)
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{
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TU_ATTR_ALWAYS_INLINE static inline uint16_t get_buf_offset(void const * buffer) {
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uint32_t addr = (uint32_t) buffer;
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TU_ASSERT( (addr & 0x3f) == 0, 0 );
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return ( (addr >> 6) & 0xFFFFUL ) ;
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}
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static inline uint8_t ep_addr2id(uint8_t ep_addr)
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{
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TU_ATTR_ALWAYS_INLINE static inline uint8_t ep_addr2id(uint8_t ep_addr) {
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return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
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}
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TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_highspeed) {
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return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type;
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}
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TU_ATTR_ALWAYS_INLINE static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
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return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0);
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}
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TU_ATTR_ALWAYS_INLINE static inline ep_cmd_sts_t* get_ep_cs(uint8_t ep_id) {
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return _dcd.ep[ep_id];
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}
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TU_ATTR_ALWAYS_INLINE static inline bool rhport_is_highspeed(uint8_t rhport) {
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return _dcd_controller[rhport].is_highspeed;
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}
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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static void prepare_setup_packet(uint8_t rhport)
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{
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if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
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{
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_dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);
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}else
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{
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_dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);
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static void prepare_setup_packet(uint8_t rhport) {
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uint16_t const buf_offset = get_buf_offset(_dcd.setup_packet);
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if ( _dcd_controller[rhport].is_highspeed ) {
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_dcd.ep[0][1].buffer_hs.offset = buf_offset;
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} else {
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_dcd.ep[0][1].buffer_fs.offset = buf_offset;
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}
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}
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@ -268,8 +288,8 @@ void dcd_init(uint8_t rhport)
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dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment
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dcd_reg->INTSTAT |= dcd_reg->INTSTAT; // clear all pending interrupt
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dcd_reg->INTEN = INT_DEVICE_STATUS_MASK;
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dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
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CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
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dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK |
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DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
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NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
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}
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@ -291,7 +311,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
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dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_ADDR_MASK;
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dcd_reg->DEVCMDSTAT |= dev_addr;
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}
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@ -303,13 +323,13 @@ void dcd_remote_wakeup(uint8_t rhport)
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void dcd_connect(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
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dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_CONNECT_MASK;
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}
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void dcd_disconnect(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
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dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_CONNECT_MASK;
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}
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void dcd_sof_enable(uint8_t rhport, bool en)
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@ -340,19 +360,39 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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_dcd.ep[ep_id][0].cmd_sts.stall = 0;
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_dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
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_dcd.ep[ep_id][0].cmd_sts.toggle_mode = 0;
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_dcd.ep[ep_id][0].cmd_sts.rf_tv = 0;
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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//------------- Prepare Queue Head -------------//
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uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
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ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
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// Check if endpoint is available
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TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable );
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||||
TU_ASSERT( ep_cs[0].cmd_sts.disable && ep_cs[1].cmd_sts.disable );
|
||||
|
||||
edpt_reset(rhport, ep_id);
|
||||
_dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
|
||||
|
||||
switch (p_endpoint_desc->bmAttributes.xfer) {
|
||||
case TUSB_XFER_ISOCHRONOUS:
|
||||
ep_cs[0].cmd_sts.type = 1;
|
||||
break;
|
||||
|
||||
case TUSB_XFER_INTERRUPT:
|
||||
// What is interrupt endpoint in rate feedback mode ?
|
||||
if ( rhport_is_highspeed(rhport) ) {
|
||||
ep_cs[0].cmd_sts.type = 1;
|
||||
ep_cs[0].cmd_sts.rf_tv = 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case TUSB_XFER_BULK:
|
||||
// nothing to do both type and rf_tv are 0
|
||||
break;
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
// Enable EP interrupt
|
||||
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
|
||||
@ -379,42 +419,50 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
_dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
|
||||
}
|
||||
|
||||
static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
|
||||
{
|
||||
static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) {
|
||||
uint16_t nbytes;
|
||||
ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
|
||||
|
||||
if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
|
||||
{
|
||||
nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
|
||||
_dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
|
||||
_dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
|
||||
}else
|
||||
{
|
||||
nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX);
|
||||
_dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
|
||||
_dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
|
||||
const bool is_iso = ep_is_iso(ep_cs, _dcd_controller[rhport].is_highspeed);
|
||||
|
||||
if ( rhport_is_highspeed(rhport) ) {
|
||||
nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_HS_MAX : NBYTES_CBI_HS_MAX);
|
||||
#if TU_CHECK_MCU(OPT_MCU_LPC54)
|
||||
// LPC54 Errata USB.1: In USB high-speed device mode, the NBytes field does not decrement after BULK OUT transfer.
|
||||
// Suggested Work-around: Program the NByte to the max packet size (512)
|
||||
// Actual Work-around: round up NByte to multiple of 4.
|
||||
// Note: this can cause buffer overflowed and corrupt data if host send more data than total_bytes
|
||||
if ( (ep_id > 1) && (ep_id & 0x01) == 0 && ep_is_bulk(ep_cs) ) {
|
||||
if ( nbytes & 0x03 ) {
|
||||
nbytes = tu_align4(nbytes) + 4;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
ep_cs[0].buffer_hs.offset = buf_offset;
|
||||
ep_cs[0].buffer_hs.nbytes = nbytes;
|
||||
}else {
|
||||
nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
|
||||
ep_cs[0].buffer_fs.offset = buf_offset;
|
||||
ep_cs[0].buffer_fs.nbytes = nbytes;
|
||||
}
|
||||
|
||||
_dcd.dma[ep_id].nbytes = nbytes;
|
||||
|
||||
_dcd.ep[ep_id][0].cmd_sts.active = 1;
|
||||
ep_cs[0].cmd_sts.active = 1;
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||
{
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
|
||||
uint8_t const ep_id = ep_addr2id(ep_addr);
|
||||
|
||||
if (!buffer || total_bytes == 0) {
|
||||
// Although having no data, ZLPs can cause buffer overwritten to zeroes. Probably due to USB/DMA controller side
|
||||
// effect/bug. Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
|
||||
buffer = (uint8_t *) (uint32_t) dummy;
|
||||
}
|
||||
|
||||
tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
|
||||
_dcd.dma[ep_id].total_bytes = total_bytes;
|
||||
|
||||
if (!buffer)
|
||||
{
|
||||
// Although having no data, ZLPs can cause buffer overwritten to zeroes.
|
||||
// Probably due to USB/DMA controller side effect/bug.
|
||||
// Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
|
||||
buffer = (uint8_t*)(uint32_t)dummy;
|
||||
}
|
||||
|
||||
prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
|
||||
|
||||
return true;
|
||||
@ -441,23 +489,19 @@ static void bus_reset(uint8_t rhport)
|
||||
dcd_reg->EPSKIP = 0xFFFFFFFF;
|
||||
|
||||
dcd_reg->INTSTAT = dcd_reg->INTSTAT; // clear all pending interrupt
|
||||
dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
|
||||
dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
|
||||
dcd_reg->INTEN = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
|
||||
}
|
||||
|
||||
static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
|
||||
{
|
||||
static void process_xfer_isr(uint8_t rhport, uint32_t int_status) {
|
||||
uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
|
||||
|
||||
for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
|
||||
{
|
||||
if ( tu_bit_test(int_status, ep_id) )
|
||||
{
|
||||
for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) {
|
||||
if ( tu_bit_test(int_status, ep_id) ) {
|
||||
ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
|
||||
xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
|
||||
|
||||
if ( ep_id == 0 || ep_id == 1)
|
||||
{
|
||||
if ( ep_id <= 1 ) {
|
||||
// For control endpoint, we need to manually clear Active bit
|
||||
ep_cs->cmd_sts.active = 0;
|
||||
}
|
||||
@ -465,26 +509,29 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
|
||||
uint16_t buf_offset;
|
||||
uint16_t buf_nbytes;
|
||||
|
||||
if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL)
|
||||
{
|
||||
buf_offset = ep_cs->buffer_fs.offset;
|
||||
buf_nbytes = ep_cs->buffer_fs.nbytes;
|
||||
}else
|
||||
{
|
||||
if ( rhport_is_highspeed(rhport) ) {
|
||||
buf_offset = ep_cs->buffer_hs.offset;
|
||||
buf_nbytes = ep_cs->buffer_hs.nbytes;
|
||||
|
||||
#if TU_CHECK_MCU(OPT_MCU_LPC54)
|
||||
// LPC54 Errata USB.2: In USB high-speed device mode, the NBytes field is not correct after BULK IN transfer
|
||||
// There is no work-around. For EP in transfer, the NByte value can be ignored after a packet is transmitted.
|
||||
if ( (ep_id > 1) && (ep_id & 0x01) == 1 && ep_is_bulk(ep_cs) ) {
|
||||
buf_nbytes = 0;
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
buf_offset = ep_cs->buffer_fs.offset;
|
||||
buf_nbytes = ep_cs->buffer_fs.nbytes;
|
||||
}
|
||||
|
||||
xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes;
|
||||
|
||||
if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
|
||||
{
|
||||
if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) {
|
||||
// There is more data to transfer
|
||||
// buff_offset has been already increased by hw to correct value for next transfer
|
||||
prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// for detecting ZLP
|
||||
xfer_dma->total_bytes = xfer_dma->xferred_bytes;
|
||||
|
||||
@ -511,19 +558,16 @@ void dcd_int_handler(uint8_t rhport)
|
||||
//------------- Device Status -------------//
|
||||
if ( int_status & INT_DEVICE_STATUS_MASK )
|
||||
{
|
||||
dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
|
||||
dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
|
||||
|
||||
if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
|
||||
if ( cmd_stat & DEVCMDSTAT_RESET_CHANGE_MASK) // bus reset
|
||||
{
|
||||
bus_reset(rhport);
|
||||
|
||||
tusb_speed_t speed = TUSB_SPEED_FULL;
|
||||
|
||||
if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
|
||||
{
|
||||
if ( _dcd_controller[rhport].is_highspeed ) {
|
||||
// 0 : reserved, 1 : full, 2 : high, 3: super
|
||||
if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
|
||||
{
|
||||
if ( 2 == ((cmd_stat >> DEVCMDSTAT_SPEED_SHIFT) & 0x3UL) ) {
|
||||
speed= TUSB_SPEED_HIGH;
|
||||
}
|
||||
}
|
||||
@ -531,35 +575,35 @@ void dcd_int_handler(uint8_t rhport)
|
||||
dcd_event_bus_reset(rhport, speed, true);
|
||||
}
|
||||
|
||||
if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
|
||||
if (cmd_stat & DEVCMDSTAT_CONNECT_CHANGE_MASK)
|
||||
{
|
||||
// device disconnect
|
||||
if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
|
||||
if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
|
||||
{
|
||||
// debouncing as this can be set when device is powering
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
}
|
||||
}
|
||||
|
||||
if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
|
||||
if (cmd_stat & DEVCMDSTAT_SUSPEND_CHANGE_MASK)
|
||||
{
|
||||
// suspend signal, bus idle for more than 3ms
|
||||
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
||||
if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
|
||||
if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
|
||||
{
|
||||
dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
|
||||
dcd_event_bus_signal(rhport, (cmd_stat & DEVCMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Setup Receive
|
||||
if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
|
||||
if ( tu_bit_test(int_status, 0) && (cmd_stat & DEVCMDSTAT_SETUP_RECEIVED_MASK) )
|
||||
{
|
||||
// Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
|
||||
_dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
|
||||
_dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
|
||||
|
||||
dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
|
||||
dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK;
|
||||
|
||||
dcd_event_setup_received(rhport, _dcd.setup_packet, true);
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user