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more log for debugging

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hathach 2020-02-07 16:43:44 +07:00
parent 7b20b80dc0
commit b6b9fe42af
2 changed files with 21 additions and 4 deletions
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11
src/class/cdc/cdc_device.c
View File

@ -335,25 +335,34 @@ bool cdcd_control_request(uint8_t rhport, tusb_control_request_t const * request
switch ( request->bRequest ) switch ( request->bRequest )
{ {
case CDC_REQUEST_SET_LINE_CODING: case CDC_REQUEST_SET_LINE_CODING:
TU_LOG2(" Set Line Coding\n");
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
break; break;
case CDC_REQUEST_GET_LINE_CODING: case CDC_REQUEST_GET_LINE_CODING:
TU_LOG2(" Get Line Coding\n");
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
break; break;
case CDC_REQUEST_SET_CONTROL_LINE_STATE: case CDC_REQUEST_SET_CONTROL_LINE_STATE:
{
// CDC PSTN v1.2 section 6.3.12 // CDC PSTN v1.2 section 6.3.12
// Bit 0: Indicates if DTE is present or not. // Bit 0: Indicates if DTE is present or not.
// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready) // This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
// Bit 1: Carrier control for half-duplex modems. // Bit 1: Carrier control for half-duplex modems.
// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send) // This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
bool const dtr = tu_bit_test(request->wValue, 0);
bool const rts = tu_bit_test(request->wValue, 1);
p_cdc->line_state = (uint8_t) request->wValue; p_cdc->line_state = (uint8_t) request->wValue;
TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\n", dtr, rts);
tud_control_status(rhport, request); tud_control_status(rhport, request);
// Invoke callback // Invoke callback
if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, tu_bit_test(request->wValue, 0), tu_bit_test(request->wValue, 1)); if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, dtr, rts);
}
break; break;
default: return false; // stall unsupported request default: return false; // stall unsupported request

14
src/device/usbd_control.c
View File

@ -51,8 +51,8 @@ typedef struct
static usbd_control_xfer_t _ctrl_xfer; static usbd_control_xfer_t _ctrl_xfer;
CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// Application API // Application API
@ -60,8 +60,14 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_EN
static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request) static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
{ {
// Opposite to endpoint in Data Phase
uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
TU_LOG2(" XFER Endpoint: 0x%02X, Bytes: %d\n", ep_addr, 0);
// status direction is reversed to one in the setup packet // status direction is reversed to one in the setup packet
return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0); // Note: Status must always be DATA1
return dcd_edpt_xfer(rhport, ep_addr, NULL, 0);
} }
// Status phase // Status phase
@ -106,6 +112,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
// Data stage // Data stage
TU_ASSERT( _data_stage_xact(rhport) ); TU_ASSERT( _data_stage_xact(rhport) );
TU_LOG2(" XFER Endpoint: 0x%02X, Bytes: %d\n", request->bmRequestType_bit.direction ? EDPT_CTRL_IN : EDPT_CTRL_OUT, _ctrl_xfer.data_len);
}else }else
{ {
// Status stage // Status stage