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https://github.com/hathach/tinyusb.git
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better multiple interfaces support for cdc device
This commit is contained in:
hathach
parent
a4292e5906
commit
a623f0c179
@ -51,18 +51,19 @@
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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typedef struct {
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CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
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typedef struct
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{
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/*------------- usbd_itf_t compatible -------------*/
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uint8_t itf_num;
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uint8_t ep_count;
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uint8_t ep_notif;
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uint8_t ep_in;
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uint8_t ep_out;
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cdc_acm_capability_t acm_cap;
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// Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
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uint8_t line_state;
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CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
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}cdcd_interface_t;
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//--------------------------------------------------------------------+
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@ -71,8 +72,11 @@ typedef struct {
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CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN static uint8_t _tmp_rx_buf[64];
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CFG_TUSB_ATTR_USBRAM CFG_TUSB_MEM_ALIGN static uint8_t _tmp_tx_buf[64];
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TU_FIFO_DEF(_rx_ff, CFG_TUD_CDC_RX_BUFSIZE, uint8_t, true);
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TU_FIFO_DEF(_tx_ff, CFG_TUD_CDC_TX_BUFSIZE, uint8_t, false);
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uint8_t _rx_ff_buf[CFG_TUD_CDC][CFG_TUD_CDC_RX_BUFSIZE];
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uint8_t _tx_ff_buf[CFG_TUD_CDC][CFG_TUD_CDC_RX_BUFSIZE];
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tu_fifo_t _rx_ff[CFG_TUD_CDC];
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tu_fifo_t _tx_ff[CFG_TUD_CDC];
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CFG_TUSB_ATTR_USBRAM
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static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
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@ -80,66 +84,66 @@ static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
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//--------------------------------------------------------------------+
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// APPLICATION API
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//--------------------------------------------------------------------+
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bool tud_cdc_n_connected(uint8_t rhport)
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bool tud_cdc_n_connected(uint8_t itf)
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{
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// DTR (bit 0) active isconsidered as connected
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return BIT_TEST_(_cdcd_itf[rhport].line_state, 0);
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return BIT_TEST_(_cdcd_itf[itf].line_state, 0);
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}
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uint8_t tud_cdc_n_get_line_state (uint8_t rhport)
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uint8_t tud_cdc_n_get_line_state (uint8_t itf)
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{
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return _cdcd_itf[rhport].line_state;
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return _cdcd_itf[itf].line_state;
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}
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void tud_cdc_n_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding)
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void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding)
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{
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(*coding) = _cdcd_itf[0].line_coding;
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(*coding) = _cdcd_itf[itf].line_coding;
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}
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//--------------------------------------------------------------------+
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// READ API
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//--------------------------------------------------------------------+
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uint32_t tud_cdc_n_available(uint8_t rhport)
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uint32_t tud_cdc_n_available(uint8_t itf)
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{
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return tu_fifo_count(&_rx_ff);
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return tu_fifo_count(&_rx_ff[itf]);
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}
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int8_t tud_cdc_n_read_char(uint8_t rhport)
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int8_t tud_cdc_n_read_char(uint8_t itf)
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{
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int8_t ch;
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return tu_fifo_read(&_rx_ff, &ch) ? ch : (-1);
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return tu_fifo_read(&_rx_ff[itf], &ch) ? ch : (-1);
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}
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uint32_t tud_cdc_n_read(uint8_t rhport, void* buffer, uint32_t bufsize)
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uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
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{
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return tu_fifo_read_n(&_rx_ff, buffer, bufsize);
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return tu_fifo_read_n(&_rx_ff[itf], buffer, bufsize);
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}
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//--------------------------------------------------------------------+
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// WRITE API
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//--------------------------------------------------------------------+
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uint32_t tud_cdc_n_write_char(uint8_t rhport, char ch)
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uint32_t tud_cdc_n_write_char(uint8_t itf, char ch)
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{
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return tu_fifo_write(&_tx_ff, &ch) ? 1 : 0;
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return tu_fifo_write(&_tx_ff[itf], &ch) ? 1 : 0;
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}
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uint32_t tud_cdc_n_write(uint8_t rhport, void const* buffer, uint32_t bufsize)
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uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
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{
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return tu_fifo_write_n(&_tx_ff, buffer, bufsize);
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return tu_fifo_write_n(&_tx_ff[itf], buffer, bufsize);
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}
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bool tud_cdc_n_flush (uint8_t rhport)
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bool tud_cdc_n_flush (uint8_t itf)
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{
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uint8_t edpt = _cdcd_itf[rhport].ep_in;
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VERIFY( !dcd_edpt_busy(rhport, edpt) ); // skip if previous transfer not complete
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uint8_t edpt = _cdcd_itf[itf].ep_in;
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VERIFY( !dcd_edpt_busy(TUD_RHPORT, edpt) ); // skip if previous transfer not complete
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uint16_t count = tu_fifo_read_n(&_tx_ff, _tmp_tx_buf, sizeof(_tmp_tx_buf));
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uint16_t count = tu_fifo_read_n(&_tx_ff[itf], _tmp_tx_buf, sizeof(_tmp_tx_buf));
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VERIFY( tud_cdc_n_connected(rhport) ); // fifo is empty if not connected
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VERIFY( tud_cdc_n_connected(itf) ); // fifo is empty if not connected
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if ( count ) TU_ASSERT( dcd_edpt_xfer(rhport, edpt, _tmp_tx_buf, count) );
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if ( count ) TU_ASSERT( dcd_edpt_xfer(TUD_RHPORT, edpt, _tmp_tx_buf, count) );
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return true;
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}
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@ -152,13 +156,10 @@ void cdcd_init(void)
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{
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arrclr_(_cdcd_itf);
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// default line coding is : stop bit = 1, parity = none, data bits = 8
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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_cdcd_itf[i].line_coding.bit_rate = 115200;
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_cdcd_itf[i].line_coding.stop_bits = 0;
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_cdcd_itf[i].line_coding.parity = 0;
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_cdcd_itf[i].line_coding.data_bits = 8;
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tu_fifo_config(&_rx_ff[i], _rx_ff_buf[i], CFG_TUD_CDC_RX_BUFSIZE, 1, true);
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tu_fifo_config(&_tx_ff[i], _tx_ff_buf[i], CFG_TUD_CDC_TX_BUFSIZE, 1, false);
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}
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}
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@ -172,20 +173,27 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
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return TUSB_ERROR_CDC_UNSUPPORTED_PROTOCOL;
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}
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uint8_t const * p_desc = descriptor_next ( (uint8_t const *) p_interface_desc );
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cdcd_interface_t * p_cdc = &_cdcd_itf[rhport];
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// Find available interface
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cdcd_interface_t * p_cdc = NULL;
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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if ( _cdcd_itf[i].ep_count == 0 )
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{
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p_cdc = &_cdcd_itf[i];
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break;
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}
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}
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//------------- Communication Interface -------------//
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//------------- Control Interface -------------//
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p_cdc->itf_num = p_interface_desc->bInterfaceNumber;
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p_cdc->ep_count = p_interface_desc->bNumEndpoints;
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uint8_t const * p_desc = descriptor_next ( (uint8_t const *) p_interface_desc );
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(*p_length) = sizeof(tusb_desc_interface_t);
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// Communication Functional Descriptors
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while( TUSB_DESC_CLASS_SPECIFIC == p_desc[DESCRIPTOR_OFFSET_TYPE] )
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{
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if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
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{ // save ACM bmCapabilities
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p_cdc->acm_cap = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
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}
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(*p_length) += p_desc[DESCRIPTOR_OFFSET_LENGTH];
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p_desc = descriptor_next(p_desc);
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}
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@ -204,6 +212,10 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
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if ( (TUSB_DESC_INTERFACE == p_desc[DESCRIPTOR_OFFSET_TYPE]) &&
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(TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
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{
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// p_cdc->itf_num =
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p_cdc->ep_count += ((tusb_desc_interface_t const *) p_desc)->bNumEndpoints;
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// next to endpoint descritpor
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(*p_length) += p_desc[DESCRIPTOR_OFFSET_LENGTH];
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p_desc = descriptor_next(p_desc);
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@ -214,8 +226,6 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
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(*p_length) += 2*sizeof(tusb_desc_endpoint_t);
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}
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p_cdc->itf_num = p_interface_desc->bInterfaceNumber;
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// Prepare for incoming data
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TU_ASSERT( dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
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@ -225,10 +235,15 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
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void cdcd_close(uint8_t rhport)
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{
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// no need to close opened pipe, dcd bus reset will put controller's endpoints to default state
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memclr_(&_cdcd_itf[rhport], sizeof(cdcd_interface_t));
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(void) rhport;
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tu_fifo_clear(&_rx_ff);
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tu_fifo_clear(&_tx_ff);
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arrclr_(_cdcd_itf);
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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tu_fifo_clear(&_rx_ff[i]);
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tu_fifo_clear(&_tx_ff[i]);
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}
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}
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tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t const * p_request)
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@ -238,16 +253,19 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
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//------------- Class Specific Request -------------//
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if (p_request->bmRequestType_bit.type != TUSB_REQ_TYPE_CLASS) return TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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// TODO Support multiple interface
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// TODO Support multiple interfaces
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uint8_t const itf = 0;
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cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
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if ( (CDC_REQUEST_GET_LINE_CODING == p_request->bRequest) || (CDC_REQUEST_SET_LINE_CODING == p_request->bRequest) )
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{
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uint16_t len = min16_of(sizeof(cdc_line_coding_t), p_request->wLength);
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usbd_control_xfer_st(rhport, p_request->bmRequestType_bit.direction, (uint8_t*) &_cdcd_itf[0].line_coding, len);
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usbd_control_xfer_st(rhport, p_request->bmRequestType_bit.direction, &p_cdc->line_coding, len);
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// Invoke callback
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if (CDC_REQUEST_SET_LINE_CODING == p_request->bRequest)
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{
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if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(rhport, &_cdcd_itf[0].line_coding);
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if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
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}
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}
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else if (CDC_REQUEST_SET_CONTROL_LINE_STATE == p_request->bRequest )
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@ -257,14 +275,13 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
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// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
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// Bit 1: Carrier control for half-duplex modems.
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// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
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cdcd_interface_t * p_cdc = &_cdcd_itf[rhport];
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p_cdc->line_state = (uint8_t) p_request->wValue;
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dcd_control_status(rhport, p_request->bmRequestType_bit.direction); // ACK control request
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// Invoke callback
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if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(rhport, BIT_TEST_(p_request->wValue, 0), BIT_TEST_(p_request->wValue, 1));
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if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, BIT_TEST_(p_request->wValue, 0), BIT_TEST_(p_request->wValue, 1));
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}
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else
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{
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@ -276,17 +293,19 @@ tusb_error_t cdcd_control_request_st(uint8_t rhport, tusb_control_request_t cons
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tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, uint32_t xferred_bytes)
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{
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cdcd_interface_t const * p_cdc = &_cdcd_itf[rhport];
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// TODO Support multiple interfaces
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uint8_t const itf = 0;
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cdcd_interface_t const * p_cdc = &_cdcd_itf[itf];
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if ( ep_addr == p_cdc->ep_out )
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{
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tu_fifo_write_n(&_rx_ff, _tmp_rx_buf, xferred_bytes);
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tu_fifo_write_n(&_rx_ff[itf], _tmp_rx_buf, xferred_bytes);
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// preparing for next
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TU_ASSERT( dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER );
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// fire callback
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if (tud_cdc_rx_cb) tud_cdc_rx_cb(rhport);
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if (tud_cdc_rx_cb) tud_cdc_rx_cb(itf);
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}
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return TUSB_ERROR_NONE;
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@ -295,7 +314,10 @@ tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
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#if CFG_TUD_CDC_FLUSH_ON_SOF
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void cdcd_sof(uint8_t rhport)
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{
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tud_cdc_n_flush(rhport);
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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tud_cdc_n_flush(i);
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}
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}
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#endif
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@ -56,39 +56,39 @@
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// APPLICATION API (Multiple Interfaces)
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// CFG_TUD_CDC > 1
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//--------------------------------------------------------------------+
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bool tud_cdc_n_connected (uint8_t rhport);
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uint8_t tud_cdc_n_get_line_state (uint8_t rhport);
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void tud_cdc_n_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding);
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bool tud_cdc_n_connected (uint8_t itf);
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uint8_t tud_cdc_n_get_line_state (uint8_t itf);
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void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding);
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uint32_t tud_cdc_n_available (uint8_t rhport);
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int8_t tud_cdc_n_read_char (uint8_t rhport);
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uint32_t tud_cdc_n_read (uint8_t rhport, void* buffer, uint32_t bufsize);
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uint32_t tud_cdc_n_available (uint8_t itf);
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int8_t tud_cdc_n_read_char (uint8_t itf);
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uint32_t tud_cdc_n_read (uint8_t itf, void* buffer, uint32_t bufsize);
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uint32_t tud_cdc_n_write_char (uint8_t rhport, char ch);
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uint32_t tud_cdc_n_write (uint8_t rhport, void const* buffer, uint32_t bufsize);
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bool tud_cdc_n_flush (uint8_t rhport);
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uint32_t tud_cdc_n_write_char (uint8_t itf, char ch);
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uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize);
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bool tud_cdc_n_flush (uint8_t itf);
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//--------------------------------------------------------------------+
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// APPLICATION API (Interface0)
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//--------------------------------------------------------------------+
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static inline bool tud_cdc_connected (void) { return tud_cdc_n_connected(0); }
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static inline uint8_t tud_cdc_get_line_state (uint8_t rhport) { return tud_cdc_n_get_line_state(0); }
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static inline void tud_cdc_get_line_coding (uint8_t rhport, cdc_line_coding_t* coding) { return tud_cdc_get_line_coding(0, coding); }
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static inline bool tud_cdc_connected (void) { return tud_cdc_n_connected(0); }
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static inline uint8_t tud_cdc_get_line_state (void) { return tud_cdc_n_get_line_state(0); }
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static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding) { return tud_cdc_n_get_line_coding(0, coding);}
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static inline uint32_t tud_cdc_available (void) { return tud_cdc_n_available(0); }
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static inline int8_t tud_cdc_read_char (void) { return tud_cdc_n_read_char(0); }
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static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize) { return tud_cdc_n_read(0, buffer, bufsize); }
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static inline uint32_t tud_cdc_available (void) { return tud_cdc_n_available(0); }
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static inline int8_t tud_cdc_read_char (void) { return tud_cdc_n_read_char(0); }
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static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize) { return tud_cdc_n_read(0, buffer, bufsize); }
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static inline uint32_t tud_cdc_write_char (char ch) { return tud_cdc_n_write_char(0, ch); }
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static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize) { return tud_cdc_n_write(0, buffer, bufsize); }
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static inline bool tud_cdc_flush (void) { return tud_cdc_n_flush(0); }
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static inline uint32_t tud_cdc_write_char (char ch) { return tud_cdc_n_write_char(0, ch); }
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static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize) { return tud_cdc_n_write(0, buffer, bufsize); }
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||||
static inline bool tud_cdc_flush (void) { return tud_cdc_n_flush(0); }
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION CALLBACK API (WEAK is optional)
|
||||
//--------------------------------------------------------------------+
|
||||
ATTR_WEAK void tud_cdc_rx_cb(uint8_t rhport);
|
||||
ATTR_WEAK void tud_cdc_line_state_cb(uint8_t rhport, bool dtr, bool rts);
|
||||
ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t rhport, cdc_line_coding_t const* p_line_coding);
|
||||
ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
|
||||
ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
|
||||
ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBD-CLASS DRIVER API
|
||||
|
||||
@ -528,6 +528,8 @@ void dcd_bus_event(uint8_t rhport, usbd_bus_event_type_t bus_event)
|
||||
varclr_(&_usbd_dev);
|
||||
osal_queue_flush(_usbd_q);
|
||||
osal_semaphore_reset_isr(_usbd_ctrl_sem);
|
||||
|
||||
// TODO move to unplugged
|
||||
for (uint8_t i = 0; i < USBD_CLASS_DRIVER_COUNT; i++)
|
||||
{
|
||||
if ( usbd_class_drivers[i].close ) usbd_class_drivers[i].close( rhport );
|
||||
|
||||
@ -45,6 +45,14 @@
|
||||
// for used by usbd_control_xfer_st() only, must not be used directly
|
||||
extern osal_semaphore_t _usbd_ctrl_sem;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t itf_num;
|
||||
uint8_t ep_count;
|
||||
uint8_t ep_arr[1];
|
||||
}usbd_itf_t;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// INTERNAL API for stack management
|
||||
//--------------------------------------------------------------------+
|
||||
@ -63,7 +71,7 @@ tusb_error_t usbd_open_edpt_pair(uint8_t rhport, tusb_desc_endpoint_t const* p_d
|
||||
do {\
|
||||
if (_len) { \
|
||||
tusb_error_t err;\
|
||||
dcd_control_xfer(_rhport, _dir, _buffer, _len);\
|
||||
dcd_control_xfer(_rhport, _dir, (uint8_t*) _buffer, _len);\
|
||||
osal_semaphore_wait( _usbd_ctrl_sem, OSAL_TIMEOUT_CONTROL_XFER, &err );\
|
||||
STASK_ASSERT_ERR( err );\
|
||||
}\
|
||||
|
||||
@ -107,6 +107,8 @@
|
||||
#define MODE_HOST_SUPPORTED (CONTROLLER_HOST_NUMBER > 0)
|
||||
#define MODE_DEVICE_SUPPORTED (CONTROLLER_DEVICE_NUMBER > 0)
|
||||
|
||||
#define TUD_RHPORT ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) ? 0 : ((CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE) ? 1 : -1))
|
||||
|
||||
#if !MODE_HOST_SUPPORTED && !MODE_DEVICE_SUPPORTED
|
||||
#error please configure at least 1 CFG_TUSB_CONTROLLER_N_MODE to OPT_MODE_HOST and/or OPT_MODE_DEVICE
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user