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https://github.com/hathach/tinyusb.git
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9e9f331503
@ -513,6 +513,20 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo
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return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
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}
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#if CFG_TUSB_DEBUG
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TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
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{
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static const char *str[] = {"out", "in"};
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return str[dir];
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}
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TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
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{
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static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
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return str[t];
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}
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#endif
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//--------------------------------------------------------------------+
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// Descriptor helper
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//--------------------------------------------------------------------+
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@ -138,20 +138,25 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
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_handle_buff_status_bit(bit, ep);
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}
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// Check interrupt endpoints
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// Check "interrupt" (asynchronous) endpoints for both IN and OUT
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for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
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{
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// EPX is bit 0
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// IEP1 is bit 2
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// IEP2 is bit 4
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// IEP3 is bit 6
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// EPX is bit 0 & 1
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// IEP1 IN is bit 2
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// IEP1 OUT is bit 3
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// IEP2 IN is bit 4
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// IEP2 OUT is bit 5
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// IEP3 IN is bit 6
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// IEP3 OUT is bit 7
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// etc
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bit = 1 << (i*2);
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if (remaining_buffers & bit)
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for(uint j = 0; j < 2; j++)
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{
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remaining_buffers &= ~bit;
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_handle_buff_status_bit(bit, &ep_pool[i]);
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bit = 1 << (i*2+j);
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if (remaining_buffers & bit)
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{
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remaining_buffers &= ~bit;
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_handle_buff_status_bit(bit, &ep_pool[i]);
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}
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}
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}
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@ -273,10 +278,12 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
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{
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struct hw_endpoint *ep = NULL;
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if (transfer_type == TUSB_XFER_INTERRUPT)
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if (transfer_type != TUSB_XFER_CONTROL)
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{
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// Note: even though datasheet name these "Interrupt" endpoints. These are actually
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// "Asynchronous" endpoints and can be used for other type such as: Bulk (ISO need confirmation)
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ep = _next_free_interrupt_ep();
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pico_info("Allocate interrupt ep %d\n", ep->interrupt_num);
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pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
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assert(ep);
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ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
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ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
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@ -337,13 +344,13 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
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pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
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ep->configured = true;
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if (bmInterval)
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if (ep != &epx)
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{
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// This is an interrupt endpoint
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// so need to set up interrupt endpoint address control register with:
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// device address
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// endpoint number / direction
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// preamble
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// Endpoint has its own addr_endp and interrupt bits to be setup!
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// This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
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// - device address
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// - endpoint number / direction
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// - preamble
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uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
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if (dir == TUSB_DIR_OUT)
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@ -523,6 +530,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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// Get appropriate ep. Either EPX or interrupt endpoint
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struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
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TU_ASSERT(ep);
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// EP should be inactive
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