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dma rx works well

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hathach 2023-06-08 13:37:37 +07:00
parent fc761953b3
commit 9c2a8490af
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GPG Key ID: F5D50C6D51D17CBA
3 changed files with 267 additions and 14 deletions
hw/bsp/stm32g4
boards/b_g474e_dpow1/cubemx
board.ioc
family.c
src/portable/st/typec
typec_stm32.c

194
hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc Normal file

@ -0,0 +1,194 @@
#MicroXplorer Configuration settings - do not modify
CAD.formats=
CAD.pinconfig=
CAD.provider=
Dma.Request0=UCPD1_RX
Dma.Request1=UCPD1_TX
Dma.RequestsNb=2
Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.UCPD1_RX.0.EventEnable=DISABLE
Dma.UCPD1_RX.0.Instance=DMA1_Channel1
Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE
Dma.UCPD1_RX.0.Mode=DMA_NORMAL
Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_HIGH
Dma.UCPD1_RX.0.RequestNumber=1
Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UCPD1_RX.0.SignalID=NONE
Dma.UCPD1_RX.0.SyncEnable=DISABLE
Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UCPD1_RX.0.SyncRequestNumber=1
Dma.UCPD1_RX.0.SyncSignalID=NONE
Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
Dma.UCPD1_TX.1.EventEnable=DISABLE
Dma.UCPD1_TX.1.Instance=DMA1_Channel2
Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE
Dma.UCPD1_TX.1.Mode=DMA_NORMAL
Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_HIGH
Dma.UCPD1_TX.1.RequestNumber=1
Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UCPD1_TX.1.SignalID=NONE
Dma.UCPD1_TX.1.SyncEnable=DISABLE
Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UCPD1_TX.1.SyncRequestNumber=1
Dma.UCPD1_TX.1.SyncSignalID=NONE
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=true
Mcu.CPN=STM32G474RET3
Mcu.Family=STM32G4
Mcu.IP0=DMA
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SYS
Mcu.IP4=UCPD1
Mcu.IP5=USART3
Mcu.IPNb=6
Mcu.Name=STM32G474R(B-C-E)Tx
Mcu.Package=LQFP64
Mcu.Pin0=PC10
Mcu.Pin1=PC11
Mcu.Pin2=PB4
Mcu.Pin3=PB6
Mcu.Pin4=VP_SYS_VS_Systick
Mcu.Pin5=VP_SYS_VS_DBSignals
Mcu.PinsNb=6
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32G474RETx
MxCube.Version=6.8.1
MxDb.Version=DB.6.0.81
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
PB4.Mode=Sink_AllSignals
PB4.Signal=UCPD1_CC2
PB6.Mode=Sink_AllSignals
PB6.Signal=UCPD1_CC1
PC10.GPIOParameters=GPIO_PuPd
PC10.GPIO_PuPd=GPIO_PULLUP
PC10.Mode=Asynchronous
PC10.Signal=USART3_TX
PC11.GPIOParameters=GPIO_PuPd
PC11.GPIO_PuPd=GPIO_PULLUP
PC11.Mode=Asynchronous
PC11.Signal=USART3_RX
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32G474RETx
ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=2
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=board.ioc
ProjectManager.ProjectName=board
ProjectManager.ProjectStructure=
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=Makefile
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true
RCC.ADC12Freq_Value=150000000
RCC.ADC345Freq_Value=150000000
RCC.AHBFreq_Value=150000000
RCC.APB1Freq_Value=150000000
RCC.APB1TimFreq_Value=150000000
RCC.APB2Freq_Value=150000000
RCC.APB2TimFreq_Value=150000000
RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=150000000
RCC.EXTERNAL_CLOCK_VALUE=12288000
RCC.FCLKCortexFreq_Value=150000000
RCC.FDCANFreq_Value=150000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=150000000
RCC.HRTIM1Freq_Value=150000000
RCC.HSE_VALUE=24000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=150000000
RCC.I2C2Freq_Value=150000000
RCC.I2C3Freq_Value=150000000
RCC.I2C4Freq_Value=150000000
RCC.I2SFreq_Value=150000000
RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=150000000
RCC.LPUART1Freq_Value=150000000
RCC.LSCOPinFreq_Value=32000
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=16000000
RCC.PLLM=RCC_PLLM_DIV4
RCC.PLLN=75
RCC.PLLPoutputFreq_Value=150000000
RCC.PLLQ=RCC_PLLQ_DIV4
RCC.PLLQoutputFreq_Value=75000000
RCC.PLLRCLKFreq_Value=150000000
RCC.PWRFreq_Value=150000000
RCC.QSPIFreq_Value=150000000
RCC.RNGFreq_Value=75000000
RCC.SAI1Freq_Value=150000000
RCC.SYSCLKFreq_VALUE=150000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=150000000
RCC.UART5Freq_Value=150000000
RCC.USART1Freq_Value=150000000
RCC.USART2Freq_Value=150000000
RCC.USART3Freq_Value=150000000
RCC.USBFreq_Value=75000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=300000000
USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
USART3.BaudRate=115200
USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
USART3.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
USART3.Mode=MODE_TX_RX
USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
USART3.OverSampling=UART_OVERSAMPLING_16
USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
USART3.Parity=PARITY_ODD
USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
USART3.StopBits=STOPBITS_1
USART3.SwapParam=ADVFEATURE_SWAP_DISABLE
USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
USART3.VirtualMode-Asynchronous=VM_ASYNC
USART3.WordLength=WORDLENGTH_8B
VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom

7
hw/bsp/stm32g4/family.c

@ -144,15 +144,16 @@ void board_init(void)
#if 1 #if 1
// USB PD // USB PD
// Default CC1/CC2 is PB4/PB6
/* PWR register access (for disabling dead battery feature) */ /* PWR register access (for disabling dead battery feature) */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
__HAL_RCC_UCPD1_CLK_ENABLE(); __HAL_RCC_UCPD1_CLK_ENABLE();
// Default CC1/CC2 is PB4/PB6 // Enable DMA clock
// PB4 ------> UCPD1_CC2 __HAL_RCC_DMAMUX1_CLK_ENABLE();
// PB6 ------> UCPD1_CC1 __HAL_RCC_DMA1_CLK_ENABLE();
#endif #endif
} }

80
src/portable/st/typec/typec_stm32.c

@ -31,6 +31,7 @@
#if CFG_TUSB_MCU == OPT_MCU_STM32G4 #if CFG_TUSB_MCU == OPT_MCU_STM32G4
#include "stm32g4xx.h" #include "stm32g4xx.h"
#include "stm32g4xx_hal_dma.h"
#else #else
#error "Unsupported STM32 family" #error "Unsupported STM32 family"
#endif #endif
@ -61,13 +62,46 @@ static uint32_t rx_count = 0;
static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4); static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
static uint32_t tx_count; static uint32_t tx_count;
#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
#ifdef CFG_TUC_STM32_DMA_RX
static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
TU_ATTR_ALWAYS_INLINE static inline
void dma_rx_start(uint8_t rhport)
{
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
dma_rx_ch->CMAR = (uint32_t) rx_buf;
dma_rx_ch->CNDTR = sizeof(rx_buf);
dma_rx_ch->CCR |= DMA_CCR_EN;
}
#endif
#ifdef CFG_TUC_STM32_DMA_TX
static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
#endif
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// //
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
#include "stm32g4xx_ll_dma.h"
bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) { bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
(void) rhport; (void) rhport;
#ifdef CFG_TUC_STM32_DMA_RX
// Init DMA
DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
// Peripheral -> Memory, Memory inc, 8-bit, High priority
dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
#endif
// Initialization phase: CFG1 // Initialization phase: CFG1
UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) | UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) | (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
@ -77,7 +111,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
// General programming sequence (with UCPD configured then enabled) // General programming sequence (with UCPD configured then enabled)
if (port_type == TUSB_TYPEC_PORT_SNK) { if (port_type == TUSB_TYPEC_PORT_SNK) {
// Enable both CC Phy // Enable both CC Phy
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos); UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
// Read Voltage State on CC1 & CC2 fore initial state // Read Voltage State on CC1 & CC2 fore initial state
uint32_t vstate_cc[2]; uint32_t vstate_cc[2];
@ -135,30 +169,48 @@ void tcd_int_handler(uint8_t rhport) {
TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]); TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
uint32_t cr = UCPD1->CR; uint32_t cr = UCPD1->CR;
uint32_t cfg1 = UCPD1->CFG1;
// TODO only support SNK for now, required highest voltage for now // TODO only support SNK for now, required highest voltage for now
// Enable PHY on correct CC and disable Rd on other CC
if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) { if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
TU_LOG1("Attach CC1\n"); TU_LOG1("Attach CC1\n");
cr &= ~UCPD_CR_PHYCCSEL;
cr |= UCPD_CR_PHYRXEN; cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
} else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) { } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
TU_LOG1("Attach CC2\n"); TU_LOG1("Attach CC2\n");
cr |= UCPD_CR_PHYCCSEL; cr &= ~UCPD_CR_CCENABLE;
cr |= UCPD_CR_PHYRXEN; cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
} else { } else {
TU_LOG1("Detach\n"); TU_LOG1("Detach\n");
cr &= ~UCPD_CR_PHYRXEN; cr &= ~UCPD_CR_PHYRXEN;
cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
} }
if (cr & UCPD_CR_PHYRXEN) { if (cr & UCPD_CR_PHYRXEN) {
// Enable Interrupt // Enable Interrupt
UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | uint32_t imr = UCPD1->IMR;
UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE; UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
#ifdef CFG_TUC_STM32_DMA_RX
cfg1 |= UCPD_CFG1_RXDMAEN;
dma_rx_start(rhport);
#else
imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
#endif
#ifndef CFG_TUC_STM32_DMA_TX
imr |= UCPD_IMR_TXISIE;
#endif
UCPD1->IMR = imr;
} }
// Enable PD RX
UCPD1->CR = cr; UCPD1->CR = cr;
UCPD1->CFG1 = cfg1;
// ack // ack
UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF; UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
@ -176,6 +228,7 @@ void tcd_int_handler(uint8_t rhport) {
UCPD1->ICR = UCPD_ICR_RXORDDETCF; UCPD1->ICR = UCPD_ICR_RXORDDETCF;
} }
#ifndef CFG_TUC_STM32_DMA_RX
if (sr & UCPD_SR_RXNE) { if (sr & UCPD_SR_RXNE) {
// TODO DMA later // TODO DMA later
do { do {
@ -184,8 +237,9 @@ void tcd_int_handler(uint8_t rhport) {
// no ack needed // no ack needed
} }
#endif
// End of message // Received full message
if (sr & UCPD_SR_RXMSGEND) { if (sr & UCPD_SR_RXMSGEND) {
// Skip if CRC failed // Skip if CRC failed
@ -213,13 +267,17 @@ void tcd_int_handler(uint8_t rhport) {
// notify stack after good crc ? // notify stack after good crc ?
} }
#ifdef CFG_TUC_STM32_DMA_RX
// prepare next receive
dma_rx_start(rhport);
#endif
// ack // ack
UCPD1->ICR = UCPD_ICR_RXMSGENDCF; UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
} }
if (sr & UCPD_SR_RXOVR) { if (sr & UCPD_SR_RXOVR) {
TU_LOG1("RXOVR\n"); TU_LOG1("RXOVR\n");
TU_LOG1_HEX(rx_count);
// ack // ack
UCPD1->ICR = UCPD_ICR_RXOVRCF; UCPD1->ICR = UCPD_ICR_RXOVRCF;
} }