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https://github.com/hathach/tinyusb.git
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style changes
This commit is contained in:
hathach
parent
290f4bea91
commit
8eca596fa6
@ -35,9 +35,9 @@
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//--------------------------------------------------------------------+
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// Callback weak stubs (called if application does not provide)
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//--------------------------------------------------------------------+
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TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) {
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(void)rhport;
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(void)request;
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TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
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(void) rhport;
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(void) request;
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}
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//--------------------------------------------------------------------+
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@ -50,7 +50,7 @@ extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callb
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enum {
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EDPT_CTRL_OUT = 0x00,
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EDPT_CTRL_IN = 0x80
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EDPT_CTRL_IN = 0x80
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};
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typedef struct {
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@ -71,20 +71,18 @@ tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
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//--------------------------------------------------------------------+
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// Queue ZLP status transaction
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static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
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{
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static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) {
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// Opposite to endpoint in Data Phase
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uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
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return usbd_edpt_xfer(rhport, ep_addr, NULL, 0);
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}
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// Status phase
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bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
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{
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = NULL;
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bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) {
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = NULL;
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_ctrl_xfer.total_xferred = 0;
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_ctrl_xfer.data_len = 0;
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_ctrl_xfer.data_len = 0;
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return _status_stage_xact(rhport, request);
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}
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@ -92,16 +90,15 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
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// Queue a transaction in Data Stage
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// Each transaction has up to Endpoint0's max packet size.
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// This function can also transfer an zero-length packet
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static bool _data_stage_xact(uint8_t rhport)
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{
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uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
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static bool _data_stage_xact(uint8_t rhport) {
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uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred,
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CFG_TUD_ENDPOINT0_SIZE);
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uint8_t ep_addr = EDPT_CTRL_OUT;
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if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
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{
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if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) {
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ep_addr = EDPT_CTRL_IN;
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if ( xact_len ) {
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if (xact_len) {
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TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len));
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}
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}
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@ -111,29 +108,24 @@ static bool _data_stage_xact(uint8_t rhport)
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// Transmit data to/from the control endpoint.
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// If the request's wLength is zero, a status packet is sent instead.
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bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
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{
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = (uint8_t*) buffer;
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bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, void* buffer, uint16_t len) {
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = (uint8_t*) buffer;
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_ctrl_xfer.total_xferred = 0U;
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_ctrl_xfer.data_len = tu_min16(len, request->wLength);
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_ctrl_xfer.data_len = tu_min16(len, request->wLength);
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if (request->wLength > 0U)
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{
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if(_ctrl_xfer.data_len > 0U)
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{
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if (request->wLength > 0U) {
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if (_ctrl_xfer.data_len > 0U) {
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TU_ASSERT(buffer);
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}
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// TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len);
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// Data stage
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TU_ASSERT( _data_stage_xact(rhport) );
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}
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else
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{
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TU_ASSERT(_data_stage_xact(rhport));
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} else {
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// Status stage
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TU_ASSERT( _status_stage_xact(rhport, request) );
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TU_ASSERT(_status_stage_xact(rhport, request));
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}
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return true;
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@ -143,46 +135,41 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
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// USBD API
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//--------------------------------------------------------------------+
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void usbd_control_reset(void);
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void usbd_control_set_request(tusb_control_request_t const *request);
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void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
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bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
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void usbd_control_set_request(tusb_control_request_t const* request);
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void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp);
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bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
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void usbd_control_reset(void) {
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tu_varclr(&_ctrl_xfer);
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}
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// Set complete callback
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void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp )
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{
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void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) {
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_ctrl_xfer.complete_cb = fp;
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}
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// for dcd_set_address where DCD is responsible for status response
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void usbd_control_set_request(tusb_control_request_t const *request)
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{
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = NULL;
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void usbd_control_set_request(tusb_control_request_t const* request) {
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_ctrl_xfer.request = (*request);
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_ctrl_xfer.buffer = NULL;
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_ctrl_xfer.total_xferred = 0;
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_ctrl_xfer.data_len = 0;
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_ctrl_xfer.data_len = 0;
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}
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// callback when a transaction complete on
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// - DATA stage of control endpoint or
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// - Status stage
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bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
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{
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bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
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(void) result;
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// Endpoint Address is opposite to direction bit, this is Status Stage complete event
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if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
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{
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if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) {
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TU_ASSERT(0 == xferred_bytes);
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// invoke optional dcd hook if available
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dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
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if (_ctrl_xfer.complete_cb)
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{
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if (_ctrl_xfer.complete_cb) {
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// TODO refactor with usbd_driver_print_control_complete_name
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_ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request);
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}
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@ -190,8 +177,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
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return true;
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}
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if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
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{
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if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) {
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TU_VERIFY(_ctrl_xfer.buffer);
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memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
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TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2);
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@ -202,15 +188,14 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
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// Data Stage is complete when all request's length are transferred or
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// a short packet is sent including zero-length packet.
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if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE) )
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{
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if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) ||
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(xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) {
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// DATA stage is complete
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bool is_ok = true;
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// invoke complete callback if set
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// callback can still stall control in status phase e.g out data does not make sense
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if ( _ctrl_xfer.complete_cb )
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{
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if (_ctrl_xfer.complete_cb) {
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#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
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usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
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#endif
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@ -218,21 +203,17 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
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is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request);
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}
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if ( is_ok )
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{
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if (is_ok) {
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// Send status
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TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) );
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}else
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{
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TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request));
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} else {
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// Stall both IN and OUT control endpoint
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dcd_edpt_stall(rhport, EDPT_CTRL_OUT);
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dcd_edpt_stall(rhport, EDPT_CTRL_IN);
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}
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}
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else
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{
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} else {
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// More data to transfer
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TU_ASSERT( _data_stage_xact(rhport) );
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TU_ASSERT(_data_stage_xact(rhport));
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}
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return true;
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