From 8df078dc9e8939969a8b4adb136d4e7fde3e7449 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 11:11:46 +0700 Subject: [PATCH] more rename --- src/portable/synopsys/dwc2/dcd_dwc2.c | 189 +++++++++++------------- src/portable/synopsys/dwc2/dwc2_esp32.h | 2 +- src/portable/synopsys/dwc2/dwc2_gd32.h | 2 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 8 +- 5 files changed, 97 insertions(+), 106 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b98bd0055..c0bf655f4 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -51,8 +51,7 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) -#define DEVICE_REG(_port) CORE_REG(_port) //((dwc2_core_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) +#define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) #define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) #define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) #define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) @@ -98,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * core = DWC2_REG(rhport); // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; @@ -116,8 +115,7 @@ static void bus_reset(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -125,7 +123,7 @@ static void bus_reset(uint8_t rhport) _out_ep_closed = false; // clear device address - dev->dcfg &= ~DCFG_DAD_Msk; + dwc2->dcfg &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { @@ -133,9 +131,9 @@ static void bus_reset(uint8_t rhport) } // 2. Un-mask interrupt bits - dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - dev->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dev->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -187,12 +185,12 @@ static void bus_reset(uint8_t rhport) // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to // overwrite this. - core->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + dwc2->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - core->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -200,15 +198,15 @@ static void bus_reset(uint8_t rhport) out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); - core->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; + dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } static tusb_speed_t get_speed(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - uint32_t const enum_spd = (dev->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } @@ -225,11 +223,11 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) bitvalue = DCD_FULL_SPEED; } - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // Clear and set speed bits - dev->dcfg &= ~(3 << DCFG_DSPD_Pos); - dev->dcfg |= (bitvalue << DCFG_DSPD_Pos); + dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos); + dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos); } #if defined(USB_HS_PHYC) @@ -277,7 +275,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -301,12 +299,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if(total_bytes != 0) { - dev->diepempmsk |= (1 << epnum); + dwc2->diepempmsk |= (1 << epnum); } } else { // A full OUT transfer (multiple packets, possibly) triggers XFRC. @@ -318,7 +316,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } @@ -331,7 +329,7 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // check GSNPSID @@ -341,23 +339,23 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - core->gccfg &= ~GCCFG_PWRDWN; + dwc2->gccfg &= ~GCCFG_PWRDWN; // Init The UTMI Interface - core->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); // Select default internal VBUS Indicator and Drive for ULPI - core->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); #else - core->gusbcfg |= GUSBCFG_PHYSEL; + dwc2->gusbcfg |= GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) // Highspeed with embedded UTMI PHYC // Select UTMI Interface - core->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; - core->gccfg |= GCCFG_PHYHSEN; + dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; + dwc2->gccfg |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -365,42 +363,40 @@ void dcd_init (uint8_t rhport) } else { // Enable internal PHY - core->gusbcfg |= GUSBCFG_PHYSEL; + dwc2->gusbcfg |= GUSBCFG_PHYSEL; } // Reset core after selecting PHYst // Wait AHB IDLE, reset then wait until it is cleared - while ((core->grstctl & GRSTCTL_AHBIDL) == 0U) {} - core->grstctl |= GRSTCTL_CSRST; - while ((core->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} + while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {} + dwc2->grstctl |= GRSTCTL_CSRST; + while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; // Clear all interrupts - core->gintsts |= core->gintsts; + dwc2->gintsts |= dwc2->gintsts; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - core->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; - - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. - dev->dcfg |= DCFG_NZLSOHSK; + dwc2->dcfg |= DCFG_NZLSOHSK; set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->gccfg |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->gccfg |= GCCFG_PWRDWN; - core->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | + dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; // Enable global interrupt - core->gahbcfg |= GAHBCFG_GINT; + dwc2->gahbcfg |= GAHBCFG_GINT; dcd_connect(rhport); } @@ -417,8 +413,8 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dcfg = (dev->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); @@ -428,34 +424,33 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); // set remote wakeup - dev->dctl |= DCTL_RWUSIG; + dwc2->dctl |= DCTL_RWUSIG; // enable SOF to detect bus resume - core->gintsts = GINTSTS_SOF; - core->gintmsk |= GINTMSK_SOFM; + dwc2->gintsts = GINTSTS_SOF; + dwc2->gintmsk |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms dwc2_remote_wakeup_delay(); - dev->dctl &= ~DCTL_RWUSIG; + dwc2->dctl &= ~DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dctl &= ~DCTL_SDIS; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dctl &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dctl |= DCTL_SDIS; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dctl |= DCTL_SDIS; } @@ -467,8 +462,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -489,12 +483,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint16_t const sz = calc_rx_ff_size(4*fifo_size); // If size_rx needs to be extended check if possible and if so enlarge it - if (core->grxfsiz < sz) + if (dwc2->grxfsiz < sz) { TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4); // Enlarge RX FIFO - core->grxfsiz = sz; + dwc2->grxfsiz = sz; } out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | @@ -502,7 +496,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); - dev->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); + dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); } else { @@ -528,7 +522,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->grxfsiz <= DWC2_EP_FIFO_SIZE/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= DWC2_EP_FIFO_SIZE/4); _allocated_fifo_words_tx += fifo_size; @@ -536,7 +530,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - core->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -544,7 +538,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DIEPCTL_MPSIZ_Pos); - dev->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } return true; @@ -555,13 +549,12 @@ void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; -// dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt - dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { @@ -642,8 +635,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -671,9 +663,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) } // Flush the FIFO, and wait until we have confirmed it cleared. - core->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos); - core->grstctl |= GRSTCTL_TXFFLSH; - while ( (core->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} + dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos); + dwc2->grstctl |= GRSTCTL_TXFFLSH; + while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} } else { @@ -688,8 +680,8 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. - dev->dctl |= DCTL_SGONAK; - while ( (core->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} + dwc2->dctl |= DCTL_SGONAK; + while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); @@ -698,7 +690,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) out_ep[epnum].DOEPINT = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. - dev->dctl |= DCTL_CGONAK; + dwc2->dctl |= DCTL_CGONAK; } } } @@ -708,7 +700,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) */ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -720,8 +712,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_IN) { - uint16_t const fifo_size = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; + uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; @@ -832,11 +824,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO - uint32_t ctl_word = core->grxstsp; + uint32_t ctl_word = dwc2->grxstsp; uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; @@ -896,7 +888,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { } } -static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *out_ep) +static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *out_ep) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. @@ -904,7 +896,7 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if ( dev->daint & (1 << (DAINT_OEPINT_Pos + n)) ) + if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. if ( out_ep[n].DOEPINT & DOEPINT_STUP ) @@ -933,14 +925,14 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o } } -static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in_ep) { +static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * in_ep) { // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - if ( dev->daint & (1 << (DAINT_IEPINT_Pos + n)) ) + if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). if ( in_ep[n].DIEPINT & DIEPINT_XFRC ) @@ -957,7 +949,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in } // XFER FIFO empty - if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->diepempmsk & (1 << n)) ) + if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) { // DIEPINT's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than @@ -996,7 +988,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in // Turn off TXFE if all bytes are written. if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { - dev->diepempmsk &= ~(1 << n); + dwc2->diepempmsk &= ~(1 << n); } } } @@ -1005,17 +997,16 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in void dcd_int_handler(uint8_t rhport) { - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); - uint32_t const int_status = core->gintsts & core->gintmsk; + uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. - core->gintsts = GINTSTS_USBRST; + dwc2->gintsts = GINTSTS_USBRST; bus_reset(rhport); } @@ -1023,23 +1014,23 @@ void dcd_int_handler(uint8_t rhport) { // ENUMDNE is the end of reset where speed of the link is detected - core->gintsts = GINTSTS_ENUMDNE; + dwc2->gintsts = GINTSTS_ENUMDNE; tusb_speed_t const speed = get_speed(rhport); - dwc2_set_turnaround(core, speed); + dwc2_set_turnaround(dwc2, speed); dcd_event_bus_reset(rhport, speed, true); } if(int_status & GINTSTS_USBSUSP) { - core->gintsts = GINTSTS_USBSUSP; + dwc2->gintsts = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } if(int_status & GINTSTS_WKUINT) { - core->gintsts = GINTSTS_WKUINT; + dwc2->gintsts = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1049,22 +1040,22 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only - uint32_t const otg_int = core->gotgint; + uint32_t const otg_int = dwc2->gotgint; if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } - core->gotgint = otg_int; + dwc2->gotgint = otg_int; } if(int_status & GINTSTS_SOF) { - core->gotgint = GINTSTS_SOF; + dwc2->gotgint = GINTSTS_SOF; // Disable SOF interrupt since currently only used for remote wakeup detection - core->gintmsk &= ~GINTMSK_SOFM; + dwc2->gintmsk &= ~GINTMSK_SOFM; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } @@ -1075,13 +1066,13 @@ void dcd_int_handler(uint8_t rhport) // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO - core->gintmsk &= ~GINTMSK_RXFLVLM; + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled do { handle_rxflvl_ints(rhport, out_ep); - } while(core->gotgint & GINTSTS_RXFLVL); + } while(dwc2->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) @@ -1092,21 +1083,21 @@ void dcd_int_handler(uint8_t rhport) _out_ep_closed = false; } - core->gintmsk |= GINTMSK_RXFLVLM; + dwc2->gintmsk |= GINTMSK_RXFLVLM; } // OUT endpoint interrupt handling. if(int_status & GINTSTS_OEPINT) { // OEPINT is read-only - handle_epout_ints(rhport, dev, out_ep); + handle_epout_ints(rhport, dwc2, out_ep); } // IN endpoint interrupt handling. if(int_status & GINTSTS_IEPINT) { // IEPINT bit read-only - handle_epin_ints(rhport, dev, in_ep); + handle_epin_ints(rhport, dwc2, in_ep); } // // Check for Incomplete isochronous IN transfer diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 5e544673d..d73ec0504 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -67,7 +67,7 @@ static inline void dwc2_remote_wakeup_delay(void) vTaskDelay(pdMS_TO_TICKS(1)); } -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { (void) core; (void) speed; diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index db1fb89fd..f0c7cfb38 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -76,7 +76,7 @@ static inline void dwc2_remote_wakeup_delay(void) while ( count-- ) __asm volatile ("nop"); } -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { (void) core; (void) speed; diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index d2ad8abb7..5a0071563 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,7 +113,7 @@ static inline void dwc2_remote_wakeup_delay(void) } // Set turn-around timeout according to link speed -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { core->gusbcfg &= ~GUSBCFG_TRDT; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index b83ac67f9..23d724366 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -134,11 +134,11 @@ union { //------------- Device OUT Endpoint -------------// -} dwc2_core_t; +} dwc2_regs_t; -TU_VERIFY_STATIC(offsetof(dwc2_core_t, hcfg ) == 0x0400, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_core_t, channel) == 0x0500, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_core_t, dcfg ) == 0x0800, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); // Endpoint IN typedef struct