In some STM32H7 BSP variants, initialized RCC_PeriphCLKInitStruct instances as empty

This commit is contained in:
Brandon Alba 2023-02-28 10:31:07 -08:00
parent 787afbbcd0
commit 8c8f26f14e
2 changed files with 2 additions and 2 deletions

View File

@ -111,7 +111,7 @@ static inline void board_stm32h7_clock_init(void)
separate. However, the main system PLL (PLL1) doesn't have a direct separate. However, the main system PLL (PLL1) doesn't have a direct
connection to the USB peripheral clock to generate 48 MHz, so we do this connection to the USB peripheral clock to generate 48 MHz, so we do this
dance. This will connect PLL1's Q output to the USB peripheral clock. */ dance. This will connect PLL1's Q output to the USB peripheral clock. */
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;

View File

@ -102,7 +102,7 @@ static inline void board_stm32h7_clock_init(void)
separate. However, the main system PLL (PLL1) doesn't have a direct separate. However, the main system PLL (PLL1) doesn't have a direct
connection to the USB peripheral clock to generate 48 MHz, so we do this connection to the USB peripheral clock to generate 48 MHz, so we do this
dance. This will connect PLL1's Q output to the USB peripheral clock. */ dance. This will connect PLL1's Q output to the USB peripheral clock. */
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;