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add PORT selection for makefile

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hathach 2023-07-07 16:24:22 +07:00
parent e0f1ba8b0e
commit 88478a9d05
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4 changed files with 20 additions and 1 deletions
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3
hw/bsp/ra/boards/ra6m5_ek/board.mk
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@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5
# For flash-jlink target # For flash-jlink target
JLINK_DEVICE = R7FA6M5BH JLINK_DEVICE = R7FA6M5BH
# Port 1 is highspeed
PORT ?= 1
flash: flash-jlink flash: flash-jlink

2
hw/bsp/ra/family.cmake
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@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
set(FAMILY_MCUS RA CACHE INTERNAL "") set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
#------------------------------------ #------------------------------------
# BOARD_TARGET # BOARD_TARGET

12
hw/bsp/ra/family.mk
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@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
FSP_RA = hw/mcu/renesas/fsp/ra/fsp FSP_RA = hw/mcu/renesas/fsp/ra/fsp
include $(TOP)/$(BOARD_PATH)/board.mk include $(TOP)/$(BOARD_PATH)/board.mk
# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
PORT ?= 0
CFLAGS += \ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_RAXXX \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
-DBOARD_TUD_RHPORT=$(PORT) \
-Wno-error=undef \ -Wno-error=undef \
-Wno-error=strict-prototypes \ -Wno-error=strict-prototypes \
-Wno-error=cast-align \ -Wno-error=cast-align \
@ -15,6 +19,14 @@ CFLAGS += \
-nostartfiles \ -nostartfiles \
-ffreestanding -ffreestanding
ifeq ($(PORT), 1)
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
$(info "Using PORT 1 HighSpeed")
else
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
$(info "Using PORT 0 FullSpeed")
endif
SRC_C += \ SRC_C += \
src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/dcd_rusb2.c \
src/portable/renesas/rusb2/hcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \

4
src/portable/renesas/rusb2/dcd_rusb2.c
View File

@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
// Highspeed FIFO is 32-bit // Highspeed FIFO is 32-bit
if ( is_highspeed_regbase(rusb) ) { if ( is_highspeed_regbase(rusb) ) {
// TODO 32-bit access for better performance
ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2); ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3); ff8 = (volatile uint8_t *) ((uintptr_t) fifo+3);
}else { }else {
@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len) static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
{ {
(void) rusb; (void) rusb;
// TODO 16/32-bit access for better performance
uint8_t *p = (uint8_t*)buf; uint8_t *p = (uint8_t*)buf;
volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */
while (len--) *p++ = *reg; while (len--) *p++ = *reg;