mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
esp32p4 use port0 as fs, port1 as highspeed
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parent
67e5577b42
commit
87f1993304
16
.idea/cmake.xml
generated
16
.idea/cmake.xml
generated
@ -37,7 +37,7 @@
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</envs>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</configuration>
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<configuration PROFILE_NAME="espressif_s3_devkitc" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitc -DLOG=1">
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<configuration PROFILE_NAME="espressif_s3_devkitc" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitc -DLOG=1">
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<ADDITIONAL_GENERATION_ENVIRONMENT>
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<envs>
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<env name="ESPBAUD" value="1500000" />
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@ -65,6 +65,13 @@
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</envs>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</configuration>
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<configuration PROFILE_NAME="espressif_p4_function_ev" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_p4_function_ev -DLOG=1">
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<ADDITIONAL_GENERATION_ENVIRONMENT>
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<envs>
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<env name="ESPBAUD" value="1500000" />
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</envs>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</configuration>
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<configuration PROFILE_NAME="feather_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
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<configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
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<configuration PROFILE_NAME="feather_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=1 -DLOGGER=RTT -DMAX3421_HOST=1" />
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@ -145,13 +152,6 @@
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<configuration PROFILE_NAME="max32650fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32650fthr -DLOG=0 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="max32666fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32666fthr -DLOG=0 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="max32690evkit" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32690evkit -DLOG=1 -DLOGGER=RTT" />
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<configuration PROFILE_NAME="espressif_p4_function_ev" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_p4_function_ev -DLOG=1">
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<ADDITIONAL_GENERATION_ENVIRONMENT>
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<envs>
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<env name="ESPBAUD" value="1500000" />
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</envs>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</configuration>
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</configurations>
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</component>
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</project>
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@ -4,5 +4,3 @@ idf_component_register(SRCS family.c
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INCLUDE_DIRS "." ${BOARD} ${hw_dir}
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PRIV_REQUIRES driver usb
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REQUIRES led_strip src tinyusb_src)
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target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
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@ -9,6 +9,9 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu)
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list(APPEND compile_definitions
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CFG_TUSB_MCU=${tusb_mcu}
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CFG_TUSB_OS=OPT_OS_FREERTOS
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# EXAMPLE port selection: port0 is fullspeed, port1 is highspeed
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BOARD_TUD_RHPORT=${TUD_PORT}
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BOARD_TUD_MAX_SPEED=$<IF:${TUD_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
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)
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list(APPEND srcs
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@ -2,9 +2,17 @@ cmake_minimum_required(VERSION 3.5)
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# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
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include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
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string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
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# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed)
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if (NOT DEFINED TUD_PORT)
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if (IDF_TARGET STREQUAL "esp32p4")
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set(TUD_PORT 1)
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else ()
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set(TUD_PORT 0)
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endif ()
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endif()
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# Add example src and bsp directories
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set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
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@ -31,6 +31,9 @@
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#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
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// Debug level for DWC2
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#define DWC2_DEBUG 2
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#include "device/dcd.h"
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#include "dwc2_type.h"
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@ -57,16 +60,25 @@
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#error "Unsupported MCUs"
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#endif
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enum {
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DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
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};
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// DWC2 registers
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//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
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TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
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if (rhport >= DWC2_CONTROLLER_COUNT) {
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// user mis-configured, ignore and use first controller
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rhport = 0;
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}
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return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
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}
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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// DWC2 registers
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#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
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// Debug level for DWC2
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#define DWC2_DEBUG 2
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static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
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typedef struct {
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@ -584,7 +596,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
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// Set 16-bit interface if supported
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if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
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if (dwc2->ghwcfg4_bm.phy_data_width) {
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gusbcfg |= GUSBCFG_PHYIF16;
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}
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}
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// Apply config
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@ -621,7 +635,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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}
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static bool check_dwc2(dwc2_regs_t* dwc2) {
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#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1
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#if CFG_TUSB_DEBUG >= DWC2_DEBUG
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// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
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// Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports
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volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
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@ -39,50 +39,36 @@
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#include "soc/usb_wrap_struct.h"
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#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
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#define DWC2_PERIPH_COUNT 1
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#define DWC2_FS_REG_BASE 0x60080000UL
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#define DWC2_EP_MAX 7
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#define DWC2_FS_REG_BASE 0x60080000UL
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#define DWC2_EP_MAX 7
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static const dwc2_controller_t _dwc2_controller[] = {
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{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
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};
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#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
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#define DWC2_PERIPH_COUNT 2
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#define DWC2_FS_REG_BASE 0x50040000UL
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#define DWC2_HS_REG_BASE 0x50000000UL
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#define DWC2_EP_MAX 16
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#define DWC2_FS_REG_BASE 0x50040000UL
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#define DWC2_HS_REG_BASE 0x50000000UL
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#define DWC2_EP_MAX 16
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// On ESP32 for consistency we associate
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// - Port0 to OTG_FS, and Port1 to OTG_HS
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static const dwc2_controller_t _dwc2_controller[] = {
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{
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.reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8,
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.ep_fifo_size = 4096
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},
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{
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.reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5,
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.ep_fifo_size = 1024
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}
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{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
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{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
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};
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#endif
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enum {
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DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
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};
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static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT];
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static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)];
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static void dcd_int_handler_wrap(void* arg) {
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const uint8_t rhport = (uint8_t) arg;
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const uint8_t rhport = (uint8_t)(uintptr_t) arg;
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dcd_int_handler(rhport);
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}
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
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esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
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dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]);
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dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]);
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}
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
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@ -97,7 +83,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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(void)dwc2;
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(void)hs_phy_type;
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// nothing to do
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}
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@ -105,7 +90,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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(void)dwc2;
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(void)hs_phy_type;
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// nothing to do
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}
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