mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-14 18:40:37 +00:00
ground works for hcd max3421e
This commit is contained in:
parent
9257a0f562
commit
824e585e2b
@ -1,6 +1,6 @@
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set(MCU_VARIANT nrf52840)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
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# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
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#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
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set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
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function(update_board TARGET)
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endfunction()
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@ -45,6 +45,13 @@
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#define UART_RX_PIN 24
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#define UART_TX_PIN 25
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// SPI for USB host shield
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#define SPI_SCK_PIN 14
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#define SPI_MOSI_PIN 13
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#define SPI_MISO_PIN 15
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#define SPI_CS_PIN 27
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#define MAX3241E_INT_PIN 26
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#ifdef __cplusplus
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}
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#endif
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@ -40,6 +40,7 @@
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#include "hal/nrf_gpio.h"
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#include "drivers/include/nrfx_power.h"
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#include "drivers/include/nrfx_uarte.h"
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#include "drivers/include/nrfx_spim.h"
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#ifdef SOFTDEVICE_PRESENT
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#include "nrf_sdm.h"
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@ -54,8 +55,7 @@
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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//--------------------------------------------------------------------+
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void USBD_IRQHandler(void)
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{
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void USBD_IRQHandler(void) {
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tud_int_handler(0);
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}
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@ -81,6 +81,7 @@ enum {
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#endif
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static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
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static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
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// tinyusb function that handles power event (detected, ready, removed)
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// We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
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@ -88,13 +89,11 @@ extern void tusb_hal_nrf_power_event(uint32_t event);
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// nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
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TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
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{
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TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
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tusb_hal_nrf_power_event((uint32_t) event);
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}
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void board_init(void)
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{
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void board_init(void) {
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// stop LF clock just in case we jump from application without reset
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NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
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@ -113,8 +112,7 @@ void board_init(void)
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SysTick_Config(SystemCoreClock/1000);
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// UART
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nrfx_uarte_config_t uart_cfg =
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{
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nrfx_uarte_config_t uart_cfg = {
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.pseltxd = UART_TX_PIN,
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.pselrxd = UART_RX_PIN,
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.pselcts = NRF_UARTE_PSEL_DISCONNECTED,
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@ -175,45 +173,78 @@ void board_init(void)
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if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
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if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY);
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#endif
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(void) _spi;
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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// USB host using max3421e usb controller via SPI
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nrfx_spim_config_t cfg = {
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.sck_pin = SPI_SCK_PIN,
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.mosi_pin = SPI_MOSI_PIN,
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.miso_pin = SPI_MISO_PIN,
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.ss_pin = SPI_CS_PIN,
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.ss_active_high = false,
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.irq_priority = 3,
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.orc = 0xFF,
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// default setting 4 Mhz, Mode 0, MSB first
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.frequency = NRF_SPIM_FREQ_4M,
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.mode = NRF_SPIM_MODE_0,
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.bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST,
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};
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// no handler --> blocking
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nrfx_spim_init(&_spi, &cfg, NULL, NULL);
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#endif
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}
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//--------------------------------------------------------------------+
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// Board porting API
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//--------------------------------------------------------------------+
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void board_led_write(bool state)
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{
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nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
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void board_led_write(bool state) {
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nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
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}
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uint32_t board_button_read(void)
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{
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uint32_t board_button_read(void) {
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return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
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}
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int board_uart_read(uint8_t* buf, int len)
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{
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(void) buf; (void) len;
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int board_uart_read(uint8_t *buf, int len) {
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(void) buf;
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(void) len;
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return 0;
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// return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
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}
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int board_uart_write(void const * buf, int len)
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{
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return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
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int board_uart_write(void const *buf, int len) {
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return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
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}
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#if CFG_TUSB_OS == OPT_OS_NONE
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volatile uint32_t system_ticks = 0;
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void SysTick_Handler (void)
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{
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void SysTick_Handler(void) {
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system_ticks++;
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}
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uint32_t board_millis(void)
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{
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uint32_t board_millis(void) {
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return system_ticks;
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}
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#endif
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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// API: SPI transfer with MAX3421E, must be implemented by application
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bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
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(void) rhport;
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nrfx_spim_xfer_desc_t xfer = {
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.p_tx_buffer = tx_buf,
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.tx_length = tx_len,
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.p_rx_buffer = rx_buf,
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.rx_length = rx_len,
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};
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return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
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}
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#endif
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#ifdef SOFTDEVICE_PRESENT
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@ -251,8 +282,7 @@ void SD_EVT_IRQHandler(void)
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}
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}
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void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
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{
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void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
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(void) id;
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(void) pc;
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(void) info;
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@ -122,7 +122,7 @@ function(family_configure_example TARGET RTOS)
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family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
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#${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
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${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
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)
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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@ -9,9 +9,8 @@
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#define NRFX_UARTE_ENABLED 1
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#define NRFX_UARTE0_ENABLED 1
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#define NRFX_UARTE1_ENABLED 0
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#define NRFX_UARTE2_ENABLED 0
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#define NRFX_UARTE3_ENABLED 0
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#define NRFX_SPIM_ENABLED 1
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#define NRFX_SPIM0_ENABLED 1
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#define NRFX_PRS_ENABLED 0
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#define NRFX_USBREG_ENABLED 1
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src/portable/analog/max3421e/hcd_max3421e.c
Normal file
302
src/portable/analog/max3421e/hcd_max3421e.c
Normal file
@ -0,0 +1,302 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
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#include "host/hcd.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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// Command format is
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// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
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enum {
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CMDBYTE_WRITE = 0x02,
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};
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enum {
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RCVVFIFO_ADDR = 1u << 3, // 0x08
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SNDFIFO_ADDR = 2u << 3, // 0x10
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SUDFIFO_ADDR = 4u << 3, // 0x20
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RCVBC_ADDR = 6u << 3, // 0x30
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SNDBC_ADDR = 7u << 3, // 0x38
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USBIRQ_ADDR = 13u << 3, // 0x68
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USBIEN_ADDR = 14u << 3, // 0x70
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USBCTL_ADDR = 15u << 3, // 0x78
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CPUCTL_ADDR = 16u << 3, // 0x80
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PINCTL_ADDR = 17u << 3, // 0x88
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REVISION_ADDR = 18u << 3, // 0x90
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HIRQ_ADDR = 25u << 3, // 0xC8
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HIEN_ADDR = 26u << 3, // 0xD0
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MODE_ADDR = 27u << 3, // 0xD8
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PERADDR_ADDR = 28u << 3, // 0xE0
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HCTL_ADDR = 29u << 3, // 0xE8
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HXFR_ADDR = 30u << 3, // 0xF0
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HRSL_ADDR = 31u << 3, // 0xF8
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};
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enum {
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USBIRQ_OSCOK_IRQ = 1u << 0,
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USBIRQ_NOVBUS_IRQ = 1u << 5,
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USBIRQ_VBUS_IRQ = 1u << 6,
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};
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enum {
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USBCTL_PWRDOWN = 1u << 4,
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USBCTL_CHIPRES = 1u << 5,
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};
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enum {
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CPUCTL_IE = 1u << 0,
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CPUCTL_PULSEWID0 = 1u << 6,
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CPUCTL_PULSEWID1 = 1u << 7,
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};
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enum {
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PINCTL_GPXA = 1u << 0,
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PINCTL_GPXB = 1u << 1,
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PINCTL_POSINT = 1u << 2,
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PINCTL_INTLEVEL = 1u << 3,
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PINCTL_FDUPSPI = 1u << 4,
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};
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enum {
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HIRQ_BUSEVENT_IRQ = 1u << 0,
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HIRQ_RWU_IRQ = 1u << 1,
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HIRQ_RCVDAV_IRQ = 1u << 2,
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HIRQ_SNDBAV_IRQ = 1u << 3,
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HIRQ_SUSDN_IRQ = 1u << 4,
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HIRQ_CONDET_IRQ = 1u << 5,
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HIRQ_FRAME_IRQ = 1u << 6,
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HIRQ_HXFRDN_IRQ = 1u << 7,
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};
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enum {
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MODE_HOST = 1u << 0,
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MODE_LOWSPEED = 1u << 1,
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MODE_HUBPRE = 1u << 2,
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MODE_SOFKAENAB = 1u << 3,
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MODE_SEPIRQ = 1u << 4,
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MODE_DELAYISO = 1u << 5,
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MODE_DMPULLDN = 1u << 6,
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MODE_DPPULLDN = 1u << 7,
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};
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enum {
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HCTL_BUSRST = 1u << 1,
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HCTL_FRMRST = 1u << 2,
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HCTL_SAMPLEBUS = 1u << 3,
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HCTL_SIGRSM = 1u << 4,
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HCTL_RCVTOG0 = 1u << 5,
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HCTL_RCVTOG1 = 1u << 6,
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HCTL_SNDTOG0 = 1u << 7,
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HCTL_SNDTOG1 = 1u << 8,
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};
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enum {
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HXFR_EPNUM_MASK = 0x0f,
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HXFR_SETUP = 1u << 4,
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HXFR_OUT_NIN = 1u << 5,
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HXFR_ISO = 1u << 6,
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HXFR_HS = 1u << 7,
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};
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enum {
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HRSL_RESULT_MASK = 0x0f,
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HRSL_RCVTOGRD = 1u << 4,
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HRSL_SNDTOGRD = 1u << 5,
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HRSL_KSTATUS = 1u << 6,
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HRSL_JSTATUS = 1u << 7,
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};
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// API: SPI transfer with MAX3421E, must be implemented by application
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bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
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// return HIRQ register since we are in full-duplex mode
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static uint8_t reg_write(uint8_t reg, uint8_t data) {
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uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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return rx_buf[0];
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}
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static uint8_t reg_read(uint8_t reg) {
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uint8_t tx_buf[2] = {reg, 0};
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uint8_t rx_buf[2] = {0, 0};
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return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
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}
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//--------------------------------------------------------------------+
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// Controller API
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//--------------------------------------------------------------------+
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// optional hcd configuration, called by tuh_configure()
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bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
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(void) rhport;
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(void) cfg_id;
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(void) cfg_param;
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return false;
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}
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// Initialize controller to host mode
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bool hcd_init(uint8_t rhport) {
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(void) rhport;
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// full duplex, interrupt level (should be configurable)
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reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
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// reset
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reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
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reg_write(USBCTL_ADDR, 0);
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while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
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// wait for oscillator to stabilize
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}
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// Mode: Host and DP/DM pull down
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reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
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// Connection detection
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reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
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return false;
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}
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// Interrupt Handler
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void hcd_int_handler(uint8_t rhport) {
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(void) rhport;
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}
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// Enable USB interrupt
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void hcd_int_enable (uint8_t rhport) {
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(void) rhport;
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}
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// Disable USB interrupt
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void hcd_int_disable(uint8_t rhport) {
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(void) rhport;
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}
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// Get frame number (1ms)
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uint32_t hcd_frame_number(uint8_t rhport) {
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(void) rhport;
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return 0;
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}
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//--------------------------------------------------------------------+
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// Port API
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//--------------------------------------------------------------------+
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// Get the current connect status of roothub port
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bool hcd_port_connect_status(uint8_t rhport) {
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(void) rhport;
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return false;
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}
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// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
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// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
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void hcd_port_reset(uint8_t rhport) {
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(void) rhport;
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}
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// Complete bus reset sequence, may be required by some controllers
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void hcd_port_reset_end(uint8_t rhport) {
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(void) rhport;
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}
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// Get port link speed
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tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
|
||||
return TUSB_SPEED_FULL;
|
||||
}
|
||||
|
||||
// HCD closes all opened endpoints belong to this device
|
||||
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoints API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Open an endpoint
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_desc;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
(void) buffer;
|
||||
(void) buflen;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Abort a queued transfer. Note: it can only abort transfer that has not been started
|
||||
// Return true if a queued transfer is aborted, false if there is no transfer to abort
|
||||
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) setup_packet;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// clear stall, data toggle is also reset to DATA0
|
||||
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
Loading…
x
Reference in New Issue
Block a user