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add default CFG_TUH_MAX3421 = 0, default spi speed for samd21/samd51 to 12Mhz

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hathach 2023-09-18 22:15:31 +07:00
parent 46f7cf4da2
commit 81cd995108
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GPG Key ID: F5D50C6D51D17CBA
4 changed files with 25 additions and 13 deletions
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3
hw/bsp/samd21/family.c
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@ -269,7 +269,8 @@ uint32_t board_millis(void) {
static void max3421_init(void) { static void max3421_init(void) {
//------------- SPI Init -------------// //------------- SPI Init -------------//
uint32_t const baudrate = 4000000u; // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
uint32_t const baudrate = 12000000u;
// Enable the APB clock for SERCOM // Enable the APB clock for SERCOM
PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID); PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);

11
hw/bsp/samd51/family.c
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@ -183,7 +183,9 @@ uint32_t board_millis(void) {
static void max3421_init(void) { static void max3421_init(void) {
//------------- SPI Init -------------// //------------- SPI Init -------------//
uint32_t const baudrate = 4000000u;
// MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
uint32_t const baudrate = 12000000u;
struct { struct {
volatile uint32_t *mck_apb; volatile uint32_t *mck_apb;
@ -229,7 +231,12 @@ static void max3421_init(void) {
while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1); while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
// Set the baud rate // Set the baud rate
sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1); uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
if (baud_reg) {
baud_reg--;
}
sercom->SPI.BAUD.reg = baud_reg;
// Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom) // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT); gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);

2
src/portable/analog/max3421/hcd_max3421.c
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@ -263,7 +263,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
max3421_spi_lock(rhport, in_isr); max3421_spi_lock(rhport, in_isr);
tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0); tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
_hcd_data.hirq = hirq; _hcd_data.hirq = hirq;
tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len); tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);

22
src/tusb_option.h
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@ -424,11 +424,11 @@
//------------- CLASS -------------// //------------- CLASS -------------//
#ifndef CFG_TUH_HUB #ifndef CFG_TUH_HUB
#define CFG_TUH_HUB 0 #define CFG_TUH_HUB 0
#endif #endif
#ifndef CFG_TUH_CDC #ifndef CFG_TUH_CDC
#define CFG_TUH_CDC 0 #define CFG_TUH_CDC 0
#endif #endif
#ifndef CFG_TUH_CDC_FTDI #ifndef CFG_TUH_CDC_FTDI
@ -442,34 +442,38 @@
#endif #endif
#ifndef CFG_TUH_HID #ifndef CFG_TUH_HID
#define CFG_TUH_HID 0 #define CFG_TUH_HID 0
#endif #endif
#ifndef CFG_TUH_MIDI #ifndef CFG_TUH_MIDI
#define CFG_TUH_MIDI 0 #define CFG_TUH_MIDI 0
#endif #endif
#ifndef CFG_TUH_MSC #ifndef CFG_TUH_MSC
#define CFG_TUH_MSC 0 #define CFG_TUH_MSC 0
#endif #endif
#ifndef CFG_TUH_VENDOR #ifndef CFG_TUH_VENDOR
#define CFG_TUH_VENDOR 0 #define CFG_TUH_VENDOR 0
#endif #endif
#ifndef CFG_TUH_API_EDPT_XFER #ifndef CFG_TUH_API_EDPT_XFER
#define CFG_TUH_API_EDPT_XFER 0 #define CFG_TUH_API_EDPT_XFER 0
#endif #endif
// Enable PIO-USB software host controller // Enable PIO-USB software host controller
#ifndef CFG_TUH_RPI_PIO_USB #ifndef CFG_TUH_RPI_PIO_USB
#define CFG_TUH_RPI_PIO_USB 0 #define CFG_TUH_RPI_PIO_USB 0
#endif #endif
#ifndef CFG_TUD_RPI_PIO_USB #ifndef CFG_TUD_RPI_PIO_USB
#define CFG_TUD_RPI_PIO_USB 0 #define CFG_TUD_RPI_PIO_USB 0
#endif #endif
// MAX3421 Host controller option
#ifndef CFG_TUH_MAX3421
#define CFG_TUH_MAX3421 0
#endif
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// TypeC Options (Default) // TypeC Options (Default)