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more constant rename clean up
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hathach
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@ -49,6 +49,41 @@
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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// ENDPTCTRL
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enum {
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ENDPTCTRL_STALL = TU_BIT(0),
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ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
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ENDPTCTRL_TOGGLE_RESET = TU_BIT(6),
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ENDPTCTRL_ENABLE = TU_BIT(7)
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};
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// USBCMD
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enum {
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USBCMD_RUN_STOP = TU_BIT(0),
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USBCMD_RESET = TU_BIT(1),
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USBCMD_SETUP_TRIPWIRE = TU_BIT(13),
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USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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};
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// Interrupt Threshold bit 23:16
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// USBSTS, USBINTR
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enum {
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INTR_USB = TU_BIT(0),
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INTR_ERROR = TU_BIT(1),
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INTR_PORT_CHANGE = TU_BIT(2),
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INTR_RESET = TU_BIT(6),
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INTR_SOF = TU_BIT(7),
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INTR_SUSPEND = TU_BIT(8),
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INTR_NAK = TU_BIT(16)
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};
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// PORTSC
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enum {
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PORTSC_CURRENT_CONNECT_STATUS = TU_BIT(0),
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PORTSC_FORCE_PORT_RESUME = TU_BIT(6),
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PORTSC_SUSPEND = TU_BIT(7)
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};
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// Device Register starting with CAPLENGTH offset
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typedef struct
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{
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@ -95,41 +130,7 @@ typedef struct
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} dcd_registers_t;
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/*---------- ENDPTCTRL ----------*/
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enum {
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ENDPTCTRL_MASK_STALL = TU_BIT(0),
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ENDPTCTRL_MASK_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
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ENDPTCTRL_MASK_TOGGLE_RESET = TU_BIT(6),
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ENDPTCTRL_MASK_ENABLE = TU_BIT(7)
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};
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/*---------- USBCMD ----------*/
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enum {
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USBCMD_MASK_RUN_STOP = TU_BIT(0),
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USBCMD_MASK_RESET = TU_BIT(1),
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USBCMD_MASK_SETUP_TRIPWIRE = TU_BIT(13),
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USBCMD_MASK_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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};
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// Interrupt Threshold bit 23:16
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/*---------- USBSTS, USBINTR ----------*/
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enum {
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INT_MASK_USB = TU_BIT(0),
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INT_MASK_ERROR = TU_BIT(1),
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INT_MASK_PORT_CHANGE = TU_BIT(2),
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INT_MASK_RESET = TU_BIT(6),
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INT_MASK_SOF = TU_BIT(7),
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INT_MASK_SUSPEND = TU_BIT(8),
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INT_MASK_NAK = TU_BIT(16)
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};
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//------------- PORTSC -------------//
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enum {
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PORTSC_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
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PORTSC_FORCE_PORT_RESUME_MASK = TU_BIT(6),
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PORTSC_SUSPEND_MASK = TU_BIT(7)
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};
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// Queue Transfer Descriptor
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typedef struct
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{
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// Word 0: Next QTD Pointer
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@ -159,6 +160,7 @@ typedef struct
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TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
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// Queue Head
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typedef struct
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{
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// Word 0: Capabilities and Characteristics
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@ -258,7 +260,7 @@ void dcd_init(uint8_t rhport)
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lpc_usb->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
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lpc_usb->USBSTS = lpc_usb->USBSTS;
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lpc_usb->USBINTR = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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lpc_usb->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND | INTR_SOF;
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lpc_usb->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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lpc_usb->USBCMD |= TU_BIT(0); // connect
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@ -329,7 +331,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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@ -338,8 +340,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// data toggle also need to be reset
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_regs[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_regs[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -363,7 +365,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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// Enable EP Control
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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dcd_regs[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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@ -409,15 +411,15 @@ void dcd_isr(uint8_t rhport)
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if (int_status == 0) return;// disabled interrupt sources
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if (int_status & INT_MASK_RESET)
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if (int_status & INTR_RESET)
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{
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bus_reset(rhport);
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dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
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}
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if (int_status & INT_MASK_SUSPEND)
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if (int_status & INTR_SUSPEND)
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{
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if (lpc_usb->PORTSC1 & PORTSC_SUSPEND_MASK)
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if (lpc_usb->PORTSC1 & PORTSC_SUSPEND)
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{
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// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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@ -428,16 +430,16 @@ void dcd_isr(uint8_t rhport)
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}
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// TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INT_MASK_PORT_CHANGE)
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// if (int_status & INTR_PORT_CHANGE)
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// {
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// if ( !(lpc_usb->PORTSC1 & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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// if ( !(lpc_usb->PORTSC1 & PORTSC_CURRENT_CONNECT_STATUS) )
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// {
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// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
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// dcd_event_handler(&event, true);
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// }
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// }
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if (int_status & INT_MASK_USB)
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if (int_status & INTR_USB)
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{
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uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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@ -470,13 +472,13 @@ void dcd_isr(uint8_t rhport)
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}
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}
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if (int_status & INT_MASK_SOF)
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if (int_status & INTR_SOF)
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{
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dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
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}
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if (int_status & INT_MASK_NAK) {}
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if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
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if (int_status & INTR_NAK) {}
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if (int_status & INTR_ERROR) TU_ASSERT(false, );
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}
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#endif
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