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https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
more musb update
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fe7ffc8eda
commit
76eb2f5066
@ -643,8 +643,7 @@ void dcd_sof_enable(uint8_t rhport, bool en)
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//--------------------------------------------------------------------+
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// Configure endpoint's registers according to descriptor
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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{
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
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const unsigned ep_addr = ep_desc->bEndpointAddress;
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const unsigned epn = tu_edpt_number(ep_addr);
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const unsigned dir_in = tu_edpt_dir(ep_addr);
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@ -662,22 +661,30 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
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const uint8_t is_rx = 1 - dir_in;
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ep_csr->maxp_csr[is_rx].maxp = mps;
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ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0;
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musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx];
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maxp_csr->maxp = mps;
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maxp_csr->csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0;
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// flush and reset data toggle
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uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx);
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if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
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if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
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csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx);
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}
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ep_csr->maxp_csr[is_rx].csrl = csrl;
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maxp_csr->csrl = csrl;
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musb->intren_ep[is_rx] |= TU_BIT(epn);
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/* Setup FIFO */
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fifo_configure(musb, epn, dir_in, mps);
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return true;
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}
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// bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
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// }
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//
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// bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
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// }
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void dcd_edpt_close_all(uint8_t rhport)
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{
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musb_regs_t* musb = MUSB_REGS(rhport);
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@ -688,23 +695,20 @@ void dcd_edpt_close_all(uint8_t rhport)
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musb->intr_rxen = 0;
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for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
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musb_ep_csr_t* ep_csr = get_ep_csr(musb, i);
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ep_csr->tx_maxp = 0;
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ep_csr->tx_csrh = 0;
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if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY)
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ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH;
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else
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ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT;
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for (unsigned d = 0; d < 2; d++) {
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musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[d];
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maxp_csr->maxp = 0;
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maxp_csr->csrh = 0;
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ep_csr->rx_maxp = 0;
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ep_csr->rx_csrh = 0;
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if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) {
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ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH;
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} else {
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ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT;
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// flush and reset data toggle
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uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(d);
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if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
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csrl |= MUSB_CSRL_FLUSH_FIFO(d);
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}
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maxp_csr->csrl = csrl;
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fifo_reset(musb, i, 1-d);
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}
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fifo_reset(musb, i, 0);
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fifo_reset(musb, i, 1);
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}
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#if MUSB_CFG_DYNAMIC_FIFO
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@ -755,12 +759,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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unsigned const epnum = tu_edpt_number(ep_addr);
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unsigned const ie = musb_dcd_get_int_enable(rhport);
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musb_dcd_int_disable(rhport);
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if (epnum) {
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_dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
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ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
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} else {
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ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
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}
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if (ie) musb_dcd_int_enable(rhport);
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return ret;
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}
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@ -783,11 +789,13 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
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// Stall endpoint
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
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unsigned const epn = tu_edpt_number(ep_addr);
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unsigned const ie = musb_dcd_get_int_enable(rhport);
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musb_dcd_int_disable(rhport);
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unsigned const epn = tu_edpt_number(ep_addr);
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musb_regs_t* musb_regs = MUSB_REGS(rhport);
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musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
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musb_dcd_int_disable(rhport);
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if (0 == epn) {
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if (!ep_addr) { /* Ignore EP80 */
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_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
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@ -795,13 +803,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
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ep_csr->csr0l = MUSB_CSRL0_STALL;
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}
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} else {
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if (tu_edpt_dir(ep_addr)) { /* IN */
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ep_csr->tx_csrl = MUSB_TXCSRL1_STALL;
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} else { /* OUT */
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TU_ASSERT(!(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY),);
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ep_csr->rx_csrl = MUSB_RXCSRL1_STALL;
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}
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const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
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ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_SEND_STALL(is_rx);
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}
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if (ie) musb_dcd_int_enable(rhport);
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}
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@ -809,16 +814,16 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void)rhport;
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unsigned const ie = musb_dcd_get_int_enable(rhport);
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musb_dcd_int_disable(rhport);
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unsigned const epn = tu_edpt_number(ep_addr);
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musb_regs_t* musb_regs = MUSB_REGS(rhport);
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musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
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unsigned const ie = musb_dcd_get_int_enable(rhport);
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musb_dcd_int_disable(rhport);
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if (tu_edpt_dir(ep_addr)) { /* IN */
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ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT;
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} else { /* OUT */
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ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT;
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}
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const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
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ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx);
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if (ie) musb_dcd_int_enable(rhport);
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}
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@ -47,18 +47,15 @@ static const IRQn_Type musb_irqs[] = {
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USB_IRQn
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};
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TU_ATTR_ALWAYS_INLINE
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static inline void musb_dcd_int_enable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) {
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NVIC_EnableIRQ(musb_irqs[rhport]);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void musb_dcd_int_disable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) {
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NVIC_DisableIRQ(musb_irqs[rhport]);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
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#ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5
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return NVIC_GetEnableIRQ(musb_irqs[rhport]);
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#else
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@ -67,8 +64,7 @@ static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
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#endif
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void musb_dcd_int_clear(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) {
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NVIC_ClearPendingIRQ(musb_irqs[rhport]);
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}
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@ -83,6 +83,12 @@
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#define __R volatile const
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#endif
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typedef struct TU_ATTR_PACKED {
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__IO uint16_t maxp; // 0x00, 0x04: MAXP
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__IO uint8_t csrl; // 0x02, 0x06: CSRL
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__IO uint8_t csrh; // 0x03, 0x07: CSRH
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}musb_ep_maxp_csr_t;
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// 0: TX (device IN, host OUT)
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// 1: RX (device OUT, host IN)
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typedef struct TU_ATTR_PACKED {
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@ -103,11 +109,7 @@ typedef struct TU_ATTR_PACKED {
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__IO uint8_t rx_csrh; // 0x07: RX CSRH
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};
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struct {
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__IO uint16_t maxp; // 0x00: MAXP
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__IO uint8_t csrl; // 0x02: CSRL
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__IO uint8_t csrh; // 0x03: CSRH
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}maxp_csr[2];
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musb_ep_maxp_csr_t maxp_csr[2];
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};
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union {
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@ -330,7 +332,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_
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#define MUSB_CSRL_PACKET_READY(_rx) (1u << 0)
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#define MUSB_CSRL_FLUSH_FIFO(_rx) (1u << ((_rx) ? 4 : 3))
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#define MUSB_CSRL_SEND_STALL(_rx) (1u << ((_rx) ? 5 : 4))
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#define MUSB_CSRL_SENT_STALL(_rx) (1u << ((_rx) ? 6 : 5))
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#define MUSB_CSRL_STALLED(_rx) (1u << ((_rx) ? 6 : 5))
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#define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6))
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// 0x13, 0x17: TX/RX CSRH
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