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Merge pull request #1491 from Ryzee119/ohci_fixes
OHCI usbh, tweaks and improvements
This commit is contained in:
Ha Thach
GitHub
commit
73afca14eb
@ -75,6 +75,21 @@
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#include "tusb_timeout.h" // TODO remove
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//--------------------------------------------------------------------+
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// Optional API implemented by application if needed
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// TODO move to a more ovious place/file
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//--------------------------------------------------------------------+
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// flush data cache
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TU_ATTR_WEAK extern void tusb_app_dcache_flush(uintptr_t addr, uint32_t data_size);
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// invalidate data cache
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TU_ATTR_WEAK extern void tusb_app_dcache_invalidate(uintptr_t addr, uint32_t data_size);
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// Optional physical <-> virtual address translation
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TU_ATTR_WEAK extern void* tusb_app_virt_to_phys(void *virt_addr);
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TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr);
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//--------------------------------------------------------------------+
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// Internal Inline Functions
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//--------------------------------------------------------------------+
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@ -28,8 +28,8 @@
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#define TUSB_MCU_H_
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//--------------------------------------------------------------------+
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// Port Specific
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// TUP stand for TinyUSB Port (can be renamed)
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// Port/Platform Specific
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// TUP stand for TinyUSB Port/Platform (can be renamed)
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//--------------------------------------------------------------------+
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//------------- Unaligned Memory Access -------------//
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@ -55,6 +55,7 @@
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#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
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#define TUP_DCD_ENDPOINT_MAX 16
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#define TUP_USBIP_OHCI
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#define TUP_OHCI_RHPORTS 2
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#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
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// TODO USB0 has 6, USB1 has 4
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@ -106,7 +106,7 @@ typedef struct
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// Controller API
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//--------------------------------------------------------------------+
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// optional hcd configuration, called by tuh_config()
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// optional hcd configuration, called by tuh_configure()
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bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK;
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// Initialize controller to host mode
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@ -35,6 +35,10 @@
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// TASK API
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//--------------------------------------------------------------------+
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#if CFG_TUH_ENABLED
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// currently only needed/available in host mode
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void osal_task_delay(uint32_t msec);
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#endif
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//--------------------------------------------------------------------+
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// Binary Semaphore API
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@ -28,6 +28,10 @@
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#if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI)
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#ifndef TUP_OHCI_RHPORTS
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#error OHCI is enabled, but TUP_OHCI_RHPORTS is not defined.
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#endif
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//--------------------------------------------------------------------+
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// INCLUDE
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//--------------------------------------------------------------------+
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@ -157,6 +161,21 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
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//--------------------------------------------------------------------+
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// USBH-HCD API
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//--------------------------------------------------------------------+
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// If your system requires separation of virtual and physical memory, implement
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// tusb_app_virt_to_phys and tusb_app_virt_to_phys in your application.
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TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address)
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{
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if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address);
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return virtual_address;
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}
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TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
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{
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if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address);
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return physical_address;
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}
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// Initialization according to 5.1.1.4
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bool hcd_init(uint8_t rhport)
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{
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@ -166,21 +185,43 @@ bool hcd_init(uint8_t rhport)
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tu_memclr(&ohci_data, sizeof(ohci_data_t));
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for(uint8_t i=0; i<32; i++)
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{ // assign all interrupt pointers to period head ed
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ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
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ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed);
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}
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ohci_data.control[0].ed.skip = 1;
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ohci_data.bulk_head_ed.skip = 1;
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ohci_data.period_head_ed.skip = 1;
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//If OHCI hardware is in SMM mode, gain ownership (Ref OHCI spec 5.1.1.3.3)
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if (OHCI_REG->control_bit.interrupt_routing == 1)
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{
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OHCI_REG->command_status_bit.ownership_change_request = 1;
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while (OHCI_REG->control_bit.interrupt_routing == 1) {}
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}
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//If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4)
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else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET &&
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OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL)
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{
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//Wait 20 ms. (Ref Usb spec 7.1.7.7)
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OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME;
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#if CFG_TUSB_OS != OPT_OS_NONE
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// os_none implement task delay using usb frame counter which is not started yet
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// therefore cause infinite delay.
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// TODO find a way to delay in case of os none e.g __nop
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osal_task_delay(20);
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#endif
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}
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// reset controller
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OHCI_REG->command_status_bit.controller_reset = 1;
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while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us
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//------------- init ohci registers -------------//
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OHCI_REG->control_head_ed = (uint32_t) &ohci_data.control[0].ed;
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OHCI_REG->bulk_head_ed = (uint32_t) &ohci_data.bulk_head_ed;
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OHCI_REG->hcca = (uint32_t) &ohci_data.hcca;
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OHCI_REG->control_head_ed = (uint32_t) _phys_addr(&ohci_data.control[0].ed);
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OHCI_REG->bulk_head_ed = (uint32_t) _phys_addr(&ohci_data.bulk_head_ed);
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OHCI_REG->hcca = (uint32_t) _phys_addr(&ohci_data.hcca);
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OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
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OHCI_REG->interrupt_status = OHCI_REG->interrupt_status; // clear current set bits
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@ -188,15 +229,21 @@ bool hcd_init(uint8_t rhport)
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OHCI_INT_UNRECOVERABLE_ERROR_MASK | OHCI_INT_FRAME_OVERFLOW_MASK | OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
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OHCI_INT_MASTER_ENABLE_MASK;
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OHCI_REG->control |= OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
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OHCI_REG->control = OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
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OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
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OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;
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OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated.
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OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval
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OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
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OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
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#if CFG_TUSB_OS != OPT_OS_NONE
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// TODO as above delay
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osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up
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#endif
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return true;
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}
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@ -212,8 +259,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
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//--------------------------------------------------------------------+
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void hcd_port_reset(uint8_t hostid)
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{
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(void) hostid;
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OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
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OHCI_REG->rhport_status[hostid] = RHPORT_PORT_RESET_STATUS_MASK;
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}
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void hcd_port_reset_end(uint8_t rhport)
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@ -223,14 +269,12 @@ void hcd_port_reset_end(uint8_t rhport)
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bool hcd_port_connect_status(uint8_t hostid)
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{
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(void) hostid;
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return OHCI_REG->rhport_status_bit[0].current_connect_status;
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return OHCI_REG->rhport_status_bit[hostid].current_connect_status;
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}
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tusb_speed_t hcd_port_speed_get(uint8_t hostid)
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{
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(void) hostid;
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return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
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return OHCI_REG->rhport_status_bit[hostid].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
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}
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// endpoints are tied to an address, which only reclaim after a long delay when enumerating
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@ -308,8 +352,8 @@ static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
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p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO;
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p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
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p_td->current_buffer_pointer = data_ptr;
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p_td->buffer_end = total_bytes ? (data_ptr + total_bytes-1) : data_ptr;
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p_td->current_buffer_pointer = _phys_addr(data_ptr);
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p_td->buffer_end = total_bytes ? (_phys_addr(data_ptr + total_bytes - 1)) : (uint8_t *)p_td->current_buffer_pointer;
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}
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static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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@ -345,7 +389,7 @@ static ohci_ed_t * ed_find_free(void)
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static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
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{
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p_ed->next = p_pre->next;
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p_pre->next = (uint32_t) p_ed;
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p_pre->next = (uint32_t) _phys_addr(p_ed);
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}
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static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
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@ -354,20 +398,24 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
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while( p_prev->next )
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{
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ohci_ed_t* ed = (ohci_ed_t*) p_prev->next;
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ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
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if (ed->dev_addr == dev_addr)
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{
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// unlink ed
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// Prevent Host Controller from processing this ED while we remove it
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ed->skip = 1;
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// unlink ed, will also move up p_prev
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p_prev->next = ed->next;
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// point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
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ed->next = (uint32_t) p_head;
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ed->next = (uint32_t) _phys_addr(p_head);
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ed->used = 0;
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ed->skip = 0;
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}else
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{
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p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
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}
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// check next valid since we could remove it
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if (p_prev->next) p_prev = (ohci_ed_t*) p_prev->next;
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}
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}
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@ -386,11 +434,11 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
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// tail is always NULL
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if ( tu_align16(p_ed->td_head.address) == 0 )
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{ // TD queue is empty --> head = TD
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p_ed->td_head.address |= (uint32_t) p_gtd;
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p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd);
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}
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else
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{ // TODO currently only support queue up to 2 TD each endpoint at a time
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((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
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((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd);
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}
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}
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@ -443,10 +491,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
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qtd->index = dev_addr;
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qtd->pid = PID_SETUP;
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qtd->data_toggle = GTD_DT_DATA0;
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qtd->delay_interrupt = 0;
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qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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//------------- Attach TDs list to Control Endpoint -------------//
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ed->td_head.address = (uint32_t) qtd;
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ed->td_head.address = (uint32_t) _phys_addr(qtd);
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OHCI_REG->command_status_bit.control_list_filled = 1;
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@ -470,9 +518,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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gtd->index = dev_addr;
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gtd->pid = dir ? PID_IN : PID_OUT;
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gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
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gtd->delay_interrupt = 0;
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gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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ed->td_head.address = (uint32_t) gtd;
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ed->td_head.address = (uint32_t) _phys_addr(gtd);
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OHCI_REG->command_status_bit.control_list_filled = 1;
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}else
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@ -484,7 +532,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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gtd_init(gtd, buffer, buflen);
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gtd->index = ed-ohci_data.ed_pool;
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gtd->delay_interrupt = 0;
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gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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td_insert_to_ed(ed, gtd);
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@ -520,16 +568,17 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
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while(td_head != NULL)
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{
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td_head = _virt_addr(td_head);
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uint32_t next = td_head->next;
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// make current's item become reverse's first item
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td_head->next = (uint32_t) td_reverse_head;
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td_reverse_head = td_head;
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td_reverse_head = _phys_addr(td_head);
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td_head = (ohci_td_item_t*) next; // advance to next item
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}
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return td_reverse_head;
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return _virt_addr(td_reverse_head);
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}
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static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
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@ -565,6 +614,7 @@ static void done_queue_isr(uint8_t hostid)
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// done head is written in reversed order of completion --> need to reverse the done queue first
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ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
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ohci_data.hcca.done_head = 0;
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while( td_head != NULL )
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{
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@ -600,7 +650,7 @@ static void done_queue_isr(uint8_t hostid)
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hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
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}
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td_head = (ohci_td_item_t*) td_head->next;
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td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next);
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}
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}
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@ -611,6 +661,9 @@ void hcd_int_handler(uint8_t hostid)
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if (int_status == 0) return;
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// Disable MIE as per OHCI spec 5.3
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OHCI_REG->interrupt_disable = OHCI_INT_MASTER_ENABLE_MASK;
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// Frame number overflow
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if ( int_status & OHCI_INT_FRAME_OVERFLOW_MASK )
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{
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@ -620,29 +673,30 @@ void hcd_int_handler(uint8_t hostid)
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//------------- RootHub status -------------//
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if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
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{
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uint32_t const rhport_status = OHCI_REG->rhport_status[0] & RHPORT_ALL_CHANGE_MASK;
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// TODO dual port is not yet supported
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if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
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for (int i = 0; i < TUP_OHCI_RHPORTS; i++)
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{
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// TODO check if remote wake-up
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if ( OHCI_REG->rhport_status_bit[0].current_connect_status )
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uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK;
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if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
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{
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// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
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OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
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hcd_event_device_attach(hostid, true);
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}else
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{
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hcd_event_device_remove(hostid, true);
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// TODO check if remote wake-up
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if ( OHCI_REG->rhport_status_bit[i].current_connect_status )
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{
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// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
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OHCI_REG->rhport_status[i] = RHPORT_PORT_RESET_STATUS_MASK;
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hcd_event_device_attach(i, true);
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}else
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{
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hcd_event_device_remove(i, true);
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}
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}
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if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
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{
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}
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OHCI_REG->rhport_status[i] = rhport_status; // acknowledge all interrupt
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}
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if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
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{
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}
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OHCI_REG->rhport_status[0] = rhport_status; // acknowledge all interrupt
|
||||
}
|
||||
|
||||
//------------- Transfer Complete -------------//
|
||||
@ -652,6 +706,8 @@ void hcd_int_handler(uint8_t hostid)
|
||||
}
|
||||
|
||||
OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt
|
||||
|
||||
OHCI_REG->interrupt_enable = OHCI_INT_MASTER_ENABLE_MASK; // Enable MIE
|
||||
}
|
||||
//--------------------------------------------------------------------+
|
||||
// HELPER
|
||||
|
||||
@ -58,7 +58,9 @@ typedef struct {
|
||||
|
||||
TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
|
||||
|
||||
typedef struct {
|
||||
// common link item for gtd and itd for list travel
|
||||
// use as pointer only
|
||||
typedef struct TU_ATTR_ALIGNED(16) {
|
||||
uint32_t reserved[2];
|
||||
volatile uint32_t next;
|
||||
uint32_t reserved2;
|
||||
@ -230,8 +232,27 @@ typedef volatile struct
|
||||
uint32_t periodic_start;
|
||||
uint32_t lowspeed_threshold;
|
||||
|
||||
uint32_t rh_descriptorA;
|
||||
uint32_t rh_descriptorB;
|
||||
union {
|
||||
uint32_t rh_descriptorA;
|
||||
struct {
|
||||
uint32_t number_downstream_ports : 8;
|
||||
uint32_t power_switching_mode : 1;
|
||||
uint32_t no_power_switching : 1;
|
||||
uint32_t device_type : 1;
|
||||
uint32_t overcurrent_protection_mode : 1;
|
||||
uint32_t no_over_current_protection : 1;
|
||||
uint32_t reserved : 11;
|
||||
uint32_t power_on_to_good_time : 8;
|
||||
} rh_descriptorA_bit;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t rh_descriptorB;
|
||||
struct {
|
||||
uint32_t device_removable : 16;
|
||||
uint32_t port_power_control_mask : 16;
|
||||
} rh_descriptorB_bit;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t rh_status;
|
||||
@ -248,7 +269,7 @@ typedef volatile struct
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t rhport_status[2]; // TODO NXP OHCI controller only has 2 ports
|
||||
uint32_t rhport_status[TUP_OHCI_RHPORTS];
|
||||
struct {
|
||||
uint32_t current_connect_status : 1;
|
||||
uint32_t port_enable_status : 1;
|
||||
@ -265,11 +286,11 @@ typedef volatile struct
|
||||
uint32_t port_over_current_indicator_change : 1;
|
||||
uint32_t port_reset_status_change : 1;
|
||||
uint32_t TU_RESERVED : 11;
|
||||
}rhport_status_bit[2];
|
||||
}rhport_status_bit[TUP_OHCI_RHPORTS];
|
||||
};
|
||||
}ohci_registers_t;
|
||||
|
||||
TU_VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct");
|
||||
TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * TUP_OHCI_RHPORTS)), "size is not correct");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user