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https://github.com/hathach/tinyusb.git
synced 2025-02-19 06:40:45 +00:00
rename tusbd_msc_scsi_received_isr to tusbd_msc_scsi_cb
fix the status phase true --> false ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), false) ); board ea4357 added P9_5 pull down for device connect
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@ -75,8 +75,13 @@ void board_init(void)
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//------------- USB -------------//
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// USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
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scu_pinmux(0x2, 3, MD_PUP | MD_EZI, FUNC7); // USB0 VBus Power
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scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7); // USB0 VBus Power
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#if TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_DEVICE
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scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
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GPIO_SetDir(5, BIT_(18), 1);
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#endif
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// USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
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// TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
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@ -97,7 +97,7 @@ static scsi_mode_parameters_t msc_dev_mode_para TUSB_CFG_ATTR_USBRAM =
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//--------------------------------------------------------------------+
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// tinyusb callback (ISR context)
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//--------------------------------------------------------------------+
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msc_csw_status_t tusbd_msc_scsi_received_isr (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length)
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msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length)
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{
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// read10 & write10 has their own callback and MUST not be handled here
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switch (scsi_cmd[0])
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@ -82,10 +82,10 @@
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#define TUSB_CFG_DEVICE_FULLSPEED 1 // TODO refractor, remove
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//------------- CLASS -------------//
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#define TUSB_CFG_DEVICE_HID_KEYBOARD 1
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#define TUSB_CFG_DEVICE_HID_KEYBOARD 0
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#define TUSB_CFG_DEVICE_HID_MOUSE 0
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#define TUSB_CFG_DEVICE_HID_GENERIC 0
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#define TUSB_CFG_DEVICE_MSC 0
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#define TUSB_CFG_DEVICE_MSC 1
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#define TUSB_CFG_DEVICE_CDC 0
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//--------------------------------------------------------------------+
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@ -66,6 +66,7 @@ STATIC_VAR mscd_interface_t mscd_data TUSB_CFG_ATTR_USBRAM;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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static bool read10_write10_data_xfer(mscd_interface_t* p_msc);
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//--------------------------------------------------------------------+
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// USBD-CLASS API
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@ -136,6 +137,80 @@ tusb_error_t mscd_control_request_subtask(uint8_t coreid, tusb_control_request_t
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return TUSB_ERROR_NONE;
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}
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//--------------------------------------------------------------------+
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// MSCD APPLICATION CALLBACK
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//--------------------------------------------------------------------+
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tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xferred_bytes)
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{
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// TODO failed --> STALL pipe, on clear STALL --> queue endpoint OUT
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static bool is_waiting_read10_write10 = false; // indicate we are transferring data in READ10, WRITE10 command
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mscd_interface_t * const p_msc = &mscd_data;
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msc_cmd_block_wrapper_t * const p_cbw = &p_msc->cbw;
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msc_cmd_status_wrapper_t * const p_csw = &p_msc->csw;
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//------------- new CBW received -------------//
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if ( !is_waiting_read10_write10 )
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{
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if ( endpointhandle_is_equal(p_msc->edpt_in, edpt_hdl) ) return TUSB_ERROR_NONE; // bulk in interrupt for dcd to clean up
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ASSERT( endpointhandle_is_equal(p_msc->edpt_out, edpt_hdl) &&
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xferred_bytes == sizeof(msc_cmd_block_wrapper_t) &&
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event == TUSB_EVENT_XFER_COMPLETE &&
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p_cbw->signature == MSC_CBW_SIGNATURE, TUSB_ERROR_INVALID_PARA );
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p_csw->signature = MSC_CSW_SIGNATURE;
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p_csw->tag = p_cbw->tag;
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p_csw->data_residue = 0;
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if ( (SCSI_CMD_READ_10 != p_cbw->command[0]) && (SCSI_CMD_WRITE_10 != p_cbw->command[0]) )
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{
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void *p_buffer = NULL;
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uint16_t actual_length = (uint16_t) p_cbw->xfer_bytes;
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p_csw->status = tusbd_msc_scsi_cb(edpt_hdl.coreid, p_cbw->lun, p_cbw->command, &p_buffer, &actual_length);
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//------------- Data Phase (non READ10, WRITE10) -------------//
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if ( p_cbw->xfer_bytes )
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{
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ASSERT( p_cbw->xfer_bytes >= actual_length, TUSB_ERROR_INVALID_PARA );
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endpoint_handle_t const edpt_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->edpt_in : p_msc->edpt_out;
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if ( p_buffer == NULL || actual_length == 0 )
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{ // application does not provide data to response --> possibly unsupported SCSI command
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ASSERT_STATUS( dcd_pipe_stall(edpt_data) );
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p_csw->status = MSC_CSW_STATUS_FAILED;
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}else
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{
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ASSERT_STATUS( dcd_pipe_queue_xfer( edpt_data, p_buffer, min16_of(actual_length, (uint16_t) p_cbw->xfer_bytes)) );
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}
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}
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}
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}
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//------------- Data Phase For READ10 & WRITE10 (can be executed several times) -------------//
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if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
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{
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if (is_waiting_read10_write10)
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{ // continue with read10, write10 data transfer, interrupt must come from endpoint IN
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ASSERT( endpointhandle_is_equal(p_msc->edpt_in, edpt_hdl) && event == TUSB_EVENT_XFER_COMPLETE, TUSB_ERROR_INVALID_PARA);
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}
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is_waiting_read10_write10 = !read10_write10_data_xfer(p_msc);
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}
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//------------- Status Phase -------------//
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// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
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if (!is_waiting_read10_write10)
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{
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), false) );
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//------------- Queue the next CBW -------------//
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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}
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return TUSB_ERROR_NONE;
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}
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// return true if data phase is complete, false if not yet complete
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static bool read10_write10_data_xfer(mscd_interface_t* p_msc)
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{
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@ -182,78 +257,4 @@ static bool read10_write10_data_xfer(mscd_interface_t* p_msc)
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}
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}
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//--------------------------------------------------------------------+
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// MSCD APPLICATION CALLBACK
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//--------------------------------------------------------------------+
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tusb_error_t mscd_xfer_cb(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xferred_bytes)
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{
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// TODO failed --> STALL pipe, on clear STALL --> queue endpoint OUT
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static bool is_waiting_read10_write10 = false; // indicate we are transferring data in READ10, WRITE10 command
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mscd_interface_t * const p_msc = &mscd_data;
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msc_cmd_block_wrapper_t * const p_cbw = &p_msc->cbw;
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msc_cmd_status_wrapper_t * const p_csw = &p_msc->csw;
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//------------- new CBW received -------------//
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if ( !is_waiting_read10_write10)
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{
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if ( endpointhandle_is_equal(p_msc->edpt_in, edpt_hdl) ) return TUSB_ERROR_NONE; // bulk in interrupt for dcd to clean up
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ASSERT( endpointhandle_is_equal(p_msc->edpt_out, edpt_hdl) &&
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xferred_bytes == sizeof(msc_cmd_block_wrapper_t) &&
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event == TUSB_EVENT_XFER_COMPLETE &&
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p_cbw->signature == MSC_CBW_SIGNATURE, TUSB_ERROR_INVALID_PARA );
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p_csw->signature = MSC_CSW_SIGNATURE;
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p_csw->tag = p_cbw->tag;
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p_csw->data_residue = 0;
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if ( (SCSI_CMD_READ_10 != p_cbw->command[0]) && (SCSI_CMD_WRITE_10 != p_cbw->command[0]) )
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{
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void *p_buffer = NULL;
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uint16_t actual_length = (uint16_t) p_cbw->xfer_bytes;
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p_csw->status = tusbd_msc_scsi_received_isr(edpt_hdl.coreid, p_cbw->lun, p_cbw->command, &p_buffer, &actual_length);
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//------------- Data Phase -------------//
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if ( p_cbw->xfer_bytes )
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{
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ASSERT( p_cbw->xfer_bytes >= actual_length, TUSB_ERROR_INVALID_PARA );
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endpoint_handle_t const edpt_data = BIT_TEST_(p_cbw->dir, 7) ? p_msc->edpt_in : p_msc->edpt_out;
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if ( p_buffer == NULL || actual_length == 0 )
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{ // application does not provide data to response --> possibly unsupported SCSI command
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ASSERT_STATUS( dcd_pipe_stall(edpt_data) );
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p_csw->status = MSC_CSW_STATUS_FAILED;
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}else
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{
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ASSERT_STATUS( dcd_pipe_queue_xfer( edpt_data, p_buffer, min16_of(actual_length, (uint16_t) p_cbw->xfer_bytes)) );
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}
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}
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}
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}
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//------------- Data Phase For READ10 & WRITE10 (can be executed several times) -------------//
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if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
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{
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if (is_waiting_read10_write10)
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{ // continue with read10, write10 data transfer, interrupt must come from endpoint IN
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ASSERT( endpointhandle_is_equal(p_msc->edpt_in, edpt_hdl) && event == TUSB_EVENT_XFER_COMPLETE, TUSB_ERROR_INVALID_PARA);
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}
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is_waiting_read10_write10 = !read10_write10_data_xfer(p_msc);
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}
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//------------- Status Phase -------------//
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// Either bulk in & out can be stalled in the data phase, dcd must make sure these queued transfer will be resumed after host clear stall
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if (!is_waiting_read10_write10)
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{
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_in , p_csw, sizeof(msc_cmd_status_wrapper_t), true) ); // need to be true for dcd to clean up qtd !!
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//------------- Queue the next CBW -------------//
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ASSERT_STATUS( dcd_pipe_xfer( p_msc->edpt_out, p_cbw, sizeof(msc_cmd_block_wrapper_t), true) );
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}
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return TUSB_ERROR_NONE;
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}
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#endif
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@ -114,7 +114,7 @@ uint16_t tusbd_msc_write10_cb(uint8_t coreid, uint8_t lun, void** pp_buffer, uin
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* \note Although this callback is called by tinyusb device task (non-isr context), however as all the classes share
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* the same task (to save resource), any delay in this callback will cause delay in reponse on other classes.
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*/
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msc_csw_status_t tusbd_msc_scsi_received_isr (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length);
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msc_csw_status_t tusbd_msc_scsi_cb (uint8_t coreid, uint8_t lun, uint8_t scsi_cmd[16], void ** pp_buffer, uint16_t* p_length);
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/** @} */
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/** @} */
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