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stm32h7: Enable USB peripheral (device does not enumerate yet).
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@ -21,7 +21,8 @@ SRC_C += \
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \
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hw/mcu/st/stm32lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
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SRC_S += \
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hw/mcu/st/startup/stm32h7/startup_stm32h743xx.s
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@ -163,6 +163,11 @@ void board_init(void)
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GPIO_InitStruct.Pull = GPIO_PULLUP;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
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// https://community.st.com/s/question/0D50X00009XkYZLSA3/stm32h7-nucleo-usb-fs-cdc
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// TODO: Board init actually works fine without this line.
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HAL_PWREx_EnableUSBVoltageDetector();
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__HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
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}
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//--------------------------------------------------------------------+
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@ -34,6 +34,7 @@
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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/*------------------------------------------------------------------*/
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/* Controller API
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@ -41,6 +42,43 @@
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void dcd_init (uint8_t rhport)
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{
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(void) rhport;
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// Programming model begins on page 2634 of Rev 6 of reference manual.
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USB2_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_TXFELVL | USB_OTG_GAHBCFG_GINT;
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// No HNP/SRP (no OTG support), program timeout later, turnaround
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// programmed for 32+ MHz.
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USB2_OTG_FS->GUSBCFG |= (0x06 << USB_OTG_GUSBCFG_TRDT_Pos);
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// Clear all used interrupts
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USB2_OTG_FS->GINTSTS |= USB_OTG_GINTSTS_OTGINT | USB_OTG_GINTSTS_MMIS | \
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USB_OTG_GINTSTS_USBRST | USB_OTG_GINTSTS_ENUMDNE | \
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USB_OTG_GINTSTS_ESUSP | USB_OTG_GINTSTS_USBSUSP | USB_OTG_GINTSTS_SOF;
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// Required as part of core initialization. Disable OTGINT as we don't use
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// it right now. TODO: How should mode mismatch be handled? It will cause
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// the core to stop working/require reset.
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USB2_OTG_FS->GINTMSK |= /* USB_OTG_GINTMSK_OTGINT | */ USB_OTG_GINTMSK_MMISM;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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// If USB host misbehaves during status portion of control xfer
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// (non zero-length packet), send STALL back and discard. Full speed.
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dev->DCFG |= USB_OTG_DCFG_NZLSOHSK | (3 << USB_OTG_DCFG_DSPD_Pos);
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USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | \
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USB_OTG_GINTMSK_SOFM | USB_OTG_GINTMSK_RXFLVLM /* SB_OTG_GINTMSK_ESUSPM | \
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USB_OTG_GINTMSK_USBSUSPM */;
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// Enable pullup, enable peripheral.
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#ifdef USB_OTG_GCCFG_VBDEN
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USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
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#else
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USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
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#endif
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// This step does not appear to be specified in the programmer's model.
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dev->DCTL &= ~USB_OTG_DCTL_SDIS;
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}
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void dcd_int_enable (uint8_t rhport)
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