mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-20 18:40:57 +00:00
add semaphore for control xfer for > 64 support for some mcu such as lpc11u/lpc17xx
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d4a260c090
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6e463caec0
@ -85,9 +85,8 @@
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#define TUSB_CFG_DEVICE_HID_MOUSE 1
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#define TUSB_CFG_DEVICE_HID_GENERIC 0
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#define TUSB_CFG_DEVICE_MSC 0
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#define TUSB_CFG_DEVICE_CDC 0
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#define TUSB_CFG_DEVICE_CDC 1
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// TODO LPC11UXX seems not able to DMA > 64 bytes control transfer while LPC13uxx has no problem with that
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//--------------------------------------------------------------------+
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// COMMON CONFIGURATION
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@ -241,7 +241,17 @@ void dcd_isr(uint8_t coreid)
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LPC_USB->DEVCMDSTAT |= CMDSTAT_MASK_SETUP_RECEIVED;
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dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
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}
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else if ( int_status & 0x03 )
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{ // either control endpoints
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endpoint_handle_t edpt_hdl =
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{
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.coreid = coreid,
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.index = BIT_TEST_(int_status, 1) ? 1 : 0
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};
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// FIXME xferred_byte for control xfer is not needed now !!!
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usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE, 0);
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}
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//------------- Non-Control Endpoints -------------//
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@ -265,6 +275,7 @@ void dcd_isr(uint8_t coreid)
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LPC_USB->EPBUFCFG = BIT_CLR_(LPC_USB->EPBUFCFG , ep_id); // clear double buffering
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// TODO no way determine if the transfer is failed or not
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// FIXME xferred_byte is not correct
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usbd_xfer_isr(edpt_hdl, TUSB_EVENT_XFER_COMPLETE,
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dcd_data.expected_bytes[ep_id] - dcd_data.qhd[ep_id][0].total_bytes); // only number of bytes in the IOC qtd
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}
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@ -283,19 +294,6 @@ void dcd_pipe_control_stall(uint8_t coreid)
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dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
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}
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// used for data phase only
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//tusb_error_t dcd_pipe_control_queue_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length)
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//{
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// (void) coreid;
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//
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// uint8_t const ep_id = dir; // IN : 1, OUT = 0
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//
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// dcd_data.qhd[ep_id][0].buff_addr_offset = (length ? addr_offset(p_buffer) : 0 );
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// dcd_data.qhd[ep_id][0].total_bytes = length;
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//
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//}
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// can be data phase (long data) or status phase
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length)
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{
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(void) coreid;
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@ -49,6 +49,13 @@
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#include "tusb_descriptors.h" // TODO callback include
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#include "usbd_dcd.h"
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// Some MCUs cannot transfer more than 64 bytes each queue, thus require special task-alike treatment
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#if MCU == MCU_LPC11UXX
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#define USBD_CONTROL_ONE_PACKET_EACH_XFER // for each Transfer, cannot queue more than packet size
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enum {
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USBD_COTNROL_MAX_LENGTH_EACH_XFER = 64
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};
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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@ -127,75 +134,92 @@ typedef struct {
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OSAL_TASK_DEF(usbd_task, 150, TUSB_CFG_OS_TASK_PRIO);
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OSAL_QUEUE_DEF(usbd_queue_def, USBD_TASK_QUEUE_DEPTH, usbd_task_event_t);
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OSAL_SEM_DEF(usbd_control_xfer_semaphore_def);
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static osal_queue_handle_t usbd_queue_hdl;
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static osal_semaphore_handle_t usbd_control_xfer_sem_hdl;
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tusb_error_t usbd_body_subtask(void)
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{
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OSAL_SUBTASK_BEGIN
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static uint8_t coreid;
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tusb_error_t error = TUSB_ERROR_NONE;
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usbd_task_event_t event;
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osal_queue_receive(usbd_queue_hdl, &event, OSAL_TIMEOUT_WAIT_FOREVER, &error);
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SUBTASK_ASSERT_STATUS(error);
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coreid = event.coreid;
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if ( USBD_EVENTID_SETUP_RECEIVED == event.event_id )
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{
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usbd_device_info_t *p_device = &usbd_devices[event.coreid];
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tusb_control_request_t* p_request = &p_device->control_request;
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{ // should copy to setup packet to local variable as the new one may overwrite while we processing here
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static tusb_control_request_t control_request;
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control_request = usbd_devices[coreid].control_request;
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//------------- Standard Control such as those in enumeration -------------//
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if( TUSB_REQUEST_RECIPIENT_DEVICE == p_request->bmRequestType_bit.recipient &&
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TUSB_REQUEST_TYPE_STANDARD == p_request->bmRequestType_bit.type )
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if( TUSB_REQUEST_RECIPIENT_DEVICE == control_request.bmRequestType_bit.recipient &&
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TUSB_REQUEST_TYPE_STANDARD == control_request.bmRequestType_bit.type )
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{
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if ( TUSB_REQUEST_GET_DESCRIPTOR == p_request->bRequest )
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if ( TUSB_REQUEST_GET_DESCRIPTOR == control_request.bRequest )
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{
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static uint8_t const * p_buffer = NULL;
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static uint16_t length = 0;
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error = get_descriptor_subtask(event.coreid, p_request, &p_buffer, &length);
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error = get_descriptor_subtask(coreid, &control_request, &p_buffer, &length);
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dcd_pipe_control_xfer(event.coreid, p_request->bmRequestType_bit.direction, p_buffer, length); // zero length
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#ifdef USBD_CONTROL_ONE_PACKET_EACH_XFER
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while ( length > USBD_COTNROL_MAX_LENGTH_EACH_XFER && error == TUSB_ERROR_NONE )
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{
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usbd_devices[coreid].is_waiting_control_xfer = true;
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dcd_pipe_control_xfer(coreid, control_request.bmRequestType_bit.direction, p_buffer, USBD_COTNROL_MAX_LENGTH_EACH_XFER); // zero length
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osal_semaphore_wait(usbd_control_xfer_sem_hdl, OSAL_TIMEOUT_NORMAL, &error);
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length -= USBD_COTNROL_MAX_LENGTH_EACH_XFER;
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p_buffer += USBD_COTNROL_MAX_LENGTH_EACH_XFER;
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}
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usbd_devices[coreid].is_waiting_control_xfer = false;
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#endif
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if ( TUSB_ERROR_NONE == error )
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{
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dcd_pipe_control_xfer(coreid, control_request.bmRequestType_bit.direction, p_buffer, length); // zero length
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}
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}
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else if ( TUSB_REQUEST_SET_ADDRESS == p_request->bRequest )
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else if ( TUSB_REQUEST_SET_ADDRESS == control_request.bRequest )
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{
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dcd_controller_set_address(event.coreid, (uint8_t) p_request->wValue);
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p_device->state = TUSB_DEVICE_STATE_ADDRESSED;
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dcd_controller_set_address(coreid, (uint8_t) control_request.wValue);
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usbd_devices[coreid].state = TUSB_DEVICE_STATE_ADDRESSED;
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}
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else if ( TUSB_REQUEST_SET_CONFIGURATION == p_request->bRequest )
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else if ( TUSB_REQUEST_SET_CONFIGURATION == control_request.bRequest )
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{
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usbd_set_configure_received(event.coreid, (uint8_t) p_request->wValue);
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usbd_set_configure_received(coreid, (uint8_t) control_request.wValue);
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}else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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}
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}
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//------------- Class/Interface Specific Request -------------//
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else if ( TUSB_REQUEST_RECIPIENT_INTERFACE == p_request->bmRequestType_bit.recipient)
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else if ( TUSB_REQUEST_RECIPIENT_INTERFACE == control_request.bmRequestType_bit.recipient)
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{
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tusb_std_class_code_t class_code = p_device->interface2class[ u16_low_u8(p_request->wIndex) ];
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tusb_std_class_code_t class_code = usbd_devices[coreid].interface2class[ u16_low_u8(control_request.wIndex) ];
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if ( (TUSB_CLASS_AUDIO <= class_code) && (class_code <= TUSB_CLASS_AUDIO_VIDEO) &&
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usbd_class_drivers[class_code].control_request )
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{
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error = usbd_class_drivers[class_code].control_request(event.coreid, p_request);
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error = usbd_class_drivers[class_code].control_request(coreid, &control_request);
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}else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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}
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}
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//------------- Endpoint Request -------------//
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else if ( TUSB_REQUEST_RECIPIENT_ENDPOINT == p_request->bmRequestType_bit.recipient &&
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TUSB_REQUEST_TYPE_STANDARD == p_request->bmRequestType_bit.type )
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else if ( TUSB_REQUEST_RECIPIENT_ENDPOINT == control_request.bmRequestType_bit.recipient &&
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TUSB_REQUEST_TYPE_STANDARD == control_request.bmRequestType_bit.type &&
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TUSB_REQUEST_CLEAR_FEATURE == control_request.bRequest )
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{
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if ( TUSB_REQUEST_CLEAR_FEATURE == p_request->bRequest )
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{
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dcd_pipe_clear_stall(event.coreid, u16_low_u8(p_request->wIndex) );
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} else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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}
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dcd_pipe_clear_stall(coreid, u16_low_u8(control_request.wIndex) );
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} else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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@ -203,11 +227,11 @@ tusb_error_t usbd_body_subtask(void)
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if(TUSB_ERROR_NONE != error)
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{ // Response with Protocol Stall if request is not supported
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dcd_pipe_control_stall(event.coreid);
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dcd_pipe_control_stall(coreid);
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// ASSERT(error == TUSB_ERROR_NONE, VOID_RETURN);
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}else
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{ // status phase
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dcd_pipe_control_xfer(event.coreid, 1-p_request->bmRequestType_bit.direction, NULL, 0); // zero length
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dcd_pipe_control_xfer(coreid, 1-control_request.bmRequestType_bit.direction, NULL, 0); // zero length
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}
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}
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@ -246,6 +270,10 @@ tusb_error_t usbd_init (void)
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//------------- Task init -------------//
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usbd_queue_hdl = osal_queue_create( OSAL_QUEUE_REF(usbd_queue_def) );
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ASSERT_PTR(usbd_queue_hdl, TUSB_ERROR_OSAL_QUEUE_FAILED);
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usbd_control_xfer_sem_hdl = osal_semaphore_create( OSAL_SEM_REF(usbd_control_xfer_semaphore_def) );
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ASSERT_PTR(usbd_queue_hdl, TUSB_ERROR_OSAL_SEMAPHORE_FAILED);
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ASSERT_STATUS( osal_task_create( OSAL_TASK_REF(usbd_task) ));
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//------------- class init -------------//
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@ -351,9 +379,12 @@ void usbd_xfer_isr(endpoint_handle_t edpt_hdl, tusb_event_t event, uint32_t xfer
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// usbd_device_info_t *p_device = &usbd_devices[edpt_hdl.coreid];
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uint8_t class_index = std_class_code_to_index(edpt_hdl.class_code);
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if (class_index == 0) // Control Transfer
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if (class_index == 0 ) // Control Transfer
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{
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if (usbd_devices[edpt_hdl.coreid].is_waiting_control_xfer)
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{
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osal_semaphore_post( usbd_control_xfer_sem_hdl );
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}
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}else if (usbd_class_drivers[class_index].isr)
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{
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usbd_class_drivers[class_index].isr(edpt_hdl, event, xferred_bytes);
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@ -61,6 +61,7 @@
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typedef struct {
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volatile uint8_t state;
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uint8_t is_waiting_control_xfer; // set if task is waiting for control xfer to complete to proceed
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tusb_control_request_t control_request;
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uint8_t interface2class[USBD_MAX_INTERFACE]; // determine interface number belongs to which class
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}usbd_device_info_t;
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