diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index d162e4e8e..a2c40e669 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -216,17 +216,19 @@ static inline bool     tu_bit_test (uint32_t value, uint8_t pos) { return (value
 void tu_print_mem(void const *buf, uint8_t size, uint16_t count);
 
 #ifndef tu_printf
-  #define tu_printf     printf
+  #define tu_printf         printf
 #endif
 
 // Log with debug level 1
-#define TU_LOG1         tu_printf
-#define TU_LOG1_MEM     tu_print_mem
+#define TU_LOG1               tu_printf
+#define TU_LOG1_MEM           tu_print_mem
+#define TU_LOG1_LOCATION()    tu_printf("%s: %d:\n", __PRETTY_FUNCTION__, __LINE__)
 
 // Log with debug level 2
 #if CFG_TUSB_DEBUG > 1
-  #define TU_LOG2       TU_LOG1
-  #define TU_LOG2_MEM   TU_LOG1_MEM
+  #define TU_LOG2             TU_LOG1
+  #define TU_LOG2_MEM         TU_LOG1_MEM
+  #define TU_LOG2_LOCATION()  TU_LOG1_LOCATION()
 #endif
 
 #endif // CFG_TUSB_DEBUG
diff --git a/src/device/dcd.h b/src/device/dcd.h
index dca289e78..8ae232fa6 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -110,6 +110,10 @@ void dcd_remote_wakeup(uint8_t rhport);
 // Endpoint API
 //--------------------------------------------------------------------+
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
+
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open        (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
 
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 7f6cf5a40..8b9b8f1cf 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -64,6 +64,7 @@ static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t con
   return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
 }
 
+// Status phase
 bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
 {
   _ctrl_xfer.request       = (*request);
@@ -141,6 +142,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
   {
     TU_ASSERT(0 == xferred_bytes);
+    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
     return true;
   }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ec182960e..7ba9481ba 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -296,6 +296,8 @@ void dcd_int_disable(uint8_t rhport)
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   (void)rhport;
+
+  // FIXME use dcd_edpt0_status_complete()
   // We cannot immediatly change it; it must be queued to change after the STATUS packet is sent.
   // (CTR handler will actually change the address once it sees that the transmission is complete)
   newDADDR = dev_addr;