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https://github.com/hathach/tinyusb.git
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separate data & status from dcd_pipe_control_xfer
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@ -160,7 +160,6 @@ tusb_error_t hidd_control_request(uint8_t coreid, tusb_control_request_t const *
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{
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case HID_REQUEST_CONTROL_SET_IDLE:
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// idle_rate = u16_high_u8(p_request->wValue);
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dcd_pipe_control_xfer(coreid, TUSB_DIR_HOST_TO_DEV, NULL, 0);
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break;
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case HID_REQUEST_CONTROL_SET_REPORT:
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@ -81,7 +81,7 @@ void dcd_controller_set_address(uint8_t coreid, uint8_t dev_addr);
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void dcd_controller_set_configuration(uint8_t coreid);
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//------------- PIPE API -------------//
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * buffer, uint16_t length);
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length);
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void dcd_pipe_control_stall(uint8_t coreid);
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//tusb_error_t dcd_pipe_control_write(uint8_t coreid, void const * buffer, uint16_t length);
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@ -283,28 +283,28 @@ void dcd_pipe_control_stall(uint8_t coreid)
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dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
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}
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// control transfer does not need to use qtd find function
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * buffer, uint16_t length)
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// used for data phase only
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//tusb_error_t dcd_pipe_control_queue_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length)
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//{
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// (void) coreid;
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//
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// uint8_t const ep_id = dir; // IN : 1, OUT = 0
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//
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// dcd_data.qhd[ep_id][0].buff_addr_offset = (length ? addr_offset(p_buffer) : 0 );
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// dcd_data.qhd[ep_id][0].total_bytes = length;
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//
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//}
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// can be data phase (long data) or status phase
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length)
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{
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(void) coreid;
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// determine Endpoint where Data & Status phase occurred (IN or OUT)
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uint8_t const endpoint_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0;
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uint8_t const endpoint_status = 1 - endpoint_data;
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//------------- Data Phase -------------//
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if (length)
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{
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dcd_data.qhd[endpoint_data][0].buff_addr_offset = addr_offset(buffer);
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dcd_data.qhd[endpoint_data][0].total_bytes = length;
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dcd_data.qhd[endpoint_data][0].active = 1 ;
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}
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//------------- Status Phase -------------//
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dcd_data.qhd[endpoint_status][0].buff_addr_offset = 0;
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dcd_data.qhd[endpoint_status][0].total_bytes = 0;
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dcd_data.qhd[endpoint_status][0].active = 1 ;
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uint8_t const ep_id = dir; // IN : 1, OUT = 0
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dcd_data.qhd[ep_id][0].buff_addr_offset = (length ? addr_offset(p_buffer) : 0 );
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dcd_data.qhd[ep_id][0].total_bytes = length;
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dcd_data.qhd[ep_id][0].active = 1 ;
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return TUSB_ERROR_NONE;
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}
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@ -157,12 +157,10 @@ tusb_error_t usbd_body_subtask(void)
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{
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dcd_controller_set_address(event.coreid, (uint8_t) p_request->wValue);
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p_device->state = TUSB_DEVICE_STATE_ADDRESSED;
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dcd_pipe_control_xfer(event.coreid, TUSB_DIR_HOST_TO_DEV, NULL, 0); // zero length
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}
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else if ( TUSB_REQUEST_SET_CONFIGURATION == p_request->bRequest )
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{
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usbd_set_configure_received(event.coreid, (uint8_t) p_request->wValue);
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dcd_pipe_control_xfer(event.coreid, TUSB_DIR_HOST_TO_DEV, NULL, 0); // zero length
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}else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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@ -189,7 +187,6 @@ tusb_error_t usbd_body_subtask(void)
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if ( TUSB_REQUEST_CLEAR_FEATURE == p_request->bRequest )
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{
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dcd_pipe_clear_stall(event.coreid, u16_low_u8(p_request->wIndex) );
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dcd_pipe_control_xfer(event.coreid, TUSB_DIR_HOST_TO_DEV, NULL, 0); // zero length
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} else
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{
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error = TUSB_ERROR_DCD_CONTROL_REQUEST_NOT_SUPPORT;
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@ -203,6 +200,9 @@ tusb_error_t usbd_body_subtask(void)
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{ // Response with Protocol Stall if request is not supported
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dcd_pipe_control_stall(event.coreid);
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// ASSERT(error == TUSB_ERROR_NONE, VOID_RETURN);
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}else
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{ // status phase
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dcd_pipe_control_xfer(event.coreid, 1-p_request->bmRequestType_bit.direction, NULL, 0); // zero length
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}
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}
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