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wrap up lpc11u port
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f28a15a886
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@ -54,10 +54,13 @@
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// only SRAM1 & USB RAM can be used for transfer
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#define SRAM_REGION 0x20000000
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// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
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// endpoint's max packet size and need some soft DMA helper
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/* Although device controller are the same. DMA of
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* - LPC11u can only transfer up to nbytes = 64
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* - LPC13 can transfer nbytes = 1023 (maximum)
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* - LPC15 can ???
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*/
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enum {
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DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
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DMA_NBYTES_MAX = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
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};
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enum {
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@ -80,7 +83,7 @@ enum {
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typedef struct ATTR_PACKED
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{
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// Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
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volatile uint16_t buffer_offset ;
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volatile uint16_t buffer_offset;
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volatile uint16_t nbytes : 10 ;
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uint16_t is_iso : 1 ;
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@ -93,21 +96,23 @@ typedef struct ATTR_PACKED
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TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
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typedef struct
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{
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uint16_t total_bytes;
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uint16_t xferred_bytes;
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uint16_t nbytes;
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}xfer_dma_t;
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// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
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// current_td is used to keep track of number of remaining & xferred bytes of the current request.
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typedef struct
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{
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// 256 byte aligned, 2 for double buffer (not used)
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// Each cmd_sts can only transfer up to 1023 bytes each pass
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//
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// Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
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ep_cmd_sts_t ep[EP_COUNT][2];
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struct {
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uint16_t remaining_bytes; ///< expected bytes of the queued transfer
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uint16_t xferred_bytes; ///< xferred bytes of the current transfer
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uint16_t nbytes; // Set nbytes, to determine transferred bytes each pass
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}current_td[EP_COUNT];
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xfer_dma_t dma[EP_COUNT];
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ATTR_ALIGNED(64) uint8_t setup_packet[8];
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}dcd_data_t;
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@ -119,7 +124,7 @@ typedef struct
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// EP list must be 256-byte aligned
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CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static dcd_data_t _dcd;
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static inline uint16_t addr_offset(void const * buffer)
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static inline uint16_t get_buf_offset(void const * buffer)
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{
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uint32_t addr = (uint32_t) buffer;
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TU_ASSERT( (addr & 0x3f) == 0, 0 );
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@ -204,26 +209,23 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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else
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{
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uint8_t const ep_id = ep_addr2id(ep_addr);
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_dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 1;
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_dcd.ep[ep_id][0].stall = 1;
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}
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}
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bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const ep_id = ep_addr2id(ep_addr);
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return _dcd.ep[ep_id][0].stall || _dcd.ep[ep_id][1].stall;
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return _dcd.ep[ep_id][0].stall;
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
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{
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uint8_t const ep_id = ep_addr2id(edpt_addr);
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// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
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_dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 0;
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// since the next transfer always take place on buffer0 --> clear buffer0 toggle
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_dcd.ep[ep_id][0].toggle_reset = 1;
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_dcd.ep[ep_id][0].toggle_mode = 0;
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_dcd.ep[ep_id][0].stall = 0;
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_dcd.ep[ep_id][0].toggle_reset = 1;
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_dcd.ep[ep_id][0].toggle_mode = 0;
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -240,7 +242,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
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tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
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_dcd.ep[ep_id][0].is_iso = _dcd.ep[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
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_dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
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// Enable EP interrupt
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LPC_USB->INTEN |= BIT_(ep_id);
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@ -251,32 +253,28 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const ep_id = ep_addr2id(ep_addr);
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return _dcd.ep[ep_id][0].active || _dcd.ep[ep_id][1].active;
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return _dcd.ep[ep_id][0].active;
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}
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static void prepare_ep_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
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static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
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{
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uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
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uint16_t const nbytes = tu_min16(total_bytes, DMA_NBYTES_MAX);
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_dcd.current_td[ep_id].nbytes = queued_bytes;
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_dcd.current_td[ep_id].remaining_bytes -= queued_bytes;
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_dcd.ep[ep_id][0].buffer_offset = buff_addr_offset;
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_dcd.ep[ep_id][0].nbytes = queued_bytes;
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_dcd.dma[ep_id].nbytes = nbytes;
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_dcd.ep[ep_id][0].buffer_offset = buf_offset;
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_dcd.ep[ep_id][0].nbytes = nbytes;
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_dcd.ep[ep_id][0].active = 1;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
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{
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uint8_t const ep_id = ep_addr2id(ep_addr);
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uint16_t buf_offset = addr_offset(buffer);
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_dcd.current_td[ep_id].remaining_bytes = total_bytes;
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_dcd.current_td[ep_id].xferred_bytes = 0;
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_dcd.current_td[ep_id].nbytes = 0;
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tu_varclr(&_dcd.dma[ep_id]);
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_dcd.dma[ep_id].total_bytes = total_bytes;
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prepare_ep_xfer(ep_id, buf_offset, total_bytes);
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prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
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return true;
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}
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@ -294,7 +292,7 @@ static void bus_reset(void)
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_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
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}
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_dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
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_dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
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LPC_USB->EPINUSE = 0;
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LPC_USB->EPBUFCFG = 0;
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@ -312,23 +310,24 @@ static void process_xfer_isr(uint32_t int_status)
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if ( BIT_TEST_(int_status, ep_id) )
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{
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ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
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xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
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_dcd.current_td[ep_id].xferred_bytes += _dcd.current_td[ep_id].nbytes - ep_cs->nbytes;
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xfer_dma->xferred_bytes += xfer_dma->nbytes - ep_cs->nbytes;
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if ( (ep_cs->nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
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if ( (ep_cs->nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
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{
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// There is more data to transfer
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// buff_offset has been already increased by hw to correct value for next transfer
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prepare_ep_xfer(ep_id, ep_cs->buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
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prepare_ep_xfer(ep_id, ep_cs->buffer_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
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}
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else
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{
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_dcd.current_td[ep_id].remaining_bytes = 0;
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xfer_dma->total_bytes = xfer_dma->xferred_bytes;
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uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
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// TODO no way determine if the transfer is failed or not
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dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_bytes, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
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}
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}
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}
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@ -394,7 +393,7 @@ void USB_IRQHandler(void)
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dcd_event_setup_received(0, _dcd.setup_packet, true);
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// keep waiting for next setup
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_dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
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_dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
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// clear bit0
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int_status = BIT_CLR_(int_status, 0);
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