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fix build warnings

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hathach 2023-06-16 12:02:42 +07:00
parent 8af8869d3b
commit 65d6acdbfa
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9 changed files with 47 additions and 39 deletions
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2
hw/bsp/family_support.cmake
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@ -177,6 +177,8 @@ function(family_add_freertos TARGET)
target_include_directories(freertos_config INTERFACE target_include_directories(freertos_config INTERFACE
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
) )
# add board definition to freertos_config mostly for SystemCoreClock
target_link_libraries(freertos_config INTERFACE board_${BOARD})
endif() endif()
# freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable

3
hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
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@ -44,8 +44,7 @@
// skip if included from IAR assembler // skip if included from IAR assembler
#ifndef __IASMARM__ #ifndef __IASMARM__
// FIXME cause redundant-decls warnings #include "fsl_device_registers.h"
extern uint32_t SystemCoreClock;
#endif #endif
/* Cortex M23/M33 port configuration. */ /* Cortex M23/M33 port configuration. */

12
hw/bsp/imxrt/family.cmake
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@ -103,10 +103,6 @@ function(family_configure_example TARGET)
#---------- Port Specific ---------- #---------- Port Specific ----------
# These files are built for each example since it depends on example's tusb_config.h # These files are built for each example since it depends on example's tusb_config.h
target_sources(${TARGET} PUBLIC target_sources(${TARGET} PUBLIC
# TinyUSB Port
${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
${TOP}/src/portable/ehci/ehci.c
# BSP # BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@ -121,6 +117,14 @@ function(family_configure_example TARGET)
# Add TinyUSB # Add TinyUSB
family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
# Add TinyUSB Port source
target_sources(${TARGET}-tinyusb PUBLIC
${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
${TOP}/src/portable/ehci/ehci.c
)
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
# Link dependencies # Link dependencies
target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)

6
src/device/dcd.h
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@ -108,15 +108,15 @@ typedef struct TU_ATTR_ALIGNED(4)
// clean/flush data cache: write cache -> memory. // clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory // Required before an DMA TX transfer to make sure data is in memory
void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// invalidate data cache: mark cache as invalid, next read will read from memory // invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer // Required BOTH before and after an DMA RX transfer
void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// clean and invalidate data cache // clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA // Required before an DMA transfer where memory is both read/write by DMA
void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// Controller API // Controller API

6
src/host/hcd.h
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@ -110,15 +110,15 @@ typedef struct
// clean/flush data cache: write cache -> memory. // clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory // Required before an DMA TX transfer to make sure data is in memory
void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK; void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// invalidate data cache: mark cache as invalid, next read will read from memory // invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer // Required BOTH before and after an DMA RX transfer
void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
// clean and invalidate data cache // clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA // Required before an DMA transfer where memory is both read/write by DMA
void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK; void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// Controller API // Controller API

23
src/portable/chipidea/ci_hs/ci_hs_imxrt.h
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@ -64,25 +64,28 @@ static const ci_hs_controller_t _ci_controller[] =
#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) #define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
//------------- DCache -------------// //------------- DCache -------------//
TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) { TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
return !(0x20000000 <= addr && addr < 0x20100000); return !(0x20000000 <= addr && addr < 0x20100000);
} }
TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, uint32_t data_size) {
if (imxrt_is_cache_mem((uint32_t) addr)) { const uintptr_t addr32 = (uintptr_t) addr;
SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size); if (imxrt_is_cache_mem(addr32)) {
SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
} }
} }
TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
if (imxrt_is_cache_mem((uint32_t) addr)) { const uintptr_t addr32 = (uintptr_t) addr;
SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); if (imxrt_is_cache_mem(addr32)) {
SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
} }
} }
TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
if (imxrt_is_cache_mem((uint32_t) addr)) { const uintptr_t addr32 = (uintptr_t) addr;
SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); if (imxrt_is_cache_mem(addr32)) {
SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
} }
} }

12
src/portable/chipidea/ci_hs/dcd_ci_hs.c
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@ -34,15 +34,15 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "ci_hs_imxrt.h" #include "ci_hs_imxrt.h"
void dcd_dcache_clean(void* addr, uint32_t data_size) { void dcd_dcache_clean(void const* addr, uint32_t data_size) {
imxrt_dcache_clean(addr, data_size); imxrt_dcache_clean(addr, data_size);
} }
void dcd_dcache_invalidate(void* addr, uint32_t data_size) { void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_invalidate(addr, data_size); imxrt_dcache_invalidate(addr, data_size);
} }
void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_clean_invalidate(addr, data_size); imxrt_dcache_clean_invalidate(addr, data_size);
} }
@ -58,15 +58,15 @@
#error "Unsupported MCUs" #error "Unsupported MCUs"
#endif #endif
TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) { TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) { TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
#endif #endif

6
src/portable/chipidea/ci_hs/hcd_ci_hs.c
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@ -41,15 +41,15 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "ci_hs_imxrt.h" #include "ci_hs_imxrt.h"
void hcd_dcache_clean(void* addr, uint32_t data_size) { void hcd_dcache_clean(void const* addr, uint32_t data_size) {
imxrt_dcache_clean(addr, data_size); imxrt_dcache_clean(addr, data_size);
} }
void hcd_dcache_invalidate(void* addr, uint32_t data_size) { void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_invalidate(addr, data_size); imxrt_dcache_invalidate(addr, data_size);
} }
void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_clean_invalidate(addr, data_size); imxrt_dcache_clean_invalidate(addr, data_size);
} }

8
src/portable/ehci/ehci.c
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@ -162,15 +162,15 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
static inline ehci_link_t* list_next (ehci_link_t const *p_link); static inline ehci_link_t* list_next (ehci_link_t const *p_link);
TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) { TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) { TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size; (void) addr; (void) data_size;
} }
@ -461,7 +461,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
qtd_init(td, setup_packet, 8); qtd_init(td, setup_packet, 8);
td->pid = EHCI_PID_SETUP; td->pid = EHCI_PID_SETUP;
hcd_dcache_clean((void *) setup_packet, 8); hcd_dcache_clean(setup_packet, 8);
// attach TD to QHD -> start transferring // attach TD to QHD -> start transferring
qhd_attach_qtd(qhd, td); qhd_attach_qtd(qhd, td);