fix redundant-decls warnings with USART_Printf_Init()

This commit is contained in:
hathach 2023-01-12 12:30:18 +07:00
parent e61d4aefe6
commit 658897cf4e
5 changed files with 5 additions and 9 deletions

View File

@ -75,7 +75,7 @@ void uart_sync(void)
} }
void USART_Printf_Init(uint32_t baudrate) void usart_printf_init(uint32_t baudrate)
{ {
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
USART_InitTypeDef USART_InitStructure; USART_InitTypeDef USART_InitStructure;

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@ -28,4 +28,4 @@
void uart_write(char c); void uart_write(char c);
void uart_sync(void); void uart_sync(void);
void USART_Printf_Init(uint32_t baudrate); void usart_printf_init(uint32_t baudrate);

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@ -10,7 +10,7 @@
#ifndef __CH32V30x_IT_H #ifndef __CH32V30x_IT_H
#define __CH32V30x_IT_H #define __CH32V30x_IT_H
#include "debug.h" // #include "debug.h"
#endif /* __CH32V30x_IT_H */ #endif /* __CH32V30x_IT_H */

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@ -68,7 +68,7 @@ void board_init(void) {
SysTick_Config(SystemCoreClock / 1000); SysTick_Config(SystemCoreClock / 1000);
#endif #endif
USART_Printf_Init(115200); usart_printf_init(115200);
RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY); RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE); RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);

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@ -30,9 +30,6 @@ CFLAGS += \
-Xlinker --gc-sections \ -Xlinker --gc-sections \
-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
# caused by extra void USART_Printf_Init() in debug_uart.h and EVT/EXAME/SRC/DEBUG/debug.h
CFLAGS += -Wno-error=redundant-decls
LDFLAGS += \ LDFLAGS += \
-Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs
@ -49,8 +46,7 @@ SRC_S += \
INC += \ INC += \
$(TOP)/$(BOARD_PATH) \ $(TOP)/$(BOARD_PATH) \
$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc \ $(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc
$(TOP)/$(CH32V307_SDK_SRC)/Debug
# For freeRTOS port source # For freeRTOS port source
FREERTOS_PORT = RISC-V FREERTOS_PORT = RISC-V