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https://github.com/hathach/tinyusb.git
synced 2025-03-29 19:20:22 +00:00
remove CFG_TUD_CDC_FLUSH_ON_SOF option
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583326e535
commit
61e4a8c3d3
@ -87,11 +87,6 @@
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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// TX is sent automatically every Start of Frame event.
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// If not enabled, application must call tud_cdc_write_flush() periodically
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#define CFG_TUD_CDC_FLUSH_ON_SOF 1
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// USB RAM PLACEMENT
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// USB RAM PLACEMENT
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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@ -101,10 +101,6 @@
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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// TX is sent automatically every Start of Frame event.
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// If not enabled, application must call tud_cdc_write_flush() periodically
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#define CFG_TUD_CDC_FLUSH_ON_SOF 0
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// MSC
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// MSC
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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@ -101,10 +101,6 @@
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_RX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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#define CFG_TUD_CDC_TX_BUFSIZE 64
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// TX is sent automatically every Start of Frame event.
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// If not enabled, application must call tud_cdc_write_flush() periodically
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#define CFG_TUD_CDC_FLUSH_ON_SOF 0
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// MSC
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// MSC
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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@ -85,12 +85,6 @@
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#define CFG_TUD_CDC_RX_BUFSIZE 128
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#define CFG_TUD_CDC_RX_BUFSIZE 128
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#define CFG_TUD_CDC_TX_BUFSIZE 128
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#define CFG_TUD_CDC_TX_BUFSIZE 128
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// TX is sent automatically in Start of Frame event.
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// If not enabled, application must call tud_cdc_write_flush() periodically
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#define CFG_TUD_CDC_FLUSH_ON_SOF 1
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// Number of supported Logical Unit Number (At least 1)
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// Number of supported Logical Unit Number (At least 1)
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#define CFG_TUD_MSC_MAXLUN 1
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#define CFG_TUD_MSC_MAXLUN 1
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@ -90,7 +90,7 @@ CFG_TUSB_ATTR_USBRAM static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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bool tud_cdc_n_connected(uint8_t itf)
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bool tud_cdc_n_connected(uint8_t itf)
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{
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{
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// DTR (bit 0) active isconsidered as connected
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// DTR (bit 0) active is considered as connected
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return BIT_TEST_(_cdcd_itf[itf].line_state, 0);
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return BIT_TEST_(_cdcd_itf[itf].line_state, 0);
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}
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}
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@ -348,14 +348,4 @@ tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
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return TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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}
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#if CFG_TUD_CDC_FLUSH_ON_SOF
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void cdcd_sof(uint8_t rhport)
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{
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for(uint8_t i=0; i<CFG_TUD_CDC; i++)
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{
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tud_cdc_n_flush(i);
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}
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}
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#endif
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#endif
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#endif
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@ -116,12 +116,6 @@ tusb_error_t cdcd_control_request_st (uint8_t rhport, tusb_control_request_t con
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tusb_error_t cdcd_xfer_cb (uint8_t rhport, uint8_t edpt_addr, tusb_event_t event, uint32_t xferred_bytes);
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tusb_error_t cdcd_xfer_cb (uint8_t rhport, uint8_t edpt_addr, tusb_event_t event, uint32_t xferred_bytes);
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void cdcd_reset (uint8_t rhport);
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void cdcd_reset (uint8_t rhport);
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#if CFG_TUD_CDC_FLUSH_ON_SOF
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void cdcd_sof(uint8_t rhport);
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#else
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#define cdcd_sof NULL
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#endif
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#endif
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -261,10 +261,6 @@ void tusb_hal_nrf_power_event (uint32_t event)
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NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
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NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
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USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
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USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
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#if CFG_TUD_CDC && CFG_TUD_CDC_FLUSH_ON_SOF
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NRF_USBD->INTENSET |= USBD_INTEN_SOF_Msk;
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#endif
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// Enable interrupt, Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice
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// Enable interrupt, Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice
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NVIC_SetPriority(USBD_IRQn, USB_NVIC_PRIO);
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NVIC_SetPriority(USBD_IRQn, USB_NVIC_PRIO);
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NVIC_ClearPendingIRQ(USBD_IRQn);
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NVIC_ClearPendingIRQ(USBD_IRQn);
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