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update dwc int enable/disable

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hathach 2021-10-25 00:39:37 +07:00
parent 4ab931a361
commit 61c80840c3
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GPG Key ID: 2FA891220FBFD581
3 changed files with 38 additions and 15 deletions
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17
src/portable/synopsys/dwc2/dcd_dwc2.c
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@ -32,6 +32,7 @@
#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103))
#include "device/dcd.h"
#include "dwc2_type.h"
#if defined(DCD_ATTR_DWC2_STM32)
@ -42,17 +43,15 @@
#error "Unsupported MCUs"
#endif
#include "device/dcd.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE)
#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE)
#define DEVICE_REG(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
enum
{
@ -441,14 +440,12 @@ void dcd_init (uint8_t rhport)
void dcd_int_enable (uint8_t rhport)
{
(void) rhport;
NVIC_EnableIRQ(RHPORT_IRQn);
dcd_dwc2_int_enable(rhport);
}
void dcd_int_disable (uint8_t rhport)
{
(void) rhport;
NVIC_DisableIRQ(RHPORT_IRQn);
dcd_dwc2_int_disable(rhport);
}
void dcd_set_address (uint8_t rhport, uint8_t dev_addr)

22
src/portable/synopsys/dwc2/dwc2_gd32.h
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@ -32,26 +32,38 @@
#define __NOP() __asm volatile ("nop")
// These numbers are the same for the whole GD32VF103 family.
#define RHPORT_IRQn 86
#define DWC2_REG_BASE 0x50000000UL
#define EP_MAX 4
#define EP_FIFO_SIZE 1280
#define DWC2_REG_BASE 0x50000000UL
#define RHPORT_IRQn 86
// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
// Interrupt Controller by Nuclei. It is nearly API compatible to the
// NVIC used by ARM MCUs.
#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
#define NVIC_EnableIRQ __eclic_enable_interrupt
#define NVIC_DisableIRQ __eclic_disable_interrupt
TU_ATTR_ALWAYS_INLINE
static inline void __eclic_enable_interrupt (uint32_t irq) {
*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
}
TU_ATTR_ALWAYS_INLINE
static inline void __eclic_disable_interrupt (uint32_t irq){
*(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
}
TU_ATTR_ALWAYS_INLINE
static inline void dcd_dwc2_int_enable(uint8_t rhport)
{
(void) rhport;
__eclic_enable_interrupt(RHPORT_IRQn);
}
TU_ATTR_ALWAYS_INLINE
static inline void dcd_dwc2_int_disable (uint8_t rhport)
{
(void) rhport;
__eclic_disable_interrupt(RHPORT_IRQn);
}
#endif /* DWC2_GD32_H_ */

14
src/portable/synopsys/dwc2/dwc2_stm32.h
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@ -84,4 +84,18 @@
#endif
TU_ATTR_ALWAYS_INLINE
static inline void dcd_dwc2_int_enable(uint8_t rhport)
{
(void) rhport;
NVIC_EnableIRQ(RHPORT_IRQn);
}
TU_ATTR_ALWAYS_INLINE
static inline void dcd_dwc2_int_disable (uint8_t rhport)
{
(void) rhport;
NVIC_DisableIRQ(RHPORT_IRQn);
}
#endif /* DWC2_STM32_H_ */