mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-20 04:21:29 +00:00
commit
5f5ee465a6
@ -95,7 +95,7 @@ enum
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#define EPNUM_MSC_IN 0x85
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#elif CFG_TUSB_MCU == OPT_MCU_SAMG
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// SAMG doesn't support a same endpoint number with IN and OUT
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// SAMG doesn't support a same endpoint number with different direction IN and OUT
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// e.g EP1 OUT & EP1 IN cannot exist together
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#define EPNUM_CDC_NOTIF 0x81
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#define EPNUM_CDC_OUT 0x02
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@ -80,10 +80,20 @@ enum
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#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
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// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
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// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
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#define EPNUM_MSC 0x02
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// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
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#define EPNUM_MSC_OUT 0x02
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#define EPNUM_MSC_IN 0x82
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#elif CFG_TUSB_MCU == OPT_MCU_SAMG
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// SAMG doesn't support a same endpoint number with different direction IN and OUT
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// e.g EP1 OUT & EP1 IN cannot exist together
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#define EPNUM_MSC_OUT 0x01
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#define EPNUM_MSC_IN 0x82
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#else
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#define EPNUM_MSC 0x01
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#define EPNUM_MSC_OUT 0x01
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#define EPNUM_MSC_IN 0x81
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#endif
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uint8_t const desc_configuration[] =
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@ -92,7 +102,7 @@ uint8_t const desc_configuration[] =
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TUD_CONFIG_DESCRIPTOR(ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
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// Interface number, string index, EP Out & EP In address, EP size
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TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC, 0x80 | EPNUM_MSC, (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 512 : 64),
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TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 512 : 64),
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};
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// Invoked when received GET CONFIGURATION DESCRIPTOR
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@ -335,25 +335,34 @@ bool cdcd_control_request(uint8_t rhport, tusb_control_request_t const * request
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switch ( request->bRequest )
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{
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case CDC_REQUEST_SET_LINE_CODING:
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TU_LOG2(" Set Line Coding\n");
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tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
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break;
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case CDC_REQUEST_GET_LINE_CODING:
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TU_LOG2(" Get Line Coding\n");
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tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
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break;
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case CDC_REQUEST_SET_CONTROL_LINE_STATE:
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{
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// CDC PSTN v1.2 section 6.3.12
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// Bit 0: Indicates if DTE is present or not.
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// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
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// Bit 1: Carrier control for half-duplex modems.
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// This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
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bool const dtr = tu_bit_test(request->wValue, 0);
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bool const rts = tu_bit_test(request->wValue, 1);
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p_cdc->line_state = (uint8_t) request->wValue;
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TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\n", dtr, rts);
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tud_control_status(rhport, request);
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// Invoke callback
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if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, tu_bit_test(request->wValue, 0), tu_bit_test(request->wValue, 1));
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if ( tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, dtr, rts);
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}
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break;
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default: return false; // stall unsupported request
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@ -51,8 +51,8 @@ typedef struct
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static usbd_control_xfer_t _ctrl_xfer;
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CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
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CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
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static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
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//--------------------------------------------------------------------+
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// Application API
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@ -60,8 +60,14 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_EN
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static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
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{
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// Opposite to endpoint in Data Phase
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uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
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TU_LOG2(" XFER Endpoint: 0x%02X, Bytes: %d\n", ep_addr, 0);
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// status direction is reversed to one in the setup packet
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return dcd_edpt_xfer(rhport, request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN, NULL, 0);
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// Note: Status must always be DATA1
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return dcd_edpt_xfer(rhport, ep_addr, NULL, 0);
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}
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// Status phase
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@ -106,6 +112,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
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// Data stage
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TU_ASSERT( _data_stage_xact(rhport) );
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TU_LOG2(" XFER Endpoint: 0x%02X, Bytes: %d\n", request->bmRequestType_bit.direction ? EDPT_CTRL_IN : EDPT_CTRL_OUT, _ctrl_xfer.data_len);
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}else
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{
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// Status stage
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@ -51,6 +51,12 @@ typedef struct
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// Endpoint 0-5, each can only be either OUT or In
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xfer_desc_t _dcd_xfer[EP_COUNT];
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// Indicate that DATA Toggle for Control Status is incorrect, which must always be DATA1 by USB Specs.
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// However SAMG DToggle is read-only, therefore we must duplicate the status phase ( D0 then D1 )
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// as walk-around to resolve this. The D0 status packet is likely to be discarded by USB Host safely.
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// Note: Only needed for IN Status e.g CDC_SET_LINE_CODING, since out data is sent by host
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volatile bool _walkaround_incorrect_dtoggle_control_status;
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void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
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{
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xfer->epsize = epsize;
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@ -111,6 +117,7 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
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// Set up endpoint 0, clear all other endpoints
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static void bus_reset(void)
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{
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_walkaround_incorrect_dtoggle_control_status = false;
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tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
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xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
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@ -201,7 +208,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
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// Set new address & Function enable bit
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UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr);
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}else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
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}
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else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
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{
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// Configured State
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UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk;
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@ -248,49 +256,50 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_begin(xfer, buffer, total_bytes);
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if (dir == TUSB_DIR_IN)
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if (dir == TUSB_DIR_OUT)
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{
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// Set DIR bit for EP0
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if ( epnum == 0 ) UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
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// Clear EP0 direction bit
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if (epnum == 0) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
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// Enable interrupt when starting OUT transfer
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if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
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}
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else
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{
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if (epnum == 0)
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{
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// Previous EP0 direction is OUT --> This transfer is ZLP control status.
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) )
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{
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// Set EP0 dir bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
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// DATA Toggle is 0, USB Specs requires Status Stage must be DATA1
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// Since SAMG DToggle is read-only, we mark this and implement the walk-around
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DTGLE_Msk) )
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{
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TU_LOG2("Incorrect DATA TOGGLE, Control Status must be DATA1\n");
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// DTGLE is read-only on SAMG, this statement has no effect
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UDP->UDP_CSR[epnum] |= UDP_CSR_DTGLE_Msk;
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// WALKROUND: duplicate IN transfer to send DATA1 status packet
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// set flag for irq to skip reporting first incorrect packet
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_walkaround_incorrect_dtoggle_control_status = true;
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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while ( UDP->UDP_CSR[epnum] & UDP_CSR_TXPKTRDY_Msk ) {}
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_walkaround_incorrect_dtoggle_control_status = false;
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}
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}
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}
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xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
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// TX ready for transfer
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}
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else
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{
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// Clear DIR bit for EP0
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if ( epnum == 0 ) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
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// OUT Data may already received and acked by hardware
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// Read it as 1st packet then continue with transfer if needed
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if ( UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk) )
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{
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// uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
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// TU_LOG2("xact_len = %d\r", xact_len);
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// // Read from EP fifo
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// xact_ep_read(epnum, xfer->buffer, xact_len);
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// xfer_packet_done(xfer);
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//
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// // Clear DATA Bank0 bit
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// UDP->UDP_CSR[epnum] &= ~UDP_CSR_RX_DATA_BK0_Msk;
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//
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// if ( 0 == xfer_packet_len(xfer) )
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// {
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// // Disable OUT EP interrupt when transfer is complete
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// UDP->UDP_IER &= ~(1 << epnum);
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//
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// dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, false);
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// return true; // complete
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// }
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}
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// Enable interrupt when starting OUT transfer
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if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
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}
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return true;
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}
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@ -343,13 +352,13 @@ void dcd_isr(uint8_t rhport)
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// if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
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// Suspend
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// if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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if (intr_status & UDP_ISR_RXSUSP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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// Resume
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// if (intr_status & UDP_ISR_RXRSM_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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if (intr_status & UDP_ISR_RXRSM_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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// Wakeup
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// if (intr_status & UDP_ISR_WAKEUP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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if (intr_status & UDP_ISR_WAKEUP_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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//------------- Endpoints -------------//
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@ -368,8 +377,17 @@ void dcd_isr(uint8_t rhport)
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// notify usbd
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dcd_event_setup_received(rhport, setup, true);
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// Clear Setup bit
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UDP->UDP_CSR[0] &= ~UDP_CSR_RXSETUP_Msk;
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// Set EP direction bit according to DATA stage
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if (setup[0] & 0x80)
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{
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UDP->UDP_CSR[0] |= UDP_CSR_DIR_Msk;
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}else
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{
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UDP->UDP_CSR[0] &= ~UDP_CSR_DIR_Msk;
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}
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// Clear Setup bit & stall bit if needed
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UDP->UDP_CSR[0] &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
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return;
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}
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@ -381,7 +399,7 @@ void dcd_isr(uint8_t rhport)
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{
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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// Endpoint IN
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//------------- Endpoint IN -------------//
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if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk)
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{
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xfer_packet_done(xfer);
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@ -397,23 +415,29 @@ void dcd_isr(uint8_t rhport)
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}else
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{
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// xfer is complete
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dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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// WALKAROUND: Skip reporting this incorrect DATA Toggle status IN transfer
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if ( !(_walkaround_incorrect_dtoggle_control_status && (epnum == 0) && (xfer->actual_len == 0)) )
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{
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// xfer is complete
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dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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// Required since control OUT can happen right after before stack handle this event
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xfer_end(xfer);
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}
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}
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// Clear TX Complete bit
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
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}
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// Endpoint OUT
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// Ping-Pong is a must for Bulk/Iso
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// When both Bank0 and Bank1 are both set, there is not way to know which one comes first
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if (UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk))
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//------------- Endpoint OUT -------------//
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// Ping-Pong is a MUST for Bulk/Iso
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// NOTE: When both Bank0 and Bank1 are both set, there is no way to know which one comes first
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uint32_t const banks_complete = UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
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if (banks_complete)
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{
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uint16_t const xact_len = (uint16_t) ((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos);
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//if (epnum != 0) TU_LOG2("xact_len = %d\r", xact_len);
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// Read from EP fifo
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xact_ep_read(epnum, xfer->buffer, xact_len);
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xfer_packet_done(xfer);
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@ -423,12 +447,12 @@ void dcd_isr(uint8_t rhport)
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// Disable OUT EP interrupt when transfer is complete
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if (epnum != 0) UDP->UDP_IDR |= (1 << epnum);
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dcd_event_xfer_complete(rhport, epnum, xact_len, XFER_RESULT_SUCCESS, true);
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// xfer_end(xfer);
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dcd_event_xfer_complete(rhport, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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xfer_end(xfer);
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}
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// Clear DATA Bank0 bit
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UDP->UDP_CSR[epnum] &= ~(UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk);
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// Clear DATA Bank0/1 bit
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UDP->UDP_CSR[epnum] &= ~banks_complete;
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}
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// Stall sent to host
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