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got interrupt in working with slave
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@ -80,8 +80,9 @@ typedef struct {
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volatile bool allocated;
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uint8_t ep_id;
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union TU_ATTR_PACKED {
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uint8_t err_count : 7;
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uint8_t err_count : 6;
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uint8_t do_ping : 1;
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uint8_t sof_schedule : 1;
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};
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uint8_t result;
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@ -681,6 +682,31 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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//--------------------------------------------------------------------
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// HCD Event Handler
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//--------------------------------------------------------------------
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static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) {
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hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
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dwc2_channel_t* channel = &dwc2->channel[ch_id];
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hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id];
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if (edpt_is_periodic(channel->hcchar_bm.ep_type)){
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// for periodic, de-allocate channel, enable SOF set frame counter for later transfer
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edpt->next_pid = channel->hctsiz_bm.pid; // save PID
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edpt->frame_countdown = edpt->frame_interval;
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dwc2->gintmsk |= GINTSTS_SOF;
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if (hcint & HCINT_HALTED) {
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// already halted, de-allocate channel (called from DMA isr)
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channel_dealloc(dwc2, ch_id);
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} else {
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// disable channel first if not halted (called slave isr)
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xfer->sof_schedule = 1;
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channel_disable(dwc2, channel);
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}
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} else {
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// for control/bulk: try again immediately
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channel_send_in_token(dwc2, channel);
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}
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}
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#if CFG_TUH_DWC2_SLAVE_ENABLE
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static void handle_rxflvl_irq(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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@ -770,6 +796,8 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
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dwc2_channel_t* channel = &dwc2->channel[ch_id];
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bool is_done = false;
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// TU_LOG1("ch%u: ep = %u, hcint = 0x%04lX\r\n", ch_id, channel->hcchar_bm.ep_num, hcint);
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if (hcint & HCINT_XFER_COMPLETE) {
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xfer->result = XFER_RESULT_SUCCESS;
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channel_disable(dwc2, channel);
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@ -786,21 +814,23 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h
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channel_disable(dwc2, channel);
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} else if (hcint & HCINT_HALTED) {
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channel->hcintmsk &= ~HCINT_HALTED;
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if (xfer->result != XFER_RESULT_INVALID) {
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if (xfer->sof_schedule) {
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// de-allocate channel but does not complete xfer, we schedule it in the SOF interrupt
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channel_dealloc(dwc2, ch_id);
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} else if (xfer->result != XFER_RESULT_INVALID) {
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is_done = true;
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} else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) {
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xfer->result = XFER_RESULT_FAILED;
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is_done = true;
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} else {
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// Re-initialize Channel
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TU_ASSERT(false);
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channel_xfer_in_retry(dwc2, ch_id, hcint);
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}
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} else if (hcint & HCINT_DATATOGGLE_ERR) {
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xfer->err_count = 0;
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TU_ASSERT(false);
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} else if (hcint & HCINT_NAK) {
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// NAK received, re-enable channel if request queue is available
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channel_send_in_token(dwc2, channel);
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channel_xfer_in_retry(dwc2, ch_id, hcint);
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} else if (hcint & HCINT_ACK) {
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xfer->err_count = 0;
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channel->hcintmsk &= ~HCINT_ACK;
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@ -887,31 +917,13 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci
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xfer->result = XFER_RESULT_FAILED;
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} else {
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channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR;
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edpt->next_pid = channel->hctsiz_bm.pid; // save PID
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if (edpt_is_periodic(channel->hcchar_bm.ep_type)){
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// for periodic, de-allocate channel, enable SOF set frame counter for later transfer
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channel_dealloc(dwc2, ch_id);
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edpt->frame_countdown = edpt->frame_interval;
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dwc2->gintmsk |= GINTSTS_SOF;
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} else {
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// for control/bulk: try again immediately
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TU_ASSERT(false);
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}
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channel_xfer_in_retry(dwc2, ch_id, hcint);
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}
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} else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) {
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xfer->err_count = 0;
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channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR);
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if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) {
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edpt->next_pid = channel->hctsiz_bm.pid; // save PID
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if (edpt_is_periodic(channel->hcchar_bm.ep_type)){
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// for periodic, de-allocate channel, enable SOF set frame counter for later transfer
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channel_dealloc(dwc2, ch_id);
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edpt->frame_countdown = edpt->frame_interval;
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dwc2->gintmsk |= GINTSTS_SOF;
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} else {
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// for control/bulk: try again immediately
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TU_ASSERT(false);
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}
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channel_xfer_in_retry(dwc2, ch_id, hcint);
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}
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}
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}
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@ -1161,6 +1173,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
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dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY;
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}
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}
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if (gintsts & GINTSTS_PTX_FIFO_EMPTY) {
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// PTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written
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const bool more_ptxfe = handle_txfifo_empty(dwc2, true);
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if (!more_ptxfe) {
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// no more pending packet, disable interrupt
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dwc2->gintmsk &= ~GINTSTS_PTX_FIFO_EMPTY;
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}
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}
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#endif
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}
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