add code & test for hcd_pipe_open interrupt

high and non-highspeed

tests/test/host/ehci/test_ehci_pipe.c

@@ -60,16 +60,7 @@ uint8_t dev_addr;
 uint8_t hostid;
 
 ehci_qhd_t *async_head;
-
+ehci_qhd_t *period_head;
-tusb_descriptor_endpoint_t const desc_ept_bulk_in =
-{
-    .bLength          = sizeof(tusb_descriptor_endpoint_t),
-    .bDescriptorType  = TUSB_DESC_ENDPOINT,
-    .bEndpointAddress = 0x81,
-    .bmAttributes     = { .xfer = TUSB_XFER_BULK },
-    .wMaxPacketSize   = 512,
-    .bInterval        = 0
-};
 
 //--------------------------------------------------------------------+
 // Setup/Teardown + helper declare
@@ -92,9 +83,11 @@ void setUp(void)
     usbh_device_info_pool[i].core_id  = hostid;
     usbh_device_info_pool[i].hub_addr = hub_addr;
     usbh_device_info_pool[i].hub_port = hub_port;
+    usbh_device_info_pool[i].speed    = TUSB_SPEED_HIGH;
   }
 
   async_head =  get_async_head( hostid );
+  period_head = get_period_head( hostid );
 }
 
 void tearDown(void)
@@ -112,7 +105,7 @@ void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_pack
 
   TEST_ASSERT_EQUAL(hub_addr, p_qhd->hub_address);
   TEST_ASSERT_EQUAL(hub_port, p_qhd->hub_port);
-  TEST_ASSERT_EQUAL(1, p_qhd->mult);
+  TEST_ASSERT_EQUAL(1, p_qhd->mult); // TDD operation model for mult
 
   TEST_ASSERT_FALSE(p_qhd->qtd_overlay.halted);
   TEST_ASSERT(p_qhd->qtd_overlay.next.terminate);
@@ -132,7 +125,7 @@ void verify_control_open_qhd(ehci_qhd_t *p_qhd)
 
   TEST_ASSERT_EQUAL(1, p_qhd->data_toggle_control);
   TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
-  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
+  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
 }
 
 void test_control_open_addr0_qhd_data(void)
@@ -191,6 +184,16 @@ void test_control_open_non_highspeed(void)
 //--------------------------------------------------------------------+
 // BULK PIPE
 //--------------------------------------------------------------------+
+tusb_descriptor_endpoint_t const desc_ept_bulk_in =
+{
+    .bLength          = sizeof(tusb_descriptor_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x81,
+    .bmAttributes     = { .xfer = TUSB_XFER_BULK },
+    .wMaxPacketSize   = 512,
+    .bInterval        = 0
+};
+
 void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
 {
   verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
@@ -198,7 +201,7 @@ void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const *
   TEST_ASSERT_FALSE(p_qhd->head_list_flag);
   TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
   TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
-  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_cmask);
+  TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
   TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
 
   //  TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
@@ -220,6 +223,9 @@ void test_open_bulk_qhd_data(void)
   //------------- Code Under TEST -------------//
   pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint);
 
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_BULK, pipe_hdl.xfer_type);
+
   p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
   verify_bulk_open_qhd(p_qhd, desc_endpoint);
 
@@ -228,3 +234,74 @@ void test_open_bulk_qhd_data(void)
   TEST_ASSERT_FALSE(async_head->next.terminate);
   TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
 }
+
+//--------------------------------------------------------------------+
+// INTERRUPT PIPE
+//--------------------------------------------------------------------+
+tusb_descriptor_endpoint_t const desc_ept_interrupt_out =
+{
+    .bLength          = sizeof(tusb_descriptor_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x02,
+    .bmAttributes     = { .xfer = TUSB_XFER_INTERRUPT },
+    .wMaxPacketSize   = 16,
+    .bInterval        = 1
+};
+void verify_int_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint)
+{
+  verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
+
+  TEST_ASSERT_FALSE(p_qhd->head_list_flag);
+  TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
+  TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
+
+  //  TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
+
+  TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
+
+  //------------- period list check -------------//
+  TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(period_head->next.address));
+  TEST_ASSERT_FALSE(period_head->next.terminate);
+  TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, period_head->next.type);
+}
+
+void test_open_interrupt_qhd_hs(void)
+{
+  ehci_qhd_t *p_qhd;
+  pipe_handle_t pipe_hdl;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
+
+  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
+
+  verify_int_qhd(p_qhd, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(0xFF, p_qhd->interrupt_smask);
+  //TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask); cmask in high speed is ignored
+}
+
+void test_open_interrupt_qhd_non_hs(void)
+{
+  ehci_qhd_t *p_qhd;
+  pipe_handle_t pipe_hdl;
+
+  usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
+
+  //------------- Code Under TEST -------------//
+  pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
+  TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
+
+  p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
+
+  verify_int_qhd(p_qhd, &desc_ept_interrupt_out);
+
+  TEST_ASSERT_EQUAL(1, p_qhd->interrupt_smask);
+  TEST_ASSERT_EQUAL(0x1c, p_qhd->non_hs_interrupt_cmask);
+
+}

tests/test/host/ehci/test_ehci_structure.c

@@ -153,7 +153,7 @@ void test_qhd_structure(void)
 
   //------------- Word 2 -------------//
   TEST_ASSERT_EQUAL( 0, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, interrupt_smask) );
-  TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_cmask) );
+  TEST_ASSERT_EQUAL( 8, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, non_hs_interrupt_cmask) );
   TEST_ASSERT_EQUAL( 16, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_address) );
   TEST_ASSERT_EQUAL( 23, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, hub_port) );
   TEST_ASSERT_EQUAL( 30, BITFIELD_OFFSET_OF_UINT32(ehci_qhd_t, 2, mult) );
@@ -192,7 +192,7 @@ void test_sitd_structure(void)
 
   //------------- Word 2 -------------//
   TEST_ASSERT_EQUAL( 4*2, offsetof(ehci_sitd_t, interrupt_smask));
-  TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_cmask));
+  TEST_ASSERT_EQUAL( 4*2+1, offsetof(ehci_sitd_t, non_hs_interrupt_cmask));
 
   //------------- Word 3 -------------//
   TEST_ASSERT_EQUAL( 1, BITFIELD_OFFSET_OF_UINT32(ehci_sitd_t, 3, split_state) );

tinyusb/host/ehci/ehci.c

@@ -274,32 +274,38 @@ pipe_handle_t hcd_pipe_open(uint8_t dev_addr, tusb_descriptor_endpoint_t const *
 {
   pipe_handle_t const null_handle = { .dev_addr = 0, .xfer_type = 0, .index = 0 };
 
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_BULK)
+  uint8_t index=0;
+  while( index<EHCI_MAX_QHD && ehci_data.device[dev_addr].qhd[index].used )
   {
-    uint8_t index=0;
+    index++;
-    while( index<EHCI_MAX_QHD && ehci_data.device[dev_addr].qhd[index].used )
-    {
-      index++;
-    }
-
-    ASSERT( index < EHCI_MAX_QHD, null_handle);
-
-    ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].qhd[index];
-    memclr_(p_qhd, sizeof(ehci_qhd_t));
-
-    queue_head_init(p_qhd, dev_addr, p_endpoint_desc->wMaxPacketSize, p_endpoint_desc->bEndpointAddress, TUSB_XFER_BULK);
-
-    //------------- insert to async list -------------//
-    // TODO might need to to disable async list first
-    ehci_qhd_t * const async_head = get_async_head(usbh_device_info_pool[dev_addr].core_id);
-    p_qhd->next = async_head->next;
-    async_head->next.address = (uint32_t) p_qhd;
-    async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
-
-    return (pipe_handle_t) { .dev_addr = dev_addr, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = index};
   }
 
-  return null_handle;
+  ASSERT( index < EHCI_MAX_QHD, null_handle);
+
+  ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].qhd[index];
+  queue_head_init(p_qhd, dev_addr, p_endpoint_desc->wMaxPacketSize, p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
+
+  ehci_qhd_t * list_head;
+
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_BULK)
+  {
+    //------------- insert to async list -------------//
+    // TODO might need to to disable async list first
+    list_head = get_async_head(usbh_device_info_pool[dev_addr].core_id);
+  }else if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_INTERRUPT)
+  {
+    //------------- insert to period list -------------//
+    // TODO might need to to disable period list first
+    list_head = get_period_head(usbh_device_info_pool[dev_addr].core_id);
+  }
+
+  p_qhd->next = list_head->next;
+  list_head->next.address = (uint32_t) p_qhd;
+  list_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
+
+  return (pipe_handle_t) { .dev_addr = dev_addr, .xfer_type = p_endpoint_desc->bmAttributes.xfer, .index = index};
+
+//  return null_handle;
 }
 
 static void queue_td_init(ehci_qtd_t* p_qtd, uint32_t data_ptr, uint16_t total_bytes)
@@ -307,12 +313,12 @@ static void queue_td_init(ehci_qtd_t* p_qtd, uint32_t data_ptr, uint16_t total_b
   memclr_(p_qtd, sizeof(ehci_qtd_t));
 
   p_qtd->alternate.terminate = 1; // not used, always set to terminated
-  p_qtd->active = 1;
+  p_qtd->active              = 1;
-  p_qtd->cerr = 3; // TODO 3 consecutive errors tolerance
+  p_qtd->cerr                = 3; // TODO 3 consecutive errors tolerance
-  p_qtd->data_toggle = 0;
+  p_qtd->data_toggle         = 0;
-  p_qtd->total_bytes = total_bytes;
+  p_qtd->total_bytes         = total_bytes;
 
-  p_qtd->buffer[0] = data_ptr;
+  p_qtd->buffer[0]           = data_ptr;
 
 }
 
@@ -384,6 +390,8 @@ static inline tusb_std_request_t* const get_control_request_ptr(uint8_t dev_addr
 
 static void queue_head_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type)
 {
+  memclr_(p_qhd, sizeof(ehci_qhd_t));
+
   p_qhd->device_address          = dev_addr;
   p_qhd->inactive_next_xact      = 0;
   p_qhd->endpoint_number         = endpoint_addr & 0x0F;
@@ -394,8 +402,15 @@ static void queue_head_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_pa
   p_qhd->non_hs_control_endpoint = ((TUSB_XFER_CONTROL == xfer_type) && (usbh_device_info_pool[dev_addr].speed != TUSB_SPEED_HIGH) )  ? 1 : 0;
   p_qhd->nak_count_reload        = 0;
 
-  p_qhd->interrupt_smask         = 0;
+  // Bulk/Control -> smask = cmask = 0
-  p_qhd->non_hs_cmask            = 0;
+  if (TUSB_XFER_INTERRUPT == xfer_type)
+  {
+    // Highspeed: schedule every uframe (1 us interval); Full/Low: schedule only 1st frame
+    p_qhd->interrupt_smask         = (TUSB_SPEED_HIGH == usbh_device_info_pool[dev_addr].speed) ? 0xFF : 0x01;
+    // Highspeed: ignored by Host Controller, Full/Low: 4.12.2.1 (EHCI) case 1 schedule complete split at 2,3,4 uframe
+    p_qhd->non_hs_interrupt_cmask  = BIN8(11100);
+  }
+
   p_qhd->hub_address             = usbh_device_info_pool[dev_addr].hub_addr;
   p_qhd->hub_port                = usbh_device_info_pool[dev_addr].hub_port;
   p_qhd->mult                    = 1; // TODO not use high bandwidth/park mode yet

tinyusb/host/ehci/ehci.h

@@ -180,7 +180,7 @@ typedef struct {
 
 	/// Word 2                       : Endpoint Capabilities
 	uint32_t interrupt_smask         : 8  ; ///< This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint
-	uint32_t non_hs_cmask            : 8  ; ///<  This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction
+	uint32_t non_hs_interrupt_cmask  : 8  ; ///<  This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction
 	uint32_t hub_address             : 7  ; ///< This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. See Section 4.12.
 	uint32_t hub_port                : 7  ; ///<  This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addrbelow), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. See Section 4.12.
 	uint32_t mult                    : 2  ; ///<  This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. 00b=Reserved 01b,10b,11b= 1 (2, 3) Transaction for this endpoint/micro frame
@@ -255,7 +255,7 @@ typedef struct {
 
 	/// Word 2: Micro-frame Schedule Control
 	uint8_t interrupt_smask     ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions
-	uint8_t non_hs_cmask     ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
+	uint8_t non_hs_interrupt_cmask     ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions.
 	uint16_t reserved ; ///< reserved
 	// End of Word 2