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stm32f4: Implement STALL logic for endpoints.

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This commit is contained in:
William D. Jones 2019-02-08 16:46:12 -05:00
parent 5526d840a8
commit 5a34a9de69
1 changed files with 88 additions and 26 deletions
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114
src/portable/stm/stm32f4/dcd_stm32f4.c
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@ -274,49 +274,110 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
{ {
(void) rhport; (void) rhport;
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
// control is never got halted // control is never got halted
if ( ep_addr == 0 ) { if(ep_addr == 0) {
return false; return false;
} }
// uint8_t const epnum = edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
// UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum]; uint8_t const dir = tu_edpt_dir(ep_addr);
// return (edpt_dir(ep_addr) == TUSB_DIR_IN ) ? ep->EPINTFLAG.bit.STALL1 : ep->EPINTFLAG.bit.STALL0; bool stalled = false;
return true;
if(dir == TUSB_DIR_IN) {
stalled = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_STALL_Msk);
} else {
stalled = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_STALL_Msk);
}
return stalled;
} }
// TODO: The logic for STALLing and disabling an endpoint is very similar
// (send STALL versus NAK handshakes back). Refactor into resuable function.
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
{ {
(void) rhport; (void) rhport;
USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
// uint8_t const epnum = edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
// UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum]; uint8_t const dir = tu_edpt_dir(ep_addr);
//
// if (edpt_dir(ep_addr) == TUSB_DIR_IN) { if(dir == TUSB_DIR_IN) {
// ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1; // Stop transmitting packets and NAK IN xfers.
// } else { in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
// ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0; while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
//
// // for control, stall both IN & OUT // Disable the endpoint. Note that both SNAK and STALL are set here.
// if (ep_addr == 0) { in_ep[epnum].DIEPCTL |= (USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_STALL | \
// ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1; USB_OTG_DIEPCTL_EPDIS);
// } while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
// } in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
// Flush the FIFO, and wait until we have confirmed it cleared.
USB_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
while((USB_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
} else {
// Asserting GONAK is required to STALL an OUT endpoint.
// Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
// anyway, and it can't be cleared by user code. If this while loop never
// finishes, we have bigger problems than just the stack.
dev->DCTL |= USB_OTG_DCTL_SGONAK;
while((USB_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
// Ditto here- disable the endpoint. Note that only STALL and not SNAK
// is set here.
out_ep[epnum].DOEPCTL |= (USB_OTG_DOEPCTL_STALL | USB_OTG_DOEPCTL_EPDIS);
while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
// Allow other OUT endpoints to keep receiving.
dev->DCTL |= USB_OTG_DCTL_CGONAK;
}
} }
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
{ {
(void) rhport; (void) rhport;
USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
// uint8_t const epnum = edpt_number(ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr);
// UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum]; uint8_t const dir = tu_edpt_dir(ep_addr);
// TODO: Figure out what happens when none of EPENA, SNAK, or STALL are
// set. Per manual, page 1364 of rev 17, for OUT endpoints,
// you set STALL _instead of_ SNAK when disabling an endpoint during a STALL.
// This means when stall is cleared, none of the above bits are set?
// //
// if (edpt_dir(ep_addr) == TUSB_DIR_IN) { // Contrast to IN endpoints, where page 1372 instructs you to set STALL
// ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1; // _and_ SNAK when STALLing IN endpoints.
// } else { if(dir == TUSB_DIR_IN) {
// ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0; in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
// }
uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> \
USB_OTG_DIEPCTL_EPTYP_Pos;
// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
// and bulk endpoints.
if(eptype == 2 || eptype == 3) {
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
}
} else {
out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> \
USB_OTG_DOEPCTL_EPTYP_Pos;
// Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
// and bulk endpoints.
if(eptype == 2 || eptype == 3) {
out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
}
}
} }
bool dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr)
@ -341,6 +402,7 @@ bool dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr)
xferring = (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_PKTCNT_Msk); xferring = (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_PKTCNT_Msk);
} }
// TODO: Also check that endpoint is active (not just enabled)?
return (enabled && xferring); return (enabled && xferring);
} }