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Merge pull request #717 from jgressmann/feat/same54xplainedpro-free-pll1
SAM E54 XPlained Pro: free PLL1 for application
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Ha Thach
GitHub
commit
59d0d255d8
@ -1,6 +1,6 @@
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DEPS_SUBMODULES += hw/mcu/microchip
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CONF_CPU_FREQUENCY ?= 120000000
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CONF_CPU_FREQUENCY ?= 48000000
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CFLAGS += \
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-mthumb \
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@ -12,9 +12,9 @@ CFLAGS += \
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-nostdlib -nostartfiles \
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-D__SAME54P20A__ \
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-DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
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-DCFG_TUSB_MCU=OPT_MCU_SAME5X
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-DCFG_TUSB_MCU=OPT_MCU_SAME5X \
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-DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
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# -DSVC_Handler=SVCall_Handler
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
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@ -58,9 +58,20 @@ void USB_3_Handler(void)
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#define LED_PIN PIN_PC18
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#define BUTTON_PIN PIN_PB31
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#define BOARD_SERCOM SERCOM2
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#define BOARD_NAME "Microchip SAM E54 Xplained Pro"
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static inline void init_clock(void)
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/** Initializes the clocks from the external 12 MHz crystal
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*
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* The goal of this setup is to preserve the second PLL
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* for the application code while still having a reasonable
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* 48 MHz clock for USB / UART.
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*
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* GCLK0: CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
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* GCLK1: unused
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* GCLK2: 12 MHz from XOSC1
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* DFLL48M: closed loop from GLCK2
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* GCLK3: 48 MHz
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*/
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static inline void init_clock_xtal(void)
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{
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/* configure for a 12MHz crystal connected to XIN1/XOUT1 */
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OSCCTRL->XOSCCTRL[1].reg =
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@ -72,16 +83,11 @@ static inline void init_clock(void)
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OSCCTRL_XOSCCTRL_ENABLE;
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while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(5) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 12 = 1Mhz, input = XOSC1 */
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000)-1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
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OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(2) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 6 = 2Mhz, input = XOSC1 */
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OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000 / 2) - 1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
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OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
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OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(5) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 12 = 1Mhz, input = XOSC1 */
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OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
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OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
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while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
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/* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
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GCLK->GENCTRL[0].reg =
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GCLK_GENCTRL_DIV(0) |
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@ -91,23 +97,47 @@ static inline void init_clock(void)
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GCLK_GENCTRL_IDC;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
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/* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
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GCLK->GENCTRL[1].reg =
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// configure GCLK2 for 12MHz from XOSC1
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GCLK->GENCTRL[2].reg =
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GCLK_GENCTRL_DIV(0) |
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GCLK_GENCTRL_RUNSTDBY |
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GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_DPLL1 |
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GCLK_GENCTRL_IDC ;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
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GCLK_GENCTRL_SRC_XOSC1 |
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GCLK_GENCTRL_IDC;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
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/* setup DFLL48M to use GLCK2 */
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
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OSCCTRL->DFLLCTRLA.reg = 0;
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while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
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OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_MODE | OSCCTRL_DFLLCTRLB_WAITLOCK;
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OSCCTRL->DFLLMUL.bit.MUL = 4; // 4 * 12MHz -> 48MHz
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OSCCTRL->DFLLCTRLA.reg =
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OSCCTRL_DFLLCTRLA_ENABLE |
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OSCCTRL_DFLLCTRLA_RUNSTDBY;
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while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
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// setup 48 MHz GCLK3 from DFLL48M
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GCLK->GENCTRL[3].reg =
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GCLK_GENCTRL_DIV(0) |
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GCLK_GENCTRL_RUNSTDBY |
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GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_DFLL |
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GCLK_GENCTRL_IDC;
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
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}
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/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
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static inline void uart_init(void)
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{
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gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
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gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
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MCLK->APBBMASK.bit.SERCOM2_ = 1;
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GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK1 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK1 -> 48MHz */
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GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
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BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
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while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
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@ -127,7 +157,7 @@ static inline void uart_init(void)
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// BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
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BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
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BOARD_SERCOM->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
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BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
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while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
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}
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@ -135,7 +165,7 @@ static inline void uart_send_buffer(uint8_t const *text, size_t len)
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{
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for (size_t i = 0; i < len; ++i) {
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BOARD_SERCOM->USART.DATA.reg = text[i];
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while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
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while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
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}
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}
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@ -143,14 +173,15 @@ static inline void uart_send_str(const char* text)
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{
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while (*text) {
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BOARD_SERCOM->USART.DATA.reg = *text++;
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while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
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while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
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}
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}
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void board_init(void)
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{
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init_clock();
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// Uncomment this line and change the GCLK for UART/USB to run off the XTAL.
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// init_clock_xtal();
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SystemCoreClock = CONF_CPU_FREQUENCY;
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@ -201,7 +232,7 @@ void board_init(void)
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* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
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* for low speed and full speed operation.
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*/
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hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
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hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
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hri_mclk_set_AHBMASK_USB_bit(MCLK);
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hri_mclk_set_APBBMASK_USB_bit(MCLK);
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