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ehci clean up
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@ -80,7 +80,6 @@ static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLI
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static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline tusb_xfer_type_t qhd_get_xfer_type(ehci_qhd_t const * p_qhd) ATTR_ALWAYS_INLINE ATTR_PURE;
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static inline ehci_qhd_t* qhd_get_from_pipe_handle(uint8_t dev_addr, pipe_handle_t pipe_hdl);
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static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd);
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// determine if a queue head has bus-related error
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static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
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@ -91,7 +90,6 @@ static inline bool qhd_has_xact_error(ehci_qhd_t * p_qhd)
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static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
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static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd ) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new) ATTR_ALWAYS_INLINE;
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@ -557,30 +555,30 @@ static void async_advance_isr(ehci_qhd_t * const async_head)
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_usbh_devices[0].state = TUSB_DEVICE_STATE_UNPLUG;
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}
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for(uint8_t relative_dev_addr=0; relative_dev_addr < CFG_TUSB_HOST_DEVICE_MAX; relative_dev_addr++)
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for(uint8_t dev_addr=1; dev_addr < CFG_TUSB_HOST_DEVICE_MAX; dev_addr++)
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{
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// check if control endpoint is removing
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ehci_qhd_t *p_control_qhd = &ehci_data.device[relative_dev_addr].control.qhd;
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ehci_qhd_t *p_control_qhd = get_control_qhd(dev_addr);
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if ( p_control_qhd->is_removing )
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{
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p_control_qhd->is_removing = 0;
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p_control_qhd->used = 0;
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// Host Controller has cleaned up its cached data for this device, set state to unplug
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_usbh_devices[relative_dev_addr+1].state = TUSB_DEVICE_STATE_UNPLUG;
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_usbh_devices[dev_addr+1].state = TUSB_DEVICE_STATE_UNPLUG;
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for (uint8_t i=0; i<HCD_MAX_ENDPOINT; i++) // free all qhd
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{
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ehci_data.device[relative_dev_addr].qhd[i].used = 0;
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ehci_data.device[relative_dev_addr].qhd[i].is_removing = 0;
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ehci_data.device[dev_addr].qhd[i].used = 0;
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ehci_data.device[dev_addr].qhd[i].is_removing = 0;
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}
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for (uint8_t i=0; i<HCD_MAX_XFER; i++) // free all qtd
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{
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ehci_data.device[relative_dev_addr].qtd[i].used = 0;
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ehci_data.device[dev_addr].qtd[i].used = 0;
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}
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// TODO free all itd & sitd
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}
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} // end for device[] loop
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}
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}
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static void port_connect_status_change_isr(uint8_t hostid)
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@ -827,7 +825,7 @@ static inline ehci_registers_t* get_operational_register(uint8_t hostid)
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//------------- queue head helper -------------//
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static inline ehci_qhd_t* get_async_head(uint8_t hostid)
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{
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return &ehci_data.dev0.qhd;
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return get_control_qhd(0);
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}
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#if EHCI_PERIODIC_LIST // TODO refractor/group this together
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@ -839,13 +837,11 @@ static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms)
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static inline ehci_qhd_t* get_control_qhd(uint8_t dev_addr)
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{
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return (dev_addr == 0) ?
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get_async_head( _usbh_devices[dev_addr].rhport ) :
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&ehci_data.device[dev_addr-1].control.qhd;
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return &ehci_data.control[dev_addr].qhd;
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}
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static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
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{
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return (dev_addr == 0) ? &ehci_data.dev0.qtd : &ehci_data.device[ dev_addr-1 ].control.qtd;
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return &ehci_data.control[dev_addr].qtd;
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}
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static inline ehci_qhd_t* qhd_find_free (uint8_t dev_addr)
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@ -880,20 +876,6 @@ static inline ehci_qhd_t* qhd_get_from_pipe_handle(uint8_t dev_addr, pipe_handle
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return &ehci_data.device[dev_addr-1].qhd[pipe_hdl.index];
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}
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static inline pipe_handle_t qhd_create_pipe_handle(ehci_qhd_t const * p_qhd)
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{
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pipe_handle_t pipe_hdl = { };
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// TODO Isochronous transfer support
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if (TUSB_XFER_CONTROL != p_qhd->xfer_type) // qhd index for control is meaningless
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{
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pipe_hdl.index = qhd_get_index(p_qhd);
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pipe_hdl.ep_addr = edpt_addr(p_qhd->endpoint_number, p_qhd->pid_non_control == EHCI_PID_IN ? 1 : 0);
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}
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return pipe_hdl;
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}
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//------------- TD helper -------------//
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static inline ehci_qtd_t* qtd_find_free(uint8_t dev_addr)
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{
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@ -456,17 +456,13 @@ typedef struct
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// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
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ehci_qhd_t period_head_arr[4];
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struct {
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ehci_qhd_t qhd; // also used as head of async list (each for 1 controller), always exists
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ehci_qtd_t qtd;
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}dev0;
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struct {
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// Note control qhd of dev0 is used as head of async list, always exists
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struct {
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ehci_qhd_t qhd;
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ehci_qtd_t qtd;
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}control;
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}control[CFG_TUSB_HOST_DEVICE_MAX+1];
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struct {
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ehci_qhd_t qhd[HCD_MAX_ENDPOINT] ; ///< Queue Head Pool
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ehci_qtd_t qtd[HCD_MAX_XFER] ATTR_ALIGNED(32) ; ///< Queue Element Transfer Pool
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// ehci_itd_t itd[EHCI_MAX_ITD] ; ///< Iso Transfer Pool
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@ -87,15 +87,17 @@ enum {
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HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
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};
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//#define HCD_MAX_ENDPOINT 16
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//#define HCD_MAX_XFER 16
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#endif
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF
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//--------------------------------------------------------------------+
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typedef struct {
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uint8_t ep_addr;
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uint8_t index;
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uint8_t reserved[2];
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uint8_t reserved[3];
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} pipe_handle_t;
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static inline bool pipehandle_is_valid(pipe_handle_t pipe_hdl)
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@ -273,7 +273,7 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t ev
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}
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else
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{
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TU_ASSERT(false, ); // something wrong, no one claims the isr's source
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TU_BREAKPOINT(); // something wrong, no one claims the isr's source
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}
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}
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}
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