From c2bbcc9f60a2b7293fad4e24468d3f045fde28ee Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 26 Dec 2023 20:14:03 +0100
Subject: [PATCH 01/19] initial support of CH34x CDC device

---
 examples/host/cdc_msc_hid/src/tusb_config.h   |   1 +
 .../cdc_msc_hid_freertos/src/tusb_config.h    |   1 +
 src/class/cdc/cdc_host.c                      | 466 +++++++++++++++++-
 src/class/cdc/serial/ch34x.h                  | 113 +++++
 src/tusb_option.h                             |  17 +
 5 files changed, 595 insertions(+), 3 deletions(-)
 create mode 100644 src/class/cdc/serial/ch34x.h

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 61abb85eb..76d59c316 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -105,6 +105,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index c661f47be..bb7c3388d 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -110,6 +110,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a6dfb45ae..9b5186e0c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Heiko Kuester (CH34x support)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -69,7 +70,16 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
+  #if CFG_TUH_CDC_CH34X
+  struct {
+    uint32_t  baud_rate;
+    uint8_t   mcr;
+    uint8_t   msr;
+    uint8_t   lcr;
+    uint32_t  quirks;
+    uint8_t   version;
+  } ch34x;
+  #endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -121,6 +131,23 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
+//------------- CH34x prototypes -------------//
+#if CFG_TUH_CDC_CH34X
+#include "serial/ch34x.h"
+
+static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
+enum {
+  CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
+};
+
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
+static void ch34x_process_config ( tuh_xfer_t* xfer );
+
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+#endif
+
+
 enum {
   SERIAL_DRIVER_ACM = 0,
 
@@ -131,6 +158,10 @@ enum {
 #if CFG_TUH_CDC_CP210X
   SERIAL_DRIVER_CP210X,
 #endif
+
+#if CFG_TUH_CDC_CH34X
+  SERIAL_DRIVER_CH34X,
+#endif
 };
 
 typedef struct {
@@ -159,6 +190,13 @@ static const cdch_serial_driver_t serial_drivers[] = {
     .set_baudrate           = cp210x_set_baudrate
   },
   #endif
+
+  #if CFG_TUH_CDC_CH34X
+  { .process_set_config     = ch34x_process_config,
+    .set_control_line_state = ch34x_set_modem_ctrl,
+    .set_baudrate           = ch34x_set_baudrate
+  },
+#endif
 };
 
 enum {
@@ -426,6 +464,12 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
         break;
       #endif
 
+      #if CFG_TUH_CDC_CH34X
+      case SERIAL_DRIVER_CH34X:
+        TU_ASSERT(false, ); // see special ch34x_control_complete function
+        break;
+      #endif
+
       default: break;
     }
   }
@@ -641,7 +685,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   {
     return acm_open(daddr, itf_desc, max_len);
   }
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
   else if ( 0xff == itf_desc->bInterfaceClass )
   {
     uint16_t vid, pid;
@@ -666,8 +710,16 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
       }
     }
     #endif
+
+    #if CFG_TUH_CDC_CH34X
+    for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) {
+      if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) {
+        return ch34x_open(daddr, itf_desc, max_len);
+      }
+    }
+    #endif
   }
-  #endif
+  #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
 
   return false;
 }
@@ -1176,4 +1228,412 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #endif
 
+//--------------------------------------------------------------------+
+// CH34x
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CH34X
+
+enum {
+  CONFIG_CH34X_STEP1 = 0,
+  CONFIG_CH34X_STEP2,
+  CONFIG_CH34X_STEP3,
+  CONFIG_CH34X_STEP4,
+  CONFIG_CH34X_STEP5,
+  CONFIG_CH34X_STEP6,
+  CONFIG_CH34X_STEP7,
+  CONFIG_CH34X_STEP8,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
+{
+  // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
+  TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
+  TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
+
+  cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
+  TU_VERIFY ( p_cdc );
+
+  TU_LOG_DRV ( "CH34x opened\r\n" );
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair ( p_cdc, desc_ep );
+}
+
+static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  tusb_control_request_t const request_setup = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_VENDOR,
+          .direction = direction
+      },
+      .bRequest = request,
+      .wValue   = tu_htole16 ( value ),
+      .wIndex   = tu_htole16 ( index ),
+      .wLength  = tu_htole16 ( length )
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if ( buffer && length > 0 ) {
+    enum_buf = usbh_get_enum_buf();
+    tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length );
+  }
+
+  tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request_setup,
+      .buffer      = enum_buf,
+      .complete_cb = complete_cb,
+      // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+  };
+
+  return tuh_control_xfer ( &xfer );
+  return false;
+}
+
+static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
+}
+
+static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
+}
+
+static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
+}
+
+static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+}
+
+/*
+ * The device line speed is given by the following equation:
+ *
+ *  baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
+ *
+ *    0 <= ps <= 3,
+ *    0 <= fact <= 1,
+ *    2 <= div <= 256 if fact = 0, or
+ *    9 <= div <= 256 if fact = 1
+ */
+// calculate baudrate devisors
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
+{
+  uint32_t fact, div, clk_div;
+  bool force_fact0 = false;
+  int32_t ps;
+  static const uint32_t ch341_min_rates[] = {
+      CH341_MIN_RATE(0),
+      CH341_MIN_RATE(1),
+      CH341_MIN_RATE(2),
+      CH341_MIN_RATE(3),
+  };
+
+  /*
+   * Clamp to supported range, this makes the (ps < 0) and (div < 2)
+   * sanity checks below redundant.
+   */
+  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
+  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
+  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
+  speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
+
+  /*
+   * Start with highest possible base clock (fact = 1) that will give a
+   * divisor strictly less than 512.
+   */
+  fact = 1;
+  for (ps = 3; ps >= 0; ps--) {
+    if (speed > ch341_min_rates[ps])
+      break;
+  }
+
+  if (ps < 0)
+    return -EINVAL;
+
+  /* Determine corresponding divisor, rounding down. */
+  clk_div = CH341_CLK_DIV(ps, fact);
+  div = CH341_CLKRATE / (clk_div * speed);
+
+  /* Some devices require a lower base clock if ps < 3. */
+  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
+    force_fact0 = true;
+
+  /* Halve base clock (fact = 0) if required. */
+  if (div < 9 || div > 255 || force_fact0) {
+    div /= 2;
+    clk_div *= 2;
+    fact = 0;
+  }
+
+  if (div < 2)
+    return -EINVAL;
+
+  /*
+   * Pick next divisor if resulting rate is closer to the requested one,
+   * scale up to avoid rounding errors on low rates.
+   */
+  if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
+      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
+    div++;
+
+  /*
+   * Prefer lower base clock (fact = 0) if even divisor.
+   *
+   * Note that this makes the receiver more tolerant to errors.
+   */
+  if (fact == 1 && div % 2 == 0) {
+    div /= 2;
+    fact = 0;
+  }
+
+  return (0x100 - div) << 8 | fact << 2 | ps;
+}
+
+// set baudrate (low level)
+// do not confuse with ch34x_set_baudrate
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  int val;
+
+  if (!baud_rate)
+    return -EINVAL;
+
+  val = ch341_get_divisor(p_cdc, baud_rate);
+  if (val < 0)
+    return -EINVAL;
+
+  /*
+   * CH341A buffers data until a full endpoint-size packet (32 bytes)
+   * has been received unless bit 7 is set.
+   *
+   * At least one device with version 0x27 appears to have this bit
+   * inverted.
+   */
+  if ( p_cdc->ch34x.version > 0x27 )
+    val |= BIT(7);
+
+  return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
+}
+
+// set lcr register
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  /*
+   * Chip versions before version 0x30 as read using
+   * CH341_REQ_READ_VERSION used separate registers for line control
+   * (stop bits, parity and word length). Version 0x30 and above use
+   * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
+   */
+  if ( p_cdc->ch34x.version < 0x30 )
+    return 0;
+
+  return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
+}
+
+// set handshake (modem controls)
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
+}
+
+// detect quirks (special versions of CH34x)
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  /*
+   * A subset of CH34x devices does not support all features. The
+   * prescaler is limited and there is no support for sending a RS232
+   * break condition. A read failure when trying to set up the latter is
+   * used to detect these devices.
+   */
+  switch ( step )
+  {
+  case 1:
+    p_cdc->ch34x.quirks = 0;
+    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
+    break;
+  case 2:
+    if ( xfer->result != XFER_RESULT_SUCCESS )
+      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
+    return true;
+    break;
+  default:
+    TU_ASSERT ( false ); // suspicious step
+    break;
+  }
+}
+
+// internal control complete to update state such as line state, encoding
+// CH34x needs a special interface recovery due to abnormal wIndex usage
+static void ch34x_control_complete(tuh_xfer_t* xfer)
+{
+  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t  *p_cdc  = get_itf ( idx );
+  TU_ASSERT ( p_cdc, );
+  TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    switch (xfer->setup->bRequest) {
+    case CH341_REQ_WRITE_REG: { // register write request
+      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
+      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
+        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+        break;
+      }
+      default: {
+        TU_ASSERT(false, ); // unexpected register write
+        break;
+      }
+      }
+      break;
+    }
+    default: {
+      TU_ASSERT(false, ); // unexpected request
+      break;
+    }
+    }
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb)
+      xfer->complete_cb(xfer);
+  }
+}
+
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
+{
+  TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
+  uint32_t baud_le = tu_htole32(baudrate);
+  p_cdc->ch34x.baud_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
+}
+
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
+  // todo later
+  return false;
+}
+
+static void ch34x_process_config ( tuh_xfer_t* xfer )
+{
+  uintptr_t const   state   = xfer->user_data & 0xff;
+  // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t  *p_cdc  = get_itf ( idx );
+  uint8_t           buffer [ CH34X_BUFFER_SIZE ];
+  cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+  TU_ASSERT ( p_cdc, );
+
+  if ( state == 0 ) {
+    // defaults
+    p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE;
+    p_cdc->ch34x.mcr = 0;
+    p_cdc->ch34x.msr = 0;
+    p_cdc->ch34x.quirks = 0;
+    p_cdc->ch34x.version = 0;
+    /*
+     * Some CH340 devices appear unable to change the initial LCR
+     * settings, so set a sane 8N1 default.
+     */
+    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
+  }
+  // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
+  switch ( state ) {
+  case CONFIG_CH34X_STEP1: // request version read
+    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
+    break;
+  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
+    p_cdc->ch34x.version = xfer->buffer[0];
+    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
+    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
+    break;
+  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
+    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
+    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
+    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP6: // detect quirks step 1
+    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
+    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
+#else
+    TU_ATTR_FALLTHROUGH;
 #endif
+    break;
+  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+    switch ( line_coding.data_bits ) {
+    case 5:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+      break;
+    case 6:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+      break;
+    case 7:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+      break;
+    case 8:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      break;
+    default:
+      TU_ASSERT ( false, ); // not supported data_bits
+      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      break;
+    }
+    if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
+      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+      if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
+        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+      if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
+        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+    }
+    TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
+    if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
+      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
+    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
+#else
+    TU_ATTR_FALLTHROUGH;
+#endif
+    break;
+    case CONFIG_CH34X_COMPLETE:
+      set_config_complete ( p_cdc, idx, itf_num );
+      break;
+    default:
+      TU_ASSERT ( false, );
+      break;
+  }
+}
+
+#endif // CFG_TUH_CDC_CH34X
+
+#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
new file mode 100644
index 000000000..94e18b252
--- /dev/null
+++ b/src/class/cdc/serial/ch34x.h
@@ -0,0 +1,113 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CH34X_H_
+#define _CH34X_H_
+
+#include <stdint.h>
+
+#define BIT(nr) ( (uint32_t)1 << (nr) )
+
+#define CH34X_BUFFER_SIZE 2
+
+// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
+
+#define DEFAULT_BAUD_RATE 9600
+
+/* flags for IO-Bits */
+#define CH341_BIT_RTS (1 << 6)
+#define CH341_BIT_DTR (1 << 5)
+
+/******************************/
+/* interrupt pipe definitions */
+/******************************/
+/* always 4 interrupt bytes */
+/* first irq byte normally 0x08 */
+/* second irq byte base 0x7d + below */
+/* third irq byte base 0x94 + below */
+/* fourth irq byte normally 0xee */
+
+/* second interrupt byte */
+#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
+
+/* status returned in third interrupt answer byte, inverted in data
+   from irq */
+#define CH341_BIT_CTS 0x01
+#define CH341_BIT_DSR 0x02
+#define CH341_BIT_RI  0x04
+#define CH341_BIT_DCD 0x08
+#define CH341_BITS_MODEM_STAT 0x0f /* all bits */
+
+/* Break support - the information used to implement this was gleaned from
+ * the Net/FreeBSD uchcom.c driver by Takanori Watanabe.  Domo arigato.
+ */
+
+// USB requests
+#define CH341_REQ_READ_VERSION 0x5F // dec 95
+#define CH341_REQ_WRITE_REG    0x9A
+#define CH341_REQ_READ_REG     0x95
+#define CH341_REQ_SERIAL_INIT  0xA1
+#define CH341_REQ_MODEM_CTRL   0xA4
+
+// CH34x registers
+#define CH341_REG_BREAK        0x05
+#define CH341_REG_PRESCALER    0x12
+#define CH341_REG_DIVISOR      0x13
+#define CH341_REG_LCR          0x18
+#define CH341_REG_LCR2         0x25
+
+#define CH341_NBREAK_BITS      0x01
+
+// line control bits
+#define CH341_LCR_ENABLE_RX    0x80
+#define CH341_LCR_ENABLE_TX    0x40
+#define CH341_LCR_MARK_SPACE   0x20
+#define CH341_LCR_PAR_EVEN     0x10
+#define CH341_LCR_ENABLE_PAR   0x08
+#define CH341_LCR_STOP_BITS_2  0x04
+#define CH341_LCR_CS8          0x03
+#define CH341_LCR_CS7          0x02
+#define CH341_LCR_CS6          0x01
+#define CH341_LCR_CS5          0x00
+
+#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
+#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
+
+#define CH341_CLKRATE   48000000
+#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
+#define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
+
+/* Supported range is 46 to 3000000 bps. */
+#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
+#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
+
+#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
+// error codes
+#define EINVAL    22  /* Invalid argument */
+
+#endif /* _CH34X_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a76281c0c..13151a07b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -470,6 +470,23 @@
     0xEA60, 0xEA70
 #endif
 
+#ifndef CFG_TUH_CDC_CH34X
+  // CH34X is not part of CDC class, only to re-use CDC driver API
+  #define CFG_TUH_CDC_CH34X 0
+#endif
+
+#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST
+  // List of product IDs that can use the CH34X CDC driver
+  #define CFG_TUH_CDC_CH34X_VID_PID_LIST \
+    { 0x1a86, 0x7523 }, /* ch340 chip */ \
+    { 0x1a86, 0x7522 }, /* ch340k chip */ \
+    { 0x1a86, 0x5523 }, /* ch341 chip */ \
+    { 0x1a86, 0xe523 }, /* ch330 chip */ \
+    { 0x4348, 0x5523 }, /* ch340 custom chip */ \
+    { 0x2184, 0x0057 }, /* overtaken from Linux driver /drivers/usb/serial/ch341.c */ \
+    { 0x9986, 0x7523 }  /* overtaken from Linux driver /drivers/usb/serial/ch341.c */
+#endif
+
 #ifndef CFG_TUH_HID
   #define CFG_TUH_HID    0
 #endif

From d92eb38c211899ed963250272d882fcac8dbaf9c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 16:56:18 +0700
Subject: [PATCH 02/19] change code style

---
 src/class/cdc/cdc_host.c | 528 +++++++++++++++++----------------------
 1 file changed, 236 insertions(+), 292 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4f36f7517..05a061487 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -106,7 +106,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 
 static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST };
 enum {
-  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+  FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_pids)
 };
 
 // Store last request baudrate since divisor to baudrate is not easy
@@ -114,7 +114,6 @@ static uint32_t _ftdi_requested_baud;
 
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
-
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -125,12 +124,11 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 
 static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST };
 enum {
-  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+  CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_pids)
 };
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
-
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -141,16 +139,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
 enum {
-  CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
+  CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids)
 };
 
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
-
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 #endif
 
+//------------- Common -------------//
 
 enum {
   SERIAL_DRIVER_ACM = 0,
@@ -204,29 +202,25 @@ static const cdch_serial_driver_t serial_drivers[] = {
 };
 
 enum {
-  SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0])
+  SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers)
 };
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline cdch_interface_t* get_itf(uint8_t idx)
-{
+static inline cdch_interface_t* get_itf(uint8_t idx) {
   TU_ASSERT(idx < CFG_TUH_CDC, NULL);
   cdch_interface_t* p_cdc = &cdch_data[idx];
 
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
     if ( (p_cdc->daddr == daddr) &&
-         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
-    {
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) {
       return i;
     }
   }
@@ -234,14 +228,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
   return TUSB_INDEX_INVALID_8;
 }
 
-
-static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     if (cdch_data[i].daddr == 0) {
       cdch_interface_t* p_cdc = &cdch_data[i];
-
       p_cdc->daddr              = daddr;
       p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
@@ -262,20 +252,16 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
     const cdch_interface_t* p_cdc = &cdch_data[i];
-
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
   return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
-{
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && info);
 
@@ -297,30 +283,26 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
   return true;
 }
 
-bool tuh_cdc_mounted(uint8_t idx)
-{
+bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   return p_cdc != NULL;
 }
 
-bool tuh_cdc_get_dtr(uint8_t idx)
-{
+bool tuh_cdc_get_dtr(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
 
-bool tuh_cdc_get_rts(uint8_t idx)
-{
+bool tuh_cdc_get_rts(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
-bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
-{
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -333,32 +315,28 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
 // Write
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_write_flush(uint8_t idx)
-{
+uint32_t tuh_cdc_write_flush(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
 }
 
-bool tuh_cdc_write_clear(uint8_t idx)
-{
+bool tuh_cdc_write_clear(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_clear(&p_cdc->stream.tx);
 }
 
-uint32_t tuh_cdc_write_available(uint8_t idx)
-{
+uint32_t tuh_cdc_write_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -369,32 +347,28 @@ uint32_t tuh_cdc_write_available(uint8_t idx)
 // Read
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_read_available(uint8_t idx)
-{
+uint32_t tuh_cdc_read_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
-bool tuh_cdc_peek(uint8_t idx, uint8_t* ch)
-{
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
 }
 
-bool tuh_cdc_read_clear (uint8_t idx)
-{
+bool tuh_cdc_read_clear (uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -408,15 +382,13 @@ bool tuh_cdc_read_clear (uint8_t idx)
 //--------------------------------------------------------------------+
 
 // internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer)
-{
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
 
-  if (xfer->result == XFER_RESULT_SUCCESS)
-  {
+  if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
@@ -502,7 +474,6 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_state = (uint8_t) line_state;
     return true;
   }
@@ -526,7 +497,6 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding.bit_rate = baudrate;
     return true;
   }
@@ -552,7 +522,6 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding = *line_coding;
     return true;
   }
@@ -562,31 +531,26 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 // CLASS-USBH API
 //--------------------------------------------------------------------+
 
-void cdch_init(void)
-{
+void cdch_init(void) {
   tu_memclr(cdch_data, sizeof(cdch_data));
 
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
-  {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
 
     tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
-                          p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
-                          p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
 
     tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
-                          p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
-                          p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
 }
 
-void cdch_close(uint8_t daddr)
-{
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
+void cdch_close(uint8_t daddr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
     cdch_interface_t* p_cdc = &cdch_data[idx];
-    if (p_cdc->daddr == daddr)
-    {
+    if (p_cdc->daddr == daddr) {
       TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
 
       // Invoke application callback
@@ -618,16 +582,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
       // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
-  }
-  else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
+  } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
     #if CFG_TUH_CDC_FTDI
     if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
       // FTDI reserve 2 bytes for status
-      // FTDI status
-//      uint8_t status[2] = {
-//        p_cdc->stream.rx.ep_buf[0],
-//        p_cdc->stream.rx.ep_buf[1]
-//      };
+      // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]};
       tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
     }else
     #endif
@@ -653,20 +612,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
-{
-  for(size_t i=0; i<2; i++)
-  {
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) {
+  for (size_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
-              TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
-
+              TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
 
-    if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
       tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
-    }else
-    {
+    } else {
       tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
     }
 
@@ -676,20 +630,17 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co
   return true;
 }
 
-bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   (void) rhport;
 
-  // Only support ACM subclass
+  // For CDC: only support ACM subclass
   // Note: Protocol 0xFF can be RNDIS device
-  if ( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass)
-  {
+  if (TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+      CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
-  {
+  else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
@@ -721,7 +672,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     }
     #endif
   }
-  #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  #endif
 
   return false;
 }
@@ -767,94 +718,85 @@ enum {
   CONFIG_ACM_COMPLETE,
 };
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
+  uint8_t const* p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
+  while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) {
+    if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) {
       // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities;
     }
 
     p_desc = tu_desc_next(p_desc);
   }
 
   // Open notification endpoint of control interface if any
-  if (itf_desc->bNumEndpoints == 1)
-  {
+  if (itf_desc->bNumEndpoints == 1) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
     // next to endpoint descriptor
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
-    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc));
   }
 
   return true;
 }
 
-static void acm_process_config(tuh_xfer_t* xfer)
-{
+static void acm_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc, );
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
 
-  switch(state)
-  {
+  switch (state) {
     case CONFIG_ACM_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
-        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config,
-                                             CONFIG_ACM_SET_LINE_CODING), );
+      if (p_cdc->acm_capability.support_line_request) {
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),);
         break;
       }
-          #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_SET_LINE_CODING:
-        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),);
         break;
       }
-        #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
-      set_config_complete(p_cdc, idx, itf_num+1);
+      set_config_complete(p_cdc, idx, itf_num + 1);
       break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
@@ -987,13 +929,12 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1
   return tuh_control_xfer(&xfer);
 }
 
-static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool
+ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -1001,8 +942,7 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
   return true;
 }
 
-static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
-{
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) {
   const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
   uint32_t divisor;
 
@@ -1022,13 +962,11 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
   return divisor;
 }
 
-static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
-{
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
   return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
 }
 
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
@@ -1055,8 +993,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
+      TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1172,8 +1109,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
@@ -1213,8 +1149,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_SET_DTR_RTS:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1248,8 +1183,7 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
-{
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) {
   // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
   TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
   TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
@@ -1303,23 +1237,19 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
   return false;
 }
 
-static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
 }
 
-static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
 }
 
-static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
 }
 
-static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
 }
 
@@ -1335,8 +1265,7 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u
  */
 // calculate baudrate devisors
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
-{
+static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   uint32_t fact, div, clk_div;
   bool force_fact0 = false;
   int32_t ps;
@@ -1362,20 +1291,19 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
    */
   fact = 1;
   for (ps = 3; ps >= 0; ps--) {
-    if (speed > ch341_min_rates[ps])
-      break;
+    if (speed > ch341_min_rates[ps]) break;
   }
 
-  if (ps < 0)
-    return -EINVAL;
+  if (ps < 0) return -EINVAL;
 
   /* Determine corresponding divisor, rounding down. */
   clk_div = CH341_CLK_DIV(ps, fact);
   div = CH341_CLKRATE / (clk_div * speed);
 
   /* Some devices require a lower base clock if ps < 3. */
-  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
+  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) {
     force_fact0 = true;
+  }
 
   /* Halve base clock (fact = 0) if required. */
   if (div < 9 || div > 255 || force_fact0) {
@@ -1384,16 +1312,16 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
     fact = 0;
   }
 
-  if (div < 2)
-    return -EINVAL;
+  if (div < 2) return -EINVAL;
 
   /*
    * Pick next divisor if resulting rate is closer to the requested one,
    * scale up to avoid rounding errors on low rates.
    */
   if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
-      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
+      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) {
     div++;
+  }
 
   /*
    * Prefer lower base clock (fact = 0) if even divisor.
@@ -1411,16 +1339,13 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
 // set baudrate (low level)
 // do not confuse with ch34x_set_baudrate
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   int val;
 
-  if (!baud_rate)
-    return -EINVAL;
+  if (!baud_rate) return -EINVAL;
 
   val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0)
-    return -EINVAL;
+  if (val < 0) return -EINVAL;
 
   /*
    * CH341A buffers data until a full endpoint-size packet (32 bytes)
@@ -1429,100 +1354,94 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate,
    * At least one device with version 0x27 appears to have this bit
    * inverted.
    */
-  if ( p_cdc->ch34x.version > 0x27 )
+  if ( p_cdc->ch34x.version > 0x27 ) {
     val |= BIT(7);
+  }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
 }
 
 // set lcr register
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * Chip versions before version 0x30 as read using
    * CH341_REQ_READ_VERSION used separate registers for line control
    * (stop bits, parity and word length). Version 0x30 and above use
    * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
    */
-  if ( p_cdc->ch34x.version < 0x30 )
-    return 0;
+  if ( p_cdc->ch34x.version < 0x30 ) return 0;
 
   return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
 }
 
 // set handshake (modem controls)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
 }
 
 // detect quirks (special versions of CH34x)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * A subset of CH34x devices does not support all features. The
    * prescaler is limited and there is no support for sending a RS232
    * break condition. A read failure when trying to set up the latter is
    * used to detect these devices.
    */
-  switch ( step )
-  {
-  case 1:
-    p_cdc->ch34x.quirks = 0;
-    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
-    break;
-  case 2:
-    if ( xfer->result != XFER_RESULT_SUCCESS )
-      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
-    return true;
-    break;
-  default:
-    TU_ASSERT ( false ); // suspicious step
-    break;
+  switch (step) {
+    case 1:
+      p_cdc->ch34x.quirks = 0;
+      return ch341_read_reg_request(p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data);
+      break;
+
+    case 2:
+      if (xfer->result != XFER_RESULT_SUCCESS) {
+        p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
+      }
+      return true;
+      break;
+
+    default:
+      TU_ASSERT (false); // suspicious step
+      break;
   }
 }
 
 // internal control complete to update state such as line state, encoding
 // CH34x needs a special interface recovery due to abnormal wIndex usage
-static void ch34x_control_complete(tuh_xfer_t* xfer)
-{
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
-  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
-  cdch_interface_t  *p_cdc  = get_itf ( idx );
-  TU_ASSERT ( p_cdc, );
-  TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
+static void ch34x_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) ((xfer->user_data & 0xff00) >> 8);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT (p_cdc,);
+  TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,); // ch34x_control_complete is only used for CH34x
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (xfer->setup->bRequest) {
-    case CH341_REQ_WRITE_REG: { // register write request
-      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
-      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
-        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+      case CH341_REQ_WRITE_REG: // register write request
+        switch (tu_le16toh (xfer->setup->wValue)) {
+          case (CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER): // baudrate write
+            p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+            break;
+
+          default:
+            TU_ASSERT(false,); // unexpected register write
+            break;
+        }
         break;
-      }
-      default: {
-        TU_ASSERT(false, ); // unexpected register write
+
+      default:
+        TU_ASSERT(false,); // unexpected request
         break;
-      }
-      }
-      break;
-    }
-    default: {
-      TU_ASSERT(false, ); // unexpected request
-      break;
-    }
     }
     xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb)
-      xfer->complete_cb(xfer);
+    if (xfer->complete_cb) xfer->complete_cb(xfer);
   }
 }
 
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
-{
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) /* do not confuse with ch341_set_baudrate */ {
   TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->ch34x.baud_rate = baudrate;
@@ -1530,15 +1449,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh
   return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
 }
 
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
   // todo later
   return false;
 }
 
-static void ch34x_process_config ( tuh_xfer_t* xfer )
-{
+static void ch34x_process_config ( tuh_xfer_t* xfer ) {
   uintptr_t const   state   = xfer->user_data & 0xff;
   // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
   uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
@@ -1561,81 +1478,108 @@ static void ch34x_process_config ( tuh_xfer_t* xfer )
      */
     p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
   }
+
   // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
-  switch ( state ) {
-  case CONFIG_CH34X_STEP1: // request version read
-    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
-    break;
-  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
-    p_cdc->ch34x.version = xfer->buffer[0];
-    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
-    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
-    break;
-  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
-    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
-    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP6: // detect quirks step 1
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
+  switch (state) {
+    case CONFIG_CH34X_STEP1: // request version read
+      TU_ASSERT (ch341_control_in(p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */0,
+                                  buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2),);
+      break;
+
+    case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
+      p_cdc->ch34x.version = xfer->buffer[0];
+      TU_LOG_DRV ("Chip version=%02x\r\n", p_cdc->ch34x.version);
+      TU_ASSERT (ch341_control_out(p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */0,
+                                   ch34x_process_config, CONFIG_CH34X_STEP3),);
+      break;
+
+    case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
+      TU_ASSERT (ch341_set_baudrate(p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config,
+                                    CONFIG_CH34X_STEP4) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
+      TU_ASSERT (ch341_set_handshake(p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP6: // detect quirks step 1
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE,
+                                     ch34x_process_config, CONFIG_CH34X_STEP7) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0) > 0,);
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
+      TU_ASSERT (ch34x_set_baudrate(p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8),);
 #else
-    TU_ATTR_FALLTHROUGH;
+      TU_ATTR_FALLTHROUGH;
 #endif
-    break;
-  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
+      break;
+
+    case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
-    switch ( line_coding.data_bits ) {
-    case 5:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
-      break;
-    case 6:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
-      break;
-    case 7:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
-      break;
-    case 8:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
-      break;
-    default:
-      TU_ASSERT ( false, ); // not supported data_bits
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
-      break;
-    }
-    if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
-      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
-    }
-    TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
-    if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
-      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
+      p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+      switch (line_coding.data_bits) {
+        case 5:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+          break;
+
+        case 6:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+          break;
+
+        case 7:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+          break;
+
+        case 8:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+
+        default:
+          TU_ASSERT (false,); // not supported data_bits
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+      }
+
+      if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
+        p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+        }
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+        }
+      }
+      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
+                                                                         CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
+      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+        p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
+      }
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE) > 0,);
 #else
-    TU_ATTR_FALLTHROUGH;
+      TU_ATTR_FALLTHROUGH;
 #endif
-    break;
+      break;
+
     case CONFIG_CH34X_COMPLETE:
-      set_config_complete ( p_cdc, idx, itf_num );
+      set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
-      TU_ASSERT ( false, );
+      TU_ASSERT (false,);
       break;
   }
 }
 
 #endif // CFG_TUH_CDC_CH34X
 
-#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
+#endif

From d192868d62b56ef2eab9300bf0698a77e4e01cd3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 18:25:15 +0700
Subject: [PATCH 03/19] fix sign-conversion warning

---
 src/class/cdc/cdc_host.c | 34 +++++++++++++++++++++-------------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 05a061487..0cc35da52 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1207,7 +1207,7 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
           .type      = TUSB_REQ_TYPE_VENDOR,
-          .direction = direction
+          .direction = direction & 0x01u
       },
       .bRequest = request,
       .wValue   = tu_htole16 ( value ),
@@ -1265,6 +1265,11 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u
  */
 // calculate baudrate devisors
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+
+static inline uint32_t clamp_val(uint32_t val, uint32_t minval, uint32_t maxval) {
+  return tu_min32(tu_max32(val, minval), maxval);
+}
+
 static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   uint32_t fact, div, clk_div;
   bool force_fact0 = false;
@@ -1280,9 +1285,6 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
    * Clamp to supported range, this makes the (ps < 0) and (div < 2)
    * sanity checks below redundant.
    */
-  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
-  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
-  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
   speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
 
   /*
@@ -1297,7 +1299,7 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   if (ps < 0) return -EINVAL;
 
   /* Determine corresponding divisor, rounding down. */
-  clk_div = CH341_CLK_DIV(ps, fact);
+  clk_div = CH341_CLK_DIV((uint32_t) ps, fact);
   div = CH341_CLKRATE / (clk_div * speed);
 
   /* Some devices require a lower base clock if ps < 3. */
@@ -1333,19 +1335,20 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
     fact = 0;
   }
 
-  return (0x100 - div) << 8 | fact << 2 | ps;
+  return (int32_t) ((0x100 - div) << 8 | fact << 2 | (uint32_t) ps);
 }
 
 // set baudrate (low level)
 // do not confuse with ch34x_set_baudrate
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
-  int val;
-
+static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   if (!baud_rate) return -EINVAL;
 
-  val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0) return -EINVAL;
+  int ret;
+  ret = ch341_get_divisor(p_cdc, baud_rate);
+  if (ret < 0) return -EINVAL;
+
+  uint16_t val = (uint16_t) ret;
 
   /*
    * CH341A buffers data until a full endpoint-size packet (32 bytes)
@@ -1355,7 +1358,7 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate,
    * inverted.
    */
   if ( p_cdc->ch34x.version > 0x27 ) {
-    val |= BIT(7);
+    val = (val | BIT(7));
   }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
@@ -1449,8 +1452,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh
   return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
 }
 
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
+  (void) p_cdc;
+  (void) line_state;
+  (void) complete_cb;
+  (void) user_data;
+
   // todo later
   return false;
 }

From 1f2901e8b12258c953e3c338897f188c98b5eaed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 18:42:39 +0700
Subject: [PATCH 04/19] fix conflict of BIT() macro

---
 src/class/cdc/cdc_host.c     |  2 +-
 src/class/cdc/serial/ch34x.h | 11 ++++-------
 src/common/tusb_common.h     |  1 +
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 0cc35da52..ca5bfff04 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1358,7 +1358,7 @@ static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate,
    * inverted.
    */
   if ( p_cdc->ch34x.version > 0x27 ) {
-    val = (val | BIT(7));
+    val = (val | TU_BIT(7));
   }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 94e18b252..4a5e61bbd 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -29,7 +29,7 @@
 
 #include <stdint.h>
 
-#define BIT(nr) ( (uint32_t)1 << (nr) )
+//#define BIT(nr) ( (uint32_t)1 << (nr) )
 
 #define CH34X_BUFFER_SIZE 2
 
@@ -93,20 +93,17 @@
 #define CH341_LCR_CS6          0x01
 #define CH341_LCR_CS5          0x00
 
-#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
-#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
+#define CH341_QUIRK_LIMITED_PRESCALER TU_BIT(0)
+#define CH341_QUIRK_SIMULATE_BREAK  TU_BIT(1)
 
 #define CH341_CLKRATE   48000000
 #define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
 #define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
 
 /* Supported range is 46 to 3000000 bps. */
-#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
+#define CH341_MIN_BPS TU_DIV_CEIL(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
 #define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
 
-#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
-#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
 // error codes
 #define EINVAL    22  /* Invalid argument */
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index caeb5f2ef..1f08ce4ed 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -37,6 +37,7 @@
 #define TU_ARRAY_SIZE(_arr)   ( sizeof(_arr) / sizeof(_arr[0]) )
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
+#define TU_DIV_CEIL(n, d)     (((n) + (d) - 1) / (d))
 
 #define TU_U16(_high, _low)   ((uint16_t) (((_high) << 8) | (_low)))
 #define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))

From e2aa671346103d3ed80c2849350488d5ddf2e0dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 12:54:39 +0700
Subject: [PATCH 05/19] move open() ad vid_pid_list into serial driver struct

---
 src/class/cdc/cdc_host.c | 102 ++++++++++++++++++---------------------
 1 file changed, 47 insertions(+), 55 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index c018cf057..91e35ec8c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -104,10 +104,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 #if CFG_TUH_CDC_FTDI
 #include "serial/ftdi_sio.h"
 
-static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST };
-enum {
-  FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_vid_pid_list)
-};
+static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
 // Store last request baudrate since divisor to baudrate is not easy
 static uint32_t _ftdi_requested_baud;
@@ -122,10 +119,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 #if CFG_TUH_CDC_CP210X
 #include "serial/cp210x.h"
 
-static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST };
-enum {
-  CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_vid_pid_list)
-};
+static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST};
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
@@ -137,10 +131,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 #if CFG_TUH_CDC_CH34X
 #include "serial/ch34x.h"
 
-static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
-enum {
-  CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids)
-};
+static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
 
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
@@ -164,9 +155,14 @@ enum {
 #if CFG_TUH_CDC_CH34X
   SERIAL_DRIVER_CH34X,
 #endif
+
+  SERIAL_DRIVER_COUNT
 };
 
 typedef struct {
+  uint16_t const (*vid_pid_list)[2];
+  uint16_t const vid_pid_count;
+  bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
@@ -174,36 +170,50 @@ typedef struct {
 
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
-  { .process_set_config     = acm_process_config,
-    .set_control_line_state = acm_set_control_line_state,
-    .set_baudrate           = acm_set_baudrate
+  {
+      .vid_pid_list           = NULL,
+      .vid_pid_count          = 0,
+      .open                   = acm_open,
+      .process_set_config     = acm_process_config,
+      .set_control_line_state = acm_set_control_line_state,
+      .set_baudrate           = acm_set_baudrate
   },
 
   #if CFG_TUH_CDC_FTDI
-  { .process_set_config     = ftdi_process_config,
-    .set_control_line_state = ftdi_sio_set_modem_ctrl,
-    .set_baudrate           = ftdi_sio_set_baudrate
+  {
+      .vid_pid_list           = ftdi_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
+      .open                   = ftdi_open,
+      .process_set_config     = ftdi_process_config,
+      .set_control_line_state = ftdi_sio_set_modem_ctrl,
+      .set_baudrate           = ftdi_sio_set_baudrate
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
-  { .process_set_config     = cp210x_process_config,
-    .set_control_line_state = cp210x_set_modem_ctrl,
-    .set_baudrate           = cp210x_set_baudrate
+  {
+      .vid_pid_list           = cp210x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
+      .open                   = cp210x_open,
+      .process_set_config     = cp210x_process_config,
+      .set_control_line_state = cp210x_set_modem_ctrl,
+      .set_baudrate           = cp210x_set_baudrate
   },
   #endif
 
   #if CFG_TUH_CDC_CH34X
-  { .process_set_config     = ch34x_process_config,
-    .set_control_line_state = ch34x_set_modem_ctrl,
-    .set_baudrate           = ch34x_set_baudrate
+  {
+      .vid_pid_list           = ch34x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
+      .open                   = ch34x_open,
+      .process_set_config     = ch34x_process_config,
+      .set_control_line_state = ch34x_set_modem_ctrl,
+      .set_baudrate           = ch34x_set_baudrate
   },
-#endif
+  #endif
 };
 
-enum {
-  SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers)
-};
+TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch");
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -639,36 +649,20 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
+  else if (SERIAL_DRIVER_COUNT > 1 &&
+           TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
-    #if CFG_TUH_CDC_FTDI
-    for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
-      if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) {
-        return ftdi_open(daddr, itf_desc, max_len);
+    for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) {
+      cdch_serial_driver_t const* driver = &serial_drivers[dr];
+      for (size_t i = 0; i < driver->vid_pid_count; i++) {
+        if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) {
+          return driver->open(daddr, itf_desc, max_len);
+        }
       }
     }
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
-      if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) {
-        return cp210x_open(daddr, itf_desc, max_len);
-      }
-    }
-    #endif
-
-    #if CFG_TUH_CDC_CH34X
-    for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) {
-      if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) {
-        return ch34x_open(daddr, itf_desc, max_len);
-      }
-    }
-    #endif
   }
-  #endif
 
   return false;
 }
@@ -683,9 +677,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
   usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
 }
 
-
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
-{
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 

From 4e6408ea4940085f66c676772d77e3951e82ea11 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 16 Jan 2024 08:07:22 +0100
Subject: [PATCH 06/19] CDCh host: further work on CH340/CH341 support

---
 examples/host/cdc_msc_hid/src/tusb_config.h   |   3 +-
 .../cdc_msc_hid_freertos/src/tusb_config.h    |   3 +-
 src/class/cdc/cdc_debug.h                     |  65 ++
 src/class/cdc/cdc_device.c                    |  21 +-
 src/class/cdc/cdc_host.c                      | 570 ++++++++----------
 src/class/cdc/cdc_host.h                      |   4 +-
 src/class/cdc/serial/ch34x.h                  | 103 +---
 7 files changed, 370 insertions(+), 399 deletions(-)
 create mode 100644 src/class/cdc/cdc_debug.h

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 76d59c316..ac14ef97e 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -120,8 +120,7 @@
 //------------- CDC -------------//
 
 // Set Line Control state on enumeration/mounted:
-// DTR ( bit 0), RTS (bit 1)
-#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR )
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index bb7c3388d..1b68dd2d8 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -125,8 +125,7 @@
 //------------- CDC -------------//
 
 // Set Line Control state on enumeration/mounted:
-// DTR ( bit 0), RTS (bit 1)
-#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR )
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
diff --git a/src/class/cdc/cdc_debug.h b/src/class/cdc/cdc_debug.h
new file mode 100644
index 000000000..879e49a50
--- /dev/null
+++ b/src/class/cdc/cdc_debug.h
@@ -0,0 +1,65 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 IngHK Heiko Kuester
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CDC_DEBUG_H_
+#define _TUSB_CDC_DEBUG_H_
+
+#include "cdc.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// logging of line coding
+#define TU_LOG_LINE_CODING(PRE_TEXT,LINE_CODING)                            \
+  TU_LOG_DRV(PRE_TEXT "Line Coding %lu Bd, %u%c%s\r\n",                     \
+    LINE_CODING.bit_rate,                                                   \
+    LINE_CODING.data_bits,                                                  \
+    LINE_CODING.parity == CDC_LINE_CODING_PARITY_NONE ? 'N' :               \
+      LINE_CODING.parity == CDC_LINE_CODING_PARITY_ODD ? 'O' :              \
+        LINE_CODING.parity == CDC_LINE_CODING_PARITY_EVEN ? 'E' :           \
+          LINE_CODING.parity == CDC_LINE_CODING_PARITY_MARK ? 'M' :         \
+            LINE_CODING.parity == CDC_LINE_CODING_PARITY_SPACE ? 'S' : '?', \
+    LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ? "1" :            \
+      LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1_5 ? "1.5" :      \
+        LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ? "2" : "?")
+
+// logging of baudrate
+#define TU_LOG_BAUDRATE(PRE_TEXT,BAUDRATE) \
+  TU_LOG_DRV(PRE_TEXT "Baudrate %lu Bd\r\n", BAUDRATE)
+
+ // logging of control line state
+#define TU_LOG_CONTROL_LINE_STATE(PRE_TEXT,LINE_STATE)            \
+  TU_LOG_DRV(PRE_TEXT "Control Line State RTS%c DTR%c\r\n", \
+    LINE_STATE & CDC_CONTROL_LINE_STATE_RTS ? '+' : '-',           \
+    LINE_STATE & CDC_CONTROL_LINE_STATE_DTR ? '+' : '-' )
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_DEBUG_H_ */
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index c26264e60..b763419e7 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -32,6 +32,9 @@
 #include "device/usbd_pvt.h"
 
 #include "cdc_device.h"
+#if 0 // TODO activate and test
+#include "cdc_debug.h"
+#endif
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUD_CDC_LOG_LEVEL
@@ -360,7 +363,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_SET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG_DRV("  Set Line Coding\r\n");
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_LINE_CODING("  Set ", p_cdc->line_coding);
+        #else
+          TU_LOG_DRV("  Set Line Coding\r\n");
+        #endif
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
       else if ( stage == CONTROL_STAGE_ACK)
@@ -372,7 +379,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_GET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG_DRV("  Get Line Coding\r\n");
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_LINE_CODING("  Get ", p_cdc->line_coding);
+        #else
+          TU_LOG_DRV("  Get Line Coding\r\n");
+        #endif
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
     break;
@@ -397,7 +408,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
-        TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_CONTROL_LINE_STATE("  Set ", p_cdc->line_state);
+        #else
+          TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        #endif
 
         // Invoke callback
         if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f6a6773e0..d46bfecb4 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -2,7 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2023 Heiko Kuester (CH34x support)
+ * Copyright (c) 2023 IngHK Heiko Kuester
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -33,6 +33,7 @@
 #include "host/usbh_pvt.h"
 
 #include "cdc_host.h"
+#include "cdc_debug.h"
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUH_CDC_LOG_LEVEL
@@ -55,7 +56,7 @@ typedef struct {
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
-  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
+  uint8_t line_state;                               // RTS, DTR (refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
 
   tuh_xfer_cb_t user_control_cb;
@@ -70,16 +71,9 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-  #if CFG_TUH_CDC_CH34X
-  struct {
-    uint32_t  baud_rate;
-    uint8_t   mcr;
-    uint8_t   msr;
-    uint8_t   lcr;
-    uint32_t  quirks;
-    uint8_t   version;
-  } ch34x;
-  #endif
+#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X
+  uint32_t  baudrate_requested;
+#endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -106,12 +100,10 @@ enum {
   FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
 };
 
-// Store last request baudrate since divisor to baudrate is not easy
-static uint32_t _ftdi_requested_baud;
-
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
 
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -128,6 +120,7 @@ enum {
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
 
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -144,6 +137,7 @@ enum {
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
 
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 #endif
@@ -169,35 +163,40 @@ typedef struct {
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 } cdch_serial_driver_t;
 
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
   { .process_set_config     = acm_process_config,
     .set_control_line_state = acm_set_control_line_state,
-    .set_baudrate           = acm_set_baudrate
+    .set_baudrate           = acm_set_baudrate,
+    .set_line_coding        = acm_set_line_coding
   },
 
   #if CFG_TUH_CDC_FTDI
   { .process_set_config     = ftdi_process_config,
     .set_control_line_state = ftdi_sio_set_modem_ctrl,
-    .set_baudrate           = ftdi_sio_set_baudrate
+    .set_baudrate           = ftdi_sio_set_baudrate,
+    .set_line_coding        = ftdi_set_line_coding
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
   { .process_set_config     = cp210x_process_config,
     .set_control_line_state = cp210x_set_modem_ctrl,
-    .set_baudrate           = cp210x_set_baudrate
+    .set_baudrate           = cp210x_set_baudrate,
+    .set_line_coding        = cp210x_set_line_coding
   },
   #endif
 
   #if CFG_TUH_CDC_CH34X
   { .process_set_config     = ch34x_process_config,
     .set_control_line_state = ch34x_set_modem_ctrl,
-    .set_baudrate           = ch34x_set_baudrate
+    .set_baudrate           = ch34x_set_baudrate,
+    .set_line_coding        = ch34x_set_line_coding
   },
-#endif
+  #endif
 };
 
 enum {
@@ -304,6 +303,7 @@ bool tuh_cdc_get_dtr(uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
+  TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
@@ -312,6 +312,7 @@ bool tuh_cdc_get_rts(uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
+  TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
@@ -322,6 +323,7 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
   TU_VERIFY(p_cdc);
 
   *line_coding = p_cdc->line_coding;
+  TU_LOG_LINE_CODING("CDCh Get ", p_cdc->line_coding);
 
   return true;
 }
@@ -440,7 +442,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 
           case FTDI_SIO_SET_BAUD_RATE:
             // convert from divisor to baudrate is not supported
-            p_cdc->line_coding.bit_rate = _ftdi_requested_baud;
+            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
 
           default: break;
@@ -465,12 +467,6 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
         break;
       #endif
 
-      #if CFG_TUH_CDC_CH34X
-      case SERIAL_DRIVER_CH34X:
-        TU_ASSERT(false, ); // see special ch34x_control_complete function
-        break;
-      #endif
-
       default: break;
     }
   }
@@ -487,7 +483,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+    TU_VERIFY(driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data));
   }else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
@@ -501,8 +497,10 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_state = (uint8_t) line_state;
-    return true;
   }
+  TU_LOG_CONTROL_LINE_STATE("CDCh Set ", p_cdc->line_state);
+
+  return true;
 }
 
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
@@ -511,7 +509,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+    TU_VERIFY(driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data));
   }else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
@@ -525,23 +523,24 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_coding.bit_rate = baudrate;
-    return true;
   }
+  TU_LOG_BAUDRATE("CDCh Set ", p_cdc->line_coding.bit_rate);
+
+  return true;
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  // only ACM support this set line coding request
-  TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
-  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }else {
+    TU_VERIFY(driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data));
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
-    bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+    bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
       // user_data is not NULL, return result via user_data
@@ -551,8 +550,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_coding = *line_coding;
-    return true;
   }
+  TU_LOG_LINE_CODING("CDCh Set ", p_cdc->line_coding);
+
+  return true;
 }
 
 //--------------------------------------------------------------------+
@@ -684,13 +685,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   {
     return acm_open(daddr, itf_desc, max_len);
   }
-<<<<<<< HEAD
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if ( 0xff == itf_desc->bInterfaceClass )
-=======
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
   else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
->>>>>>> remotes/hathach/master
   {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
@@ -816,6 +812,8 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1
     TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
   }
 
+  TU_LOG_DRV("[%u] CDCh ACM opened\r\n", daddr);
+
   return true;
 }
 
@@ -852,6 +850,12 @@ static void acm_process_config(tuh_xfer_t* xfer)
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+        TU_LOG_LINE_CODING("CDCh ACM Init ", p_cdc->line_coding);
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh ACM Init", p_cdc->line_state);
+      #endif
       // itf_num+1 to account for data interface as well
       set_config_complete(p_cdc, idx, itf_num+1);
       break;
@@ -893,6 +897,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
 
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC ACM Set Line Conding\r\n");
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
 
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -994,6 +999,12 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
@@ -1035,7 +1046,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
-  _ftdi_requested_baud = baudrate;
+  p_cdc->baudrate_requested = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
@@ -1088,6 +1099,14 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
+      #if 0 // TODO set data format
+        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+          TU_LOG_LINE_CODING("CDCh FTDI Init ", p_cdc->line_coding);
+        #endif
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh FTDI Init ", p_cdc->line_state);
+      #endif
       break;
 
     default:
@@ -1166,6 +1185,12 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
   return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
 }
 
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
@@ -1224,6 +1249,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
+      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
+        TU_LOG_LINE_CODING("CDCh CP210x Init ", p_cdc->line_coding);
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh CP210x Init ", p_cdc->line_state);
+      #endif
       break;
 
     default: break;
@@ -1233,20 +1264,19 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 #endif
 
 //--------------------------------------------------------------------+
-// CH34x
+// CH34x (CH340 & CH341)
 //--------------------------------------------------------------------+
 
 #if CFG_TUH_CDC_CH34X
 
+#define CH34X_LOGS false
+
 enum {
-  CONFIG_CH34X_STEP1 = 0,
-  CONFIG_CH34X_STEP2,
-  CONFIG_CH34X_STEP3,
-  CONFIG_CH34X_STEP4,
-  CONFIG_CH34X_STEP5,
-  CONFIG_CH34X_STEP6,
-  CONFIG_CH34X_STEP7,
-  CONFIG_CH34X_STEP8,
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
   CONFIG_CH34X_COMPLETE
 };
 
@@ -1259,17 +1289,22 @@ static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, u
   cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
   TU_VERIFY ( p_cdc );
 
-  TU_LOG_DRV ( "CH34x opened\r\n" );
+
   p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
 
   // endpoint pair
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
 
   // data endpoints expected to be in pairs
-  return open_ep_stream_pair ( p_cdc, desc_ep );
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep), false);
+
+  TU_LOG_DRV("[%u] CDCh CH34x opened\r\n", daddr);
+
+  return true;
 }
 
-static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index,
+                                uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
@@ -1297,212 +1332,66 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .setup       = &request_setup,
       .buffer      = enum_buf,
       .complete_cb = complete_cb,
-      // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+      .user_data   = user_data
   };
 
   return tuh_control_xfer ( &xfer );
-  return false;
 }
 
-static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
 }
 
-static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                               uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
 }
 
-static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
-  return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
+  return ch34x_control_out ( p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
 }
 
-static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
+//                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+//{
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+//}
+
+uint8_t ch34x_xfer_get_itf_num ( tuh_xfer_t* xfer )
+// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr
 {
-  return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
-}
-
-/*
- * The device line speed is given by the following equation:
- *
- *  baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
- *
- *    0 <= ps <= 3,
- *    0 <= fact <= 1,
- *    2 <= div <= 256 if fact = 0, or
- *    9 <= div <= 256 if fact = 1
- */
-// calculate baudrate devisors
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
-{
-  uint32_t fact, div, clk_div;
-  bool force_fact0 = false;
-  int32_t ps;
-  static const uint32_t ch341_min_rates[] = {
-      CH341_MIN_RATE(0),
-      CH341_MIN_RATE(1),
-      CH341_MIN_RATE(2),
-      CH341_MIN_RATE(3),
-  };
-
-  /*
-   * Clamp to supported range, this makes the (ps < 0) and (div < 2)
-   * sanity checks below redundant.
-   */
-  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
-  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
-  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
-  speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
-
-  /*
-   * Start with highest possible base clock (fact = 1) that will give a
-   * divisor strictly less than 512.
-   */
-  fact = 1;
-  for (ps = 3; ps >= 0; ps--) {
-    if (speed > ch341_min_rates[ps])
-      break;
-  }
-
-  if (ps < 0)
-    return -EINVAL;
-
-  /* Determine corresponding divisor, rounding down. */
-  clk_div = CH341_CLK_DIV(ps, fact);
-  div = CH341_CLKRATE / (clk_div * speed);
-
-  /* Some devices require a lower base clock if ps < 3. */
-  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
-    force_fact0 = true;
-
-  /* Halve base clock (fact = 0) if required. */
-  if (div < 9 || div > 255 || force_fact0) {
-    div /= 2;
-    clk_div *= 2;
-    fact = 0;
-  }
-
-  if (div < 2)
-    return -EINVAL;
-
-  /*
-   * Pick next divisor if resulting rate is closer to the requested one,
-   * scale up to avoid rounding errors on low rates.
-   */
-  if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
-      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
-    div++;
-
-  /*
-   * Prefer lower base clock (fact = 0) if even divisor.
-   *
-   * Note that this makes the receiver more tolerant to errors.
-   */
-  if (fact == 1 && div % 2 == 0) {
-    div /= 2;
-    fact = 0;
-  }
-
-  return (0x100 - div) << 8 | fact << 2 | ps;
-}
-
-// set baudrate (low level)
-// do not confuse with ch34x_set_baudrate
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  int val;
-
-  if (!baud_rate)
-    return -EINVAL;
-
-  val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0)
-    return -EINVAL;
-
-  /*
-   * CH341A buffers data until a full endpoint-size packet (32 bytes)
-   * has been received unless bit 7 is set.
-   *
-   * At least one device with version 0x27 appears to have this bit
-   * inverted.
-   */
-  if ( p_cdc->ch34x.version > 0x27 )
-    val |= BIT(7);
-
-  return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
-}
-
-// set lcr register
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  /*
-   * Chip versions before version 0x30 as read using
-   * CH341_REQ_READ_VERSION used separate registers for line control
-   * (stop bits, parity and word length). Version 0x30 and above use
-   * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
-   */
-  if ( p_cdc->ch34x.version < 0x30 )
-    return 0;
-
-  return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
-}
-
-// set handshake (modem controls)
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
-}
-
-// detect quirks (special versions of CH34x)
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  /*
-   * A subset of CH34x devices does not support all features. The
-   * prescaler is limited and there is no support for sending a RS232
-   * break condition. A read failure when trying to set up the latter is
-   * used to detect these devices.
-   */
-  switch ( step )
+  for ( uint8_t i=0; i<CFG_TUH_CDC; i++ )
   {
-  case 1:
-    p_cdc->ch34x.quirks = 0;
-    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
-    break;
-  case 2:
-    if ( xfer->result != XFER_RESULT_SUCCESS )
-      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
-    return true;
-    break;
-  default:
-    TU_ASSERT ( false ); // suspicious step
-    break;
+    const cdch_interface_t* p_cdc = &cdch_data[i];
+    if ( p_cdc->daddr == xfer->daddr ) return p_cdc->bInterfaceNumber;
   }
+
+  return INTERFACE_INVALID_NUMBER;
 }
 
 // internal control complete to update state such as line state, encoding
-// CH34x needs a special interface recovery due to abnormal wIndex usage
-static void ch34x_control_complete(tuh_xfer_t* xfer)
+static void ch34x_control_complete ( tuh_xfer_t* xfer )
 {
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     itf_num = ch34x_xfer_get_itf_num ( xfer );
   uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
   cdch_interface_t  *p_cdc  = get_itf ( idx );
+  uint16_t          value   = tu_le16toh ( xfer->setup->wValue );
   TU_ASSERT ( p_cdc, );
   TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
 
-  if (xfer->result == XFER_RESULT_SUCCESS) {
-    switch (xfer->setup->bRequest) {
-    case CH341_REQ_WRITE_REG: { // register write request
-      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
-      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
-        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+  if ( xfer->result == XFER_RESULT_SUCCESS ) {
+    switch ( xfer->setup->bRequest ) {
+    case CH34X_REQ_WRITE_REG: { // register write request
+      switch ( value ) {
+      case ( 0x1312 ): { // baudrate write
+        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+        #if CH34X_LOGS
+          TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate);
+        #endif
         break;
       }
       default: {
@@ -1512,6 +1401,20 @@ static void ch34x_control_complete(tuh_xfer_t* xfer)
       }
       break;
     }
+    case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request
+      if ( ~value & CH34X_BIT_RTS )
+        p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+      else
+        p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_RTS;
+      if ( ~value & CH34X_BIT_DTR )
+        p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+      else
+        p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_DTR;
+      #if CH34X_LOGS
+        TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state);
+      #endif
+      break;
+    }
     default: {
       TU_ASSERT(false, ); // unexpected request
       break;
@@ -1523,118 +1426,161 @@ static void ch34x_control_complete(tuh_xfer_t* xfer)
   }
 }
 
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
+static bool ch34x_get_factor_divisor ( uint32_t baval, uint8_t *factor, uint8_t *divisor )
+{ // calc baudrate factor and divisor
+  uint8_t  a;
+  uint8_t  b;
+  uint32_t c;
+
+  switch (baval) {
+  case 921600:
+    a = 0xf3;
+    b = 7;
+    break;
+  case 307200:
+    a = 0xd9;
+    b = 7;
+    break;
+  default:
+    if (baval > 6000000 / 255) {
+      b = 3;
+      c = 6000000;
+    } else if (baval > 750000 / 255) {
+      b = 2;
+      c = 750000;
+    } else if (baval > 93750 / 255) {
+      b = 1;
+      c = 93750;
+    } else {
+      b = 0;
+      c = 11719;
+    }
+    a = (unsigned char)(c / baval);
+    if (a == 0 || a == 0xFF)
+      return false;
+    if ((c / a - baval) > (baval - c / (a + 1)))
+      a++;
+    a = 256 - a;
+    break;
+  }
+  *factor = a;
+  *divisor = b;
+
+  return true;
+}
+
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
-  uint32_t baud_le = tu_htole32(baudrate);
-  p_cdc->ch34x.baud_rate = baudrate;
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  p_cdc->baudrate_requested = baudrate;
   p_cdc->user_control_cb = complete_cb;
-  return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
+  uint8_t factor, divisor;
+  TU_ASSERT ( ch34x_get_factor_divisor ( baudrate, &factor, &divisor ), false );
+  TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x1312, /* value */ (uint16_t)factor << 8 | 0x80 | divisor,
+                                complete_cb ? ch34x_control_complete : NULL, user_data ), false );
+
+  return true;
 }
 
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
-  TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
-  // todo later
-  return false;
+  p_cdc->user_control_cb = complete_cb;
+  uint16_t control = 0;
+  if ( line_state & CDC_CONTROL_LINE_STATE_RTS )
+    control |= CH34X_BIT_RTS;
+  if ( line_state & CDC_CONTROL_LINE_STATE_DTR )
+    control |= CH34X_BIT_DTR;
+  TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t)~control,
+                                  /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data ), false );
+  return true;
 }
 
 static void ch34x_process_config ( tuh_xfer_t* xfer )
 {
-  uintptr_t const   state   = xfer->user_data & 0xff;
-  // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
-  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
-  cdch_interface_t  *p_cdc  = get_itf ( idx );
-  uint8_t           buffer [ CH34X_BUFFER_SIZE ];
-  cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+  uint8_t const           itf_num     = ch34x_xfer_get_itf_num ( xfer );
+  uintptr_t const         state       = xfer->user_data;
+  uint8_t const           idx         = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t        *p_cdc      = get_itf ( idx );
+  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
+  uint8_t                 buffer[2];
   TU_ASSERT ( p_cdc, );
 
-  if ( state == 0 ) {
-    // defaults
-    p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE;
-    p_cdc->ch34x.mcr = 0;
-    p_cdc->ch34x.msr = 0;
-    p_cdc->ch34x.quirks = 0;
-    p_cdc->ch34x.version = 0;
-    /*
-     * Some CH340 devices appear unable to change the initial LCR
-     * settings, so set a sane 8N1 default.
-     */
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
-  }
-  // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
   switch ( state ) {
-  case CONFIG_CH34X_STEP1: // request version read
-    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
+  case CONFIG_CH34X_READ_VERSION: // request version read
+    #if CH34X_LOGS
+      TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
+    #endif
+    TU_ASSERT ( ch34x_control_in ( p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0,
+                                   /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT ), );
     break;
-  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
-    p_cdc->ch34x.version = xfer->buffer[0];
-    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
-    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
-    break;
-  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
-    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
-    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP6: // detect quirks step 1
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
-    break;
-  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+  case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
+    uint8_t version = xfer->buffer[0];
+    #if CH34X_LOGS
+      TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version );
+    #endif
+    // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
+    TU_ASSERT ( version >= 0x30, );
+    uint8_t factor, divisor;
+    TU_ASSERT ( ch34x_get_factor_divisor ( line_coding.bit_rate, &factor, &divisor ), );
+    uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
     switch ( line_coding.data_bits ) {
     case 5:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+      lcr |= CH34X_LCR_CS5;
       break;
     case 6:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+      lcr |= CH34X_LCR_CS6;
       break;
     case 7:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+      lcr |= CH34X_LCR_CS7;
       break;
     case 8:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      lcr |= CH34X_LCR_CS8;
       break;
     default:
       TU_ASSERT ( false, ); // not supported data_bits
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      lcr |= CH34X_LCR_CS8;
       break;
     }
     if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
-      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+      lcr |= CH34X_LCR_ENABLE_PAR;
       if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+        lcr |= CH34X_LCR_PAR_EVEN;
       if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+        lcr |= CH34X_LCR_MARK_SPACE;
     }
     TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
     if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
-      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
+      lcr |= CH34X_LCR_STOP_BITS_2;
+    TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */ (uint16_t)lcr << 8 | 0x9c,
+                                    /* index */ (uint16_t)factor << 8 | 0x80 | divisor, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE ), );
+    break;
+  }
+  case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver
+    TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL ), );
+    break;
+  case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control
+    TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL ), );
+    break;
+  case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+    TU_ASSERT ( ch34x_set_modem_ctrl ( p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE ), );
+    break;
+  case CONFIG_CH34X_COMPLETE:
+    p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
+    #if CH34X_LOGS
+      TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
+      TU_LOG_LINE_CODING("  ", p_cdc->line_coding);
+      TU_LOG_CONTROL_LINE_STATE("  ", p_cdc->line_state);
+    #endif
+    set_config_complete ( p_cdc, idx, itf_num );
+    break;
+  default:
+    TU_ASSERT ( false, );
     break;
-    case CONFIG_CH34X_COMPLETE:
-      set_config_complete ( p_cdc, idx, itf_num );
-      break;
-    default:
-      TU_ASSERT ( false, );
-      break;
   }
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9e5edd94e..8e3a2352a 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -37,7 +37,7 @@
 // Class Driver Configuration
 //--------------------------------------------------------------------+
 
-// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1)
+// Set Line Control state on enumeration/mounted, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR
 #ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
 #define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0
 #endif
@@ -142,7 +142,7 @@ bool tuh_cdc_read_clear (uint8_t idx);
 //   - The function will return true if transfer is successful, false otherwise.
 //--------------------------------------------------------------------+
 
-// Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
+// Request to Set Control Line State, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to set baudrate
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 94e18b252..262e012fd 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ * Copyright (c) 2023 IngHK Heiko Kuester (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -27,87 +27,34 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
-#include <stdint.h>
-
-#define BIT(nr) ( (uint32_t)1 << (nr) )
-
-#define CH34X_BUFFER_SIZE 2
-
-// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
-
-#define DEFAULT_BAUD_RATE 9600
-
-/* flags for IO-Bits */
-#define CH341_BIT_RTS (1 << 6)
-#define CH341_BIT_DTR (1 << 5)
-
-/******************************/
-/* interrupt pipe definitions */
-/******************************/
-/* always 4 interrupt bytes */
-/* first irq byte normally 0x08 */
-/* second irq byte base 0x7d + below */
-/* third irq byte base 0x94 + below */
-/* fourth irq byte normally 0xee */
-
-/* second interrupt byte */
-#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
-
-/* status returned in third interrupt answer byte, inverted in data
-   from irq */
-#define CH341_BIT_CTS 0x01
-#define CH341_BIT_DSR 0x02
-#define CH341_BIT_RI  0x04
-#define CH341_BIT_DCD 0x08
-#define CH341_BITS_MODEM_STAT 0x0f /* all bits */
-
-/* Break support - the information used to implement this was gleaned from
- * the Net/FreeBSD uchcom.c driver by Takanori Watanabe.  Domo arigato.
- */
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
 
 // USB requests
-#define CH341_REQ_READ_VERSION 0x5F // dec 95
-#define CH341_REQ_WRITE_REG    0x9A
-#define CH341_REQ_READ_REG     0x95
-#define CH341_REQ_SERIAL_INIT  0xA1
-#define CH341_REQ_MODEM_CTRL   0xA4
+#define CH34X_REQ_READ_VERSION 0x5F // dec  95
+#define CH34X_REQ_WRITE_REG    0x9A // dec 154
+#define CH34X_REQ_READ_REG     0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
-// CH34x registers
-#define CH341_REG_BREAK        0x05
-#define CH341_REG_PRESCALER    0x12
-#define CH341_REG_DIVISOR      0x13
-#define CH341_REG_LCR          0x18
-#define CH341_REG_LCR2         0x25
-
-#define CH341_NBREAK_BITS      0x01
+// modem control bits
+#define CH34X_BIT_RTS ( 1 << 6 )
+#define CH34X_BIT_DTR ( 1 << 5 )
 
 // line control bits
-#define CH341_LCR_ENABLE_RX    0x80
-#define CH341_LCR_ENABLE_TX    0x40
-#define CH341_LCR_MARK_SPACE   0x20
-#define CH341_LCR_PAR_EVEN     0x10
-#define CH341_LCR_ENABLE_PAR   0x08
-#define CH341_LCR_STOP_BITS_2  0x04
-#define CH341_LCR_CS8          0x03
-#define CH341_LCR_CS7          0x02
-#define CH341_LCR_CS6          0x01
-#define CH341_LCR_CS5          0x00
-
-#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
-#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
-
-#define CH341_CLKRATE   48000000
-#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
-#define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
-
-/* Supported range is 46 to 3000000 bps. */
-#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
-#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
-
-#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
-#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
-// error codes
-#define EINVAL    22  /* Invalid argument */
+#define CH34X_LCR_ENABLE_RX    0x80
+#define CH34X_LCR_ENABLE_TX    0x40
+#define CH34X_LCR_MARK_SPACE   0x20
+#define CH34X_LCR_PAR_EVEN     0x10
+#define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_STOP_BITS_2  0x04
+#define CH34X_LCR_CS8          0x03
+#define CH34X_LCR_CS7          0x02
+#define CH34X_LCR_CS6          0x01
+#define CH34X_LCR_CS5          0x00
 
 #endif /* _CH34X_H_ */

From 07e3d5c69192b1c45d52fc9760ab0ee65d8b0f0c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 13:16:53 +0700
Subject: [PATCH 07/19] fix number of endpoint for ch340x, also open
 notification even not used for now

---
 src/class/cdc/cdc_host.c     | 67 +++++++++++++++++++-----------------
 src/class/cdc/serial/ch34x.h |  6 ++--
 2 files changed, 38 insertions(+), 35 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 91e35ec8c..f7213d558 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -471,9 +471,9 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
@@ -494,9 +494,9 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
@@ -512,16 +512,15 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   }
 }
 
-bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   // only ACM support this set line coding request
   TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
@@ -711,7 +710,6 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint1
 
   cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
-
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
@@ -881,7 +879,6 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
   TU_VERIFY(p_cdc);
 
   TU_LOG_DRV("FTDI opened\r\n");
-
   p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
 
   // endpoint pair
@@ -921,8 +918,7 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool
-ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -1171,26 +1167,34 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) {
-  // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
-  TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
-  TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
 
-  cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
-  TU_VERIFY ( p_cdc );
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
 
-  TU_LOG_DRV ( "CH34x opened\r\n" );
+  TU_LOG_DRV ("CH34x opened\r\n");
   p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
 
-  // endpoint pair
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
 
   // data endpoints expected to be in pairs
-  return open_ep_stream_pair ( p_cdc, desc_ep );
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
 }
 
-static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
@@ -1198,17 +1202,17 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
           .direction = direction & 0x01u
       },
       .bRequest = request,
-      .wValue   = tu_htole16 ( value ),
-      .wIndex   = tu_htole16 ( index ),
-      .wLength  = tu_htole16 ( length )
+      .wValue   = tu_htole16 (value),
+      .wIndex   = tu_htole16 (index),
+      .wLength  = tu_htole16 (length)
   };
 
   // use usbh enum buf since application variable does not live long enough
   uint8_t* enum_buf = NULL;
 
-  if ( buffer && length > 0 ) {
+  if (buffer && length > 0) {
     enum_buf = usbh_get_enum_buf();
-    tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length );
+    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
   }
 
   tuh_xfer_t xfer = {
@@ -1218,11 +1222,10 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .buffer      = enum_buf,
       .complete_cb = complete_cb,
       // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+      .user_data   = (uintptr_t) ((p_cdc->bInterfaceNumber & 0xff) << 8) | (user_data & 0xff)
   };
 
-  return tuh_control_xfer ( &xfer );
-  return false;
+  return tuh_control_xfer(&xfer);
 }
 
 static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 4a5e61bbd..cc3ac99fe 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ * Copyright (c) 2023 Heiko Kuester
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -34,6 +34,7 @@
 #define CH34X_BUFFER_SIZE 2
 
 // The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
+// Note: updated driver can also be found in https://github.com/WCHSoftGroup/ch341ser_linux/tree/main/driver
 
 #define DEFAULT_BAUD_RATE 9600
 
@@ -53,8 +54,7 @@
 /* second interrupt byte */
 #define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
 
-/* status returned in third interrupt answer byte, inverted in data
-   from irq */
+/* status returned in third interrupt answer byte, inverted in data from irq */
 #define CH341_BIT_CTS 0x01
 #define CH341_BIT_DSR 0x02
 #define CH341_BIT_RI  0x04

From 46ac03ba8537a32ae2bf1f7d864879657b696f81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 17:45:16 +0700
Subject: [PATCH 08/19] change code style

---
 src/class/cdc/cdc_host.c | 97 +++++++++++++++++++---------------------
 1 file changed, 46 insertions(+), 51 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 8ef26a7d9..5541b5dee 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1291,25 +1291,22 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (xfer->setup->bRequest) {
-      case CH34X_REQ_WRITE_REG: { // register write request
+      case CH34X_REQ_WRITE_REG:
+        // register write request
         switch (value) {
-          case (0x1312): { // baudrate write
+          case (0x1312):
+            // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
-            #if CH34X_LOGS
-            TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate);
-            #endif
             break;
-          }
 
-          default: {
+          default:
             TU_ASSERT(false,); // unexpected register write
             break;
-          }
         }
         break;
-      }
 
-      case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request
+      case CH34X_REQ_MODEM_CTRL:
+        // set modem controls RTS/DTR request
         if (~value & CH34X_BIT_RTS) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
         } else {
@@ -1322,16 +1319,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
         }
 
-        #if CH34X_LOGS
-        TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state);
-        #endif
         break;
-      }
 
-      default: {
+      default:
         TU_ASSERT(false,); // unexpected request
         break;
-      }
     }
 
     xfer->complete_cb = p_cdc->user_control_cb;
@@ -1393,33 +1385,31 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con
   return false;
 }
 
-static bool
-ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb,
-                   uintptr_t user_data) {
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->baudrate_requested = baudrate;
   p_cdc->user_control_cb = complete_cb;
   uint8_t factor, divisor;
-  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor), false);
+  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor));
   uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
-  TU_ASSERT (
-      ch34x_write_reg(p_cdc, /* reg */ 0x1312, /* value */ value,
-                      complete_cb ? ch34x_control_complete : NULL, user_data), false);
+  TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
+                             complete_cb ? ch34x_control_complete : NULL, user_data));
 
   return true;
 }
 
-static bool
-ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb,
-                     uintptr_t user_data) {
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->user_control_cb = complete_cb;
   uint16_t control = 0;
-  if (line_state & CDC_CONTROL_LINE_STATE_RTS)
+  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
     control |= CH34X_BIT_RTS;
-  if (line_state & CDC_CONTROL_LINE_STATE_DTR)
+  }
+  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
     control |= CH34X_BIT_DTR;
-  TU_ASSERT (
-      ch34x_control_out(p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t) ~control,
-          /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data), false);
+  }
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
@@ -1437,9 +1427,9 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       #if CH34X_LOGS
       TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
       #endif
-      TU_ASSERT (ch34x_control_in(p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0,
-          /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
+
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
       #if CH34X_LOGS
@@ -1468,46 +1458,51 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
           lcr |= CH34X_LCR_CS8;
           break;
       }
+
       if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
         lcr |= CH34X_LCR_ENABLE_PAR;
         if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE)
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
           lcr |= CH34X_LCR_PAR_EVEN;
+        }
         if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE)
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
           lcr |= CH34X_LCR_MARK_SPACE;
+        }
       }
       TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
                                                                          CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
-      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2)
+      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
         lcr |= CH34X_LCR_STOP_BITS_2;
-      TU_ASSERT (ch34x_control_out(p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */
-                                   (uint16_t) (lcr << 8 | 0x9c),
-          /* index */ (uint16_t) (factor << 8 | 0x80 | divisor), ch34x_process_config,
-                                   CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      }
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
-    case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver
-      TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config,
-                                 CONFIG_CH34X_FLOW_CONTROL),);
+
+    case CONFIG_CH34X_SPECIAL_REG_WRITE:
+      // do special reg write, purpose unknown, overtaken from WCH driver
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
-    case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control
-      TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config,
-                                 CONFIG_CH34X_MODEM_CONTROL),);
+
+    case CONFIG_CH34X_FLOW_CONTROL:
+      // no hardware flow control
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
-    case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
-      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config,
-                                      CONFIG_CH34X_COMPLETE),);
+
+    case CONFIG_CH34X_MODEM_CONTROL:
+      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
+
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       #if CH34X_LOGS
       TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
-      TU_LOG_LINE_CODING("  ", p_cdc->line_coding);
-      TU_LOG_CONTROL_LINE_STATE("  ", p_cdc->line_state);
       #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
       TU_ASSERT (false,);
       break;

From 482a8068a51025ee8c31ccdb4355801c185172cc Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 16 Jan 2024 14:51:04 +0100
Subject: [PATCH 09/19] change code style and code cleanup

---
 src/class/cdc/cdc_host.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 5541b5dee..4cecc79a1 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1260,13 +1260,13 @@ static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t
 }
 
 static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data);
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data);
 }
 
 //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
 //                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 //{
-//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
 uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) {
@@ -1327,7 +1327,9 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
     }
 
     xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb)xfer->complete_cb(xfer);
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
   }
 }
 
@@ -1363,8 +1365,12 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
         c = 11719;
       }
       a = (unsigned char) (c / baval);
-      if (a == 0 || a == 0xFF) return false;
-      if ((c / a - baval) > (baval - c / (a + 1))) a++;
+      if (a == 0 || a == 0xFF) {
+        return false;
+      }
+      if ((c / a - baval) > (baval - c / (a + 1))) {
+        a++;
+      }
       a = (uint8_t) (256 - a);
       break;
   }
@@ -1425,7 +1431,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   switch (state) {
     case CONFIG_CH34X_READ_VERSION: // request version read
       #if CH34X_LOGS
-      TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
+        TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
       #endif
       TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
@@ -1433,7 +1439,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
       #if CH34X_LOGS
-      TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version );
+        TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version);
       #endif
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
       TU_ASSERT (version >= 0x30,);
@@ -1470,8 +1476,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
           lcr |= CH34X_LCR_MARK_SPACE;
         }
       }
-      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
-                                                                         CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
+      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
+                 line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported
       if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
         lcr |= CH34X_LCR_STOP_BITS_2;
       }
@@ -1498,7 +1504,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       #if CH34X_LOGS
-      TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
+        TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
       #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;

From f221c0fb6683fc552febbb9a52300d66f031d275 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Jan 2024 14:45:09 +0700
Subject: [PATCH 10/19] more clean up

---
 src/class/cdc/cdc_host.c     | 28 ++++++++++------------------
 src/class/cdc/serial/ch34x.h | 13 +++++++++++++
 2 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4cecc79a1..faee062cf 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -670,6 +670,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
 }
 
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
+  TU_LOG_DRV("CDCh Set Configure complete\r\n");
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
   // Prepare for incoming data
@@ -1176,8 +1177,6 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #if CFG_TUH_CDC_CH34X
 
-#define CH34X_LOGS false
-
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
   CONFIG_CH34X_SERIAL_INIT,
@@ -1247,14 +1246,13 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_
   return tuh_control_xfer(&xfer);
 }
 
-static bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
-                              tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data);
+static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data);
 }
 
-static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
-                 uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb,
-                 uintptr_t user_data) {
+static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                    uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize,
                            complete_cb, user_data);
 }
@@ -1425,27 +1423,24 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
-  uint8_t buffer[2];
+  uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
 
   switch (state) {
     case CONFIG_CH34X_READ_VERSION: // request version read
-      #if CH34X_LOGS
-        TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
-      #endif
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr);
       TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
 
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
-      #if CH34X_LOGS
-        TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version);
-      #endif
+      TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
       TU_ASSERT (version >= 0x30,);
       uint8_t factor, divisor;
       TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),);
       uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+
       switch (line_coding.data_bits) {
         case 5:
           lcr |= CH34X_LCR_CS5;
@@ -1503,9 +1498,6 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
-      #if CH34X_LOGS
-        TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
-      #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;
 
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 557e093a9..54b5b3560 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,6 +27,10 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
+// There is no official documentation for the CH34x chips. Reference can be found
+// - https://github.com/WCHSoftGroup/ch341ser_linux
+// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+
 // set line_coding @ enumeration
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
 #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
@@ -41,6 +45,15 @@
 #define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
 #define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
+#define CH34X_REG_BREAK        0x05
+#define CH34X_REG_PRESCALER    0x12
+#define CH34X_REG_DIVISOR      0x13
+#define CH34X_REG_LCR          0x18
+#define CH34X_REG_LCR2         0x25
+#define CH34X_REG_MCR_MSR      0x06
+#define CH34X_REG_MCR_MSR2     0x07
+#define CH34X_NBREAK_BITS      0x01
+
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )
 #define CH34X_BIT_DTR ( 1 << 5 )

From 3968a0fff87c794266284af7901e334d122e894c Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Wed, 17 Jan 2024 16:04:31 +0100
Subject: [PATCH 11/19] implemented ch34x_set_line_coding() and some code
 cleanup

---
 src/class/cdc/cdc_host.c     | 177 +++++++++++++++++++++--------------
 src/class/cdc/serial/ch34x.h |   7 ++
 2 files changed, 116 insertions(+), 68 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index faee062cf..45a03a31d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SET_LINE_CODING,
   CONFIG_CH34X_SPECIAL_REG_WRITE,
   CONFIG_CH34X_FLOW_CONTROL,
   CONFIG_CH34X_MODEM_CONTROL,
@@ -1292,11 +1292,10 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
       case CH34X_REQ_WRITE_REG:
         // register write request
         switch (value) {
-          case (0x1312):
+          case 0x1312: 
             // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
-
           default:
             TU_ASSERT(false,); // unexpected register write
             break;
@@ -1310,13 +1309,60 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
         }
-
         if (~value & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
         }
+        break;
 
+      case CH34X_REQ_SERIAL_INIT:
+        // serial init request (set line coding incl. baudrate)
+        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+        uint8_t lcr = (uint8_t) (value >> 8);
+        TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled
+        switch (lcr & CH34X_LCR_CS_MASK) {
+          case CH34X_LCR_CS5:
+            p_cdc->line_coding.data_bits = 5;
+            break;
+          case CH34X_LCR_CS6:
+            p_cdc->line_coding.data_bits = 6;
+            break;
+          case CH34X_LCR_CS7:
+            p_cdc->line_coding.data_bits = 7;
+            break;
+          case CH34X_LCR_CS8:
+            p_cdc->line_coding.data_bits = 8;
+            break;
+          default:
+            TU_ASSERT (false,); // unexpected data_bits lcr
+            break;
+        }
+        if (lcr & CH34X_LCR_STOP_BITS_2) {
+          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2;
+        } else {
+          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1;
+        }
+        switch (lcr & CH34X_LCR_PAR_MASK) {
+          case 0:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE;
+            break;
+          case CH34X_LCR_ENABLE_PAR:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE;
+            break;
+          default:
+            TU_ASSERT (false,); // unexpected parity lcr
+            break;
+        }
         break;
 
       default:
@@ -1378,15 +1424,57 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
   return true;
 }
 
+// calc lcr register value (data bits, parity, stop bits)
+static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) {
+  *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  switch (line_coding->data_bits) {
+    case 5:
+      *lcr |= CH34X_LCR_CS5;
+      break;
+    case 6:
+      *lcr |= CH34X_LCR_CS6;
+      break;
+    case 7:
+      *lcr |= CH34X_LCR_CS7;
+      break;
+    case 8:
+      *lcr |= CH34X_LCR_CS8;
+      break;
+    default:
+      TU_ASSERT (false); // data_bits not supported
+      break;
+  }
+  TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities
+             line_coding->parity == CDC_LINE_CODING_PARITY_ODD  || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN ||
+             line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE);
+  if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) {
+    *lcr |= CH34X_LCR_ENABLE_PAR;
+    if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
+      *lcr |= CH34X_LCR_PAR_EVEN;
+    }
+    if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
+      *lcr |= CH34X_LCR_MARK_SPACE;
+    }
+  }
+  TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || 
+             line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits
+  if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    *lcr |= CH34X_LCR_STOP_BITS_2;
+  }
+
+  return true;
+}
+
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  // TODO implement later
-  (void) p_cdc;
-  (void) line_coding;
-  (void) complete_cb;
-  (void) user_data;
-
-  return false;
+  p_cdc->baudrate_requested = line_coding->bit_rate;
+  p_cdc->user_control_cb = complete_cb;
+  uint8_t factor, divisor, lcr;
+  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
+  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
 }
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
@@ -1398,7 +1486,6 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
   uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
   TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
                              complete_cb ? ch34x_control_complete : NULL, user_data));
-
   return true;
 }
 
@@ -1427,82 +1514,36 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   TU_ASSERT (p_cdc,);
 
   switch (state) {
-    case CONFIG_CH34X_READ_VERSION: // request version read
-      TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr);
-      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+    case CONFIG_CH34X_READ_VERSION:
+      // version read request
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),);
       break;
-
-    case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
+    case CONFIG_CH34X_SET_LINE_CODING:
+      // handle version read data, set CH34x line coding (incl. baudrate)
       uint8_t version = xfer->buffer[0];
-      TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version);
-      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
+      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
+      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-      uint8_t factor, divisor;
-      TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),);
-      uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-
-      switch (line_coding.data_bits) {
-        case 5:
-          lcr |= CH34X_LCR_CS5;
-          break;
-        case 6:
-          lcr |= CH34X_LCR_CS6;
-          break;
-        case 7:
-          lcr |= CH34X_LCR_CS7;
-          break;
-        case 8:
-          lcr |= CH34X_LCR_CS8;
-          break;
-        default:
-          TU_ASSERT (false,); // not supported data_bits
-          lcr |= CH34X_LCR_CS8;
-          break;
-      }
-
-      if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
-        lcr |= CH34X_LCR_ENABLE_PAR;
-        if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
-          lcr |= CH34X_LCR_PAR_EVEN;
-        }
-        if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
-          lcr |= CH34X_LCR_MARK_SPACE;
-        }
-      }
-      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
-                 line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported
-      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
-        lcr |= CH34X_LCR_STOP_BITS_2;
-      }
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
-    }
-
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
-
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
-
     case CONFIG_CH34X_MODEM_CONTROL:
       // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
       TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
-
     case CONFIG_CH34X_COMPLETE:
-      p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       set_config_complete(p_cdc, idx, itf_num);
       break;
-
     default:
-      TU_ASSERT (false,);
+      TU_ASSERT (false,); // something gone wrong, should never reached
       break;
   }
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 54b5b3560..b4ed7420c 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,9 +27,13 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
+// For simplicity, only the name CH34X is used here,
+// but specifically only CH340 and CH341 are supported.
+
 // There is no official documentation for the CH34x chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
 // set line_coding @ enumeration
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
@@ -45,6 +49,7 @@
 #define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
 #define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
+// registers
 #define CH34X_REG_BREAK        0x05
 #define CH34X_REG_PRESCALER    0x12
 #define CH34X_REG_DIVISOR      0x13
@@ -64,10 +69,12 @@
 #define CH34X_LCR_MARK_SPACE   0x20
 #define CH34X_LCR_PAR_EVEN     0x10
 #define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
 #define CH34X_LCR_STOP_BITS_2  0x04
 #define CH34X_LCR_CS8          0x03
 #define CH34X_LCR_CS7          0x02
 #define CH34X_LCR_CS6          0x01
 #define CH34X_LCR_CS5          0x00
+#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
 
 #endif /* _CH34X_H_ */

From 30eb35f17f1baa4698da0cd45dbc3dff8906d7c0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 01:06:24 +0700
Subject: [PATCH 12/19] - revert the use of serial init for set line coding -
 update ch34x_get_lcr and ch34x_get_factor_divisor

---
 src/class/cdc/cdc_host.c     | 152 +++++++++++++++++++----------------
 src/class/cdc/serial/ch34x.h |   6 ++
 2 files changed, 90 insertions(+), 68 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 45a03a31d..150ac21f2 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SET_LINE_CODING,
+  CONFIG_CH34X_SERIAL_INIT,
   CONFIG_CH34X_SPECIAL_REG_WRITE,
   CONFIG_CH34X_FLOW_CONTROL,
   CONFIG_CH34X_MODEM_CONTROL,
@@ -1231,7 +1231,9 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_
 
   if (buffer && length > 0) {
     enum_buf = usbh_get_enum_buf();
-    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    if (direction == TUSB_DIR_OUT) {
+      tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    }
   }
 
   tuh_xfer_t xfer = {
@@ -1257,8 +1259,8 @@ static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, ui
                            complete_cb, user_data);
 }
 
-static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data);
+static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data);
 }
 
 //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
@@ -1292,10 +1294,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
       case CH34X_REQ_WRITE_REG:
         // register write request
         switch (value) {
-          case 0x1312: 
+          case CH34X_REG16_DIVISOR_PRESCALER:
             // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
+
           default:
             TU_ASSERT(false,); // unexpected register write
             break;
@@ -1309,6 +1312,7 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
         }
+
         if (~value & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
@@ -1377,8 +1381,8 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
-// calc baudrate factor and divisor
-static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* divisor) {
+// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t a;
   uint8_t b;
   uint32_t c;
@@ -1410,7 +1414,7 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
       }
       a = (unsigned char) (c / baval);
       if (a == 0 || a == 0xFF) {
-        return false;
+        return 0;
       }
       if ((c / a - baval) > (baval - c / (a + 1))) {
         a++;
@@ -1418,74 +1422,75 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
       a = (uint8_t) (256 - a);
       break;
   }
-  *factor = a;
-  *divisor = b;
 
-  return true;
+  // reg divisor = a, reg prescaler = b
+  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
+  // otherwise the chip will buffer data.
+  return (uint16_t) (a << 8 | 0x80 | b);
 }
 
-// calc lcr register value (data bits, parity, stop bits)
-static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) {
-  *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-  switch (line_coding->data_bits) {
-    case 5:
-      *lcr |= CH34X_LCR_CS5;
-      break;
-    case 6:
-      *lcr |= CH34X_LCR_CS6;
-      break;
-    case 7:
-      *lcr |= CH34X_LCR_CS7;
-      break;
-    case 8:
-      *lcr |= CH34X_LCR_CS8;
-      break;
-    default:
-      TU_ASSERT (false); // data_bits not supported
-      break;
+static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  TU_VERIFY(data_bits >= 5, 0);
+  lcr |= (uint8_t) (data_bits - 5);
+
+  if (parity) {
+    lcr |= CH34X_LCR_ENABLE_PAR;
   }
-  TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities
-             line_coding->parity == CDC_LINE_CODING_PARITY_ODD  || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN ||
-             line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE);
-  if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) {
-    *lcr |= CH34X_LCR_ENABLE_PAR;
-    if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
-      *lcr |= CH34X_LCR_PAR_EVEN;
-    }
-    if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
-      *lcr |= CH34X_LCR_MARK_SPACE;
-    }
+  switch(parity) {
+    case CDC_LINE_CODING_PARITY_EVEN:
+      lcr |= CH34X_LCR_PAR_EVEN;
+      break;
+
+    case CDC_LINE_CODING_PARITY_MARK:
+      lcr |= CH34X_LCR_MARK_SPACE;
+      break;
+
+    case CDC_LINE_CODING_PARITY_SPACE:
+      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      break;
+
+    default: break;
   }
-  TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || 
-             line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits
-  if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
-    *lcr |= CH34X_LCR_STOP_BITS_2;
+
+  // 1.5 stop bits not supported
+  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
+  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    lcr |= CH34X_LCR_STOP_BITS_2;
   }
 
+  return lcr;
+}
+
+//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->baudrate_requested = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb ? ch34x_control_complete : NULL, user_data));
+
   return true;
 }
 
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->baudrate_requested = line_coding->bit_rate;
-  p_cdc->user_control_cb = complete_cb;
-  uint8_t factor, divisor, lcr;
-  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
-  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
-  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  return true;
-}
+//  p_cdc->baudrate_requested = line_coding->bit_rate;
+//  p_cdc->user_control_cb = complete_cb;
+//  uint8_t factor, divisor, lcr;
+//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
+//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
+//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+//                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
 
-static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->baudrate_requested = baudrate;
-  p_cdc->user_control_cb = complete_cb;
-  uint8_t factor, divisor;
-  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor));
-  uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
-  TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
-                             complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
@@ -1515,35 +1520,46 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
   switch (state) {
     case CONFIG_CH34X_READ_VERSION:
-      // version read request
       TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
-      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
-    case CONFIG_CH34X_SET_LINE_CODING:
+
+    case CONFIG_CH34X_SERIAL_INIT: {
       // handle version read data, set CH34x line coding (incl. baudrate)
       uint8_t version = xfer->buffer[0];
       TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-      TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
+      TU_ASSERT(div_ps != 0, );
+
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
+    }
+
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
+
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
+
     case CONFIG_CH34X_MODEM_CONTROL:
       // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
       TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
+
     case CONFIG_CH34X_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
-      TU_ASSERT (false,); // something gone wrong, should never reached
+      TU_ASSERT (false,);
       break;
   }
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index b4ed7420c..3f78a3007 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -59,6 +59,12 @@
 #define CH34X_REG_MCR_MSR2     0x07
 #define CH34X_NBREAK_BITS      0x01
 
+#define CH341_REG_0x0F         0x0F // undocumented register
+#define CH341_REG_0x2C         0x2C // undocumented register
+#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+
+#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )
 #define CH34X_BIT_DTR ( 1 << 5 )

From c568a6793e99dde311802d4b4cb0633d2d6f5830 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 12:14:45 +0700
Subject: [PATCH 13/19] - add requested line coding to make update data format
 easier - change ch34x_xfer_get_itf_num() to simply 0

---
 src/class/cdc/cdc_host.c | 321 ++++++++++++++++++---------------------
 1 file changed, 149 insertions(+), 172 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 150ac21f2..3843a8edc 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -60,6 +60,11 @@ typedef struct {
   uint8_t line_state;                               // DTR (bit0), RTS (bit1)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
 
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  cdc_line_coding_t requested_line_coding;
+  // 1 byte padding
+  #endif
+
   tuh_xfer_cb_t user_control_cb;
 
   struct {
@@ -72,10 +77,6 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
-#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X
-  uint32_t  baudrate_requested;
-#endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -429,7 +430,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
 
           case FTDI_SIO_SET_BAUD_RATE:
             // convert from divisor to baudrate is not supported
-            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
             break;
 
           default: break;
@@ -968,7 +969,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
-  p_cdc->baudrate_requested = baudrate;
+  p_cdc->requested_line_coding.bit_rate = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
@@ -1186,6 +1187,9 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
+
 static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
   // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
   TU_VERIFY (itf_desc->bNumEndpoints == 3);
@@ -1269,20 +1273,10 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_
 //  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
-uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) {
-// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr
-  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
-    const cdch_interface_t* p_cdc = &cdch_data[i];
-    if (p_cdc->daddr == xfer->daddr) return p_cdc->bInterfaceNumber;
-  }
-
-  return INTERFACE_INVALID_NUMBER;
-}
-
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer);
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   uint16_t value = tu_le16toh (xfer->setup->wValue);
@@ -1296,7 +1290,14 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         switch (value) {
           case CH34X_REG16_DIVISOR_PRESCALER:
             // baudrate write
-            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+            break;
+
+          case CH32X_REG16_LCR2_LCR:
+            // data format write
+            p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+            p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+            p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
             break;
 
           default:
@@ -1305,68 +1306,26 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         }
         break;
 
-      case CH34X_REQ_MODEM_CTRL:
-        // set modem controls RTS/DTR request
-        if (~value & CH34X_BIT_RTS) {
+      case CH34X_REQ_MODEM_CTRL: {
+        // set modem controls RTS/DTR request. Note: signals are inverted
+        uint16_t const modem_signal = ~value;
+        if (modem_signal & CH34X_BIT_RTS) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
         } else {
-          p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
+          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
         }
 
-        if (~value & CH34X_BIT_DTR) {
+        if (modem_signal & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
-          p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
+          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
         }
         break;
+      }
 
       case CH34X_REQ_SERIAL_INIT:
         // serial init request (set line coding incl. baudrate)
-        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
-        uint8_t lcr = (uint8_t) (value >> 8);
-        TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled
-        switch (lcr & CH34X_LCR_CS_MASK) {
-          case CH34X_LCR_CS5:
-            p_cdc->line_coding.data_bits = 5;
-            break;
-          case CH34X_LCR_CS6:
-            p_cdc->line_coding.data_bits = 6;
-            break;
-          case CH34X_LCR_CS7:
-            p_cdc->line_coding.data_bits = 7;
-            break;
-          case CH34X_LCR_CS8:
-            p_cdc->line_coding.data_bits = 8;
-            break;
-          default:
-            TU_ASSERT (false,); // unexpected data_bits lcr
-            break;
-        }
-        if (lcr & CH34X_LCR_STOP_BITS_2) {
-          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2;
-        } else {
-          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1;
-        }
-        switch (lcr & CH34X_LCR_PAR_MASK) {
-          case 0:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE;
-            break;
-          case CH34X_LCR_ENABLE_PAR:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE;
-            break;
-          default:
-            TU_ASSERT (false,); // unexpected parity lcr
-            break;
-        }
+        p_cdc->line_coding = p_cdc->requested_line_coding;
         break;
 
       default:
@@ -1381,6 +1340,124 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
+//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+//  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+//                                complete_cb ? ch34x_control_complete : NULL, user_data));
+//  return false;
+//}
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb ? ch34x_control_complete : NULL, user_data));
+
+  return true;
+}
+
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+//  p_cdc->baudrate_requested = line_coding->bit_rate;
+//  p_cdc->user_control_cb = complete_cb;
+//  uint8_t factor, divisor, lcr;
+//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
+//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
+//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+//                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+
+  return true;
+}
+
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint8_t control = 0;
+  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
+    control |= CH34X_BIT_RTS;
+  }
+  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
+    control |= CH34X_BIT_DTR;
+  }
+
+  // CH34x signals are inverted
+  control = ~control;
+
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static void ch34x_process_config(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  uintptr_t const state = xfer->user_data;
+  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
+  uint8_t buffer[2]; // TODO remove
+  TU_ASSERT (p_cdc,);
+
+  switch (state) {
+    case CONFIG_CH34X_READ_VERSION:
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+      break;
+
+    case CONFIG_CH34X_SERIAL_INIT: {
+      // handle version read data, set CH34x line coding (incl. baudrate)
+      uint8_t const version = xfer->buffer[0];
+      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
+      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
+      TU_ASSERT (version >= 0x30,);
+
+      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
+      TU_ASSERT(div_ps != 0, );
+
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+
+      // Init CH34x with line coding
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      break;
+    }
+
+    case CONFIG_CH34X_SPECIAL_REG_WRITE:
+      // do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = line_coding;
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_FLOW_CONTROL:
+      // no hardware flow control
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_MODEM_CONTROL:
+      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
+      break;
+
+    case CONFIG_CH34X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      TU_ASSERT (false,);
+      break;
+  }
+}
+
+//------------- CH34x helper  -------------//
+
 // calculate divisor and prescaler for baudrate, return it as 16-bit combined value
 static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t a;
@@ -1429,7 +1506,8 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   return (uint16_t) (a << 8 | 0x80 | b);
 }
 
-static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+// calculate lcr value from data coding
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
   uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
   TU_VERIFY(data_bits >= 5, 0);
   lcr |= (uint8_t) (data_bits - 5);
@@ -1462,107 +1540,6 @@ static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t d
   return lcr;
 }
 
-//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
-//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-
-static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->baudrate_requested = baudrate;
-  p_cdc->user_control_cb = complete_cb;
-  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
-  TU_VERIFY(div_ps != 0);
-  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
-                            complete_cb ? ch34x_control_complete : NULL, user_data));
-
-  return true;
-}
-
-static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-//  p_cdc->baudrate_requested = line_coding->bit_rate;
-//  p_cdc->user_control_cb = complete_cb;
-//  uint8_t factor, divisor, lcr;
-//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
-//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
-//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-//                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  (void) p_cdc;
-  (void) line_coding;
-  (void) complete_cb;
-  (void) user_data;
-
-  return true;
-}
-
-static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
-                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->user_control_cb = complete_cb;
-  uint16_t control = 0;
-  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
-    control |= CH34X_BIT_RTS;
-  }
-  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
-    control |= CH34X_BIT_DTR;
-  }
-  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0,
-                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  return true;
-}
-
-static void ch34x_process_config(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer);
-  uintptr_t const state = xfer->user_data;
-  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
-  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
-  uint8_t buffer[2]; // TODO remove
-  TU_ASSERT (p_cdc,);
-
-  switch (state) {
-    case CONFIG_CH34X_READ_VERSION:
-      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
-      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
-      break;
-
-    case CONFIG_CH34X_SERIAL_INIT: {
-      // handle version read data, set CH34x line coding (incl. baudrate)
-      uint8_t version = xfer->buffer[0];
-      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
-      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
-      TU_ASSERT (version >= 0x30,);
-      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
-      TU_ASSERT(div_ps != 0, );
-
-      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
-                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
-      break;
-    }
-
-    case CONFIG_CH34X_SPECIAL_REG_WRITE:
-      // do special reg write, purpose unknown, overtaken from WCH driver
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
-      break;
-
-    case CONFIG_CH34X_FLOW_CONTROL:
-      // no hardware flow control
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
-      break;
-
-    case CONFIG_CH34X_MODEM_CONTROL:
-      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
-      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
-      break;
-
-    case CONFIG_CH34X_COMPLETE:
-      set_config_complete(p_cdc, idx, itf_num);
-      break;
-
-    default:
-      TU_ASSERT (false,);
-      break;
-  }
-}
 
 #endif // CFG_TUH_CDC_CH34X
 

From 23c2d929a1bae39578b195c7c7b068fb718212bd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 12:40:37 +0700
Subject: [PATCH 14/19] refactor process_internal_control_complete()

---
 src/class/cdc/cdc_host.c | 142 +++++++++++++++++++--------------------
 1 file changed, 69 insertions(+), 73 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 3843a8edc..bfaa64a77 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -396,26 +396,23 @@ bool tuh_cdc_read_clear (uint8_t idx) {
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-// internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
+static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) {
   TU_ASSERT(p_cdc, );
+  uint16_t const value = tu_le16toh(xfer->setup->wValue);
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
           case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-            p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CDC_REQUEST_SET_LINE_CODING: {
             uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
             memcpy(&p_cdc->line_coding, xfer->buffer, len);
-          }
             break;
+          }
 
           default: break;
         }
@@ -425,11 +422,10 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
       case SERIAL_DRIVER_FTDI:
         switch (xfer->setup->bRequest) {
           case FTDI_SIO_MODEM_CTRL:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case FTDI_SIO_SET_BAUD_RATE:
-            // convert from divisor to baudrate is not supported
             p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
             break;
 
@@ -442,22 +438,62 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
       case SERIAL_DRIVER_CP210X:
         switch(xfer->setup->bRequest) {
           case CP210X_SET_MHS:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CP210X_SET_BAUDRATE: {
             uint32_t baudrate;
             memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
             p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
-          }
             break;
+          }
+
+          default: break;
         }
         break;
       #endif
 
       #if CFG_TUH_CDC_CH34X
       case SERIAL_DRIVER_CH34X:
-        TU_ASSERT(false, ); // see special ch34x_control_complete function
+        switch (xfer->setup->bRequest) {
+          case CH34X_REQ_WRITE_REG:
+            // register write request
+            switch (value) {
+              case CH34X_REG16_DIVISOR_PRESCALER:
+                // baudrate
+                p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+                break;
+
+              case CH32X_REG16_LCR2_LCR:
+                // data format
+                p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+                p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+                p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
+                break;
+
+              default: break;
+            }
+            break;
+
+          case CH34X_REQ_MODEM_CTRL: {
+            // set modem controls RTS/DTR request. Note: signals are inverted
+            uint16_t const modem_signal = ~value;
+            if (modem_signal & CH34X_BIT_RTS) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
+            }
+
+            if (modem_signal & CH34X_BIT_DTR) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
+            }
+            break;
+          }
+
+          default: break;
+        }
         break;
       #endif
 
@@ -471,6 +507,15 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
+// internal control complete to update state such as line state, encoding
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+
+  process_internal_control_complete(p_cdc, xfer);
+}
+
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
@@ -1279,70 +1324,16 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
-  uint16_t value = tu_le16toh (xfer->setup->wValue);
-  TU_ASSERT (p_cdc,);
-  TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,);
-
-  if (xfer->result == XFER_RESULT_SUCCESS) {
-    switch (xfer->setup->bRequest) {
-      case CH34X_REQ_WRITE_REG:
-        // register write request
-        switch (value) {
-          case CH34X_REG16_DIVISOR_PRESCALER:
-            // baudrate write
-            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
-            break;
-
-          case CH32X_REG16_LCR2_LCR:
-            // data format write
-            p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
-            p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
-            p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
-            break;
-
-          default:
-            TU_ASSERT(false,); // unexpected register write
-            break;
-        }
-        break;
-
-      case CH34X_REQ_MODEM_CTRL: {
-        // set modem controls RTS/DTR request. Note: signals are inverted
-        uint16_t const modem_signal = ~value;
-        if (modem_signal & CH34X_BIT_RTS) {
-          p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
-        } else {
-          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
-        }
-
-        if (modem_signal & CH34X_BIT_DTR) {
-          p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
-        } else {
-          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
-        }
-        break;
-      }
-
-      case CH34X_REQ_SERIAL_INIT:
-        // serial init request (set line coding incl. baudrate)
-        p_cdc->line_coding = p_cdc->requested_line_coding;
-        break;
-
-      default:
-        TU_ASSERT(false,); // unexpected request
-        break;
-    }
-
-    xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb) {
-      xfer->complete_cb(xfer);
-    }
-  }
+  process_internal_control_complete(p_cdc, xfer);
 }
 
 //static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
 //                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
 //  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+//  p_cdc->requested_line_coding.stop_bits = stop_bits;
+//  p_cdc->requested_line_coding.parity = parity;
+//  p_cdc->requested_line_coding.data_bits = data_bits;
+//
 //  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
 //                                complete_cb ? ch34x_control_complete : NULL, user_data));
 //  return false;
@@ -1350,16 +1341,21 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->requested_line_coding.bit_rate = baudrate;
-  p_cdc->user_control_cb = complete_cb;
   uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
   TU_VERIFY(div_ps != 0);
+
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
                             complete_cb ? ch34x_control_complete : NULL, user_data));
 
   return true;
 }
 
+//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) {
+//
+//}
+
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
 //  p_cdc->baudrate_requested = line_coding->bit_rate;

From 98781bb903d94190d57ad4b9436a85a31d67404c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 15:58:05 +0700
Subject: [PATCH 15/19] - add ch34x_set_data_format() - add
 ch34x_set_line_coding()

---
 examples/host/cdc_msc_hid/src/cdc_app.c |  68 +++++++--------
 src/class/cdc/cdc_host.c                | 110 ++++++++++++++++--------
 src/class/cdc/serial/ch34x.h            |   3 +-
 3 files changed, 107 insertions(+), 74 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index a1b26e49c..81052047c 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -27,20 +27,11 @@
 #include "tusb.h"
 #include "bsp/board_api.h"
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-
-//------------- IMPLEMENTATION -------------//
-
-size_t get_console_inputs(uint8_t* buf, size_t bufsize)
-{
+size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
   size_t count = 0;
-  while (count < bufsize)
-  {
+  while (count < bufsize) {
     int ch = board_getchar();
-    if ( ch <= 0 ) break;
+    if (ch <= 0) break;
 
     buf[count] = (uint8_t) ch;
     count++;
@@ -49,22 +40,18 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize)
   return count;
 }
 
-void cdc_app_task(void)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void cdc_app_task(void) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   uint32_t count = get_console_inputs(buf, bufsize);
   buf[count] = 0;
 
   // loop over all mounted interfaces
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
-    if ( tuh_cdc_mounted(idx) )
-    {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+    if (tuh_cdc_mounted(idx)) {
       // console --> cdc interfaces
-      if (count)
-      {
+      if (count) {
         tuh_cdc_write(idx, buf, count);
         tuh_cdc_write_flush(idx);
       }
@@ -72,11 +59,14 @@ void cdc_app_task(void)
   }
 }
 
+//--------------------------------------------------------------------+
+// TinyUSB callbacks
+//--------------------------------------------------------------------+
+
 // Invoked when received new data
-void tuh_cdc_rx_cb(uint8_t idx)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   // forward cdc interfaces -> console
   uint32_t count = tuh_cdc_read(idx, buf, bufsize);
@@ -85,29 +75,31 @@ void tuh_cdc_rx_cb(uint8_t idx)
   printf((char*) buf);
 }
 
-void tuh_cdc_mount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is mounted
+// idx is index of cdc interface in the internal pool.
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
   // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
   // otherwise you need to call tuh_cdc_set_line_coding() first
-  cdc_line_coding_t line_coding = { 0 };
-  if ( tuh_cdc_get_local_line_coding(idx, &line_coding) )
-  {
+  cdc_line_coding_t line_coding = {0};
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
     printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
-    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity  , line_coding.data_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
 #endif
 }
 
-void tuh_cdc_umount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is unmounted
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 }
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index bfaa64a77..37fa30982 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1327,48 +1327,88 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   process_internal_control_complete(p_cdc, xfer);
 }
 
-//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
-//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-//  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
-//  p_cdc->requested_line_coding.stop_bits = stop_bits;
-//  p_cdc->requested_line_coding.parity = parity;
-//  p_cdc->requested_line_coding.data_bits = data_bits;
-//
-//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
-//                                complete_cb ? ch34x_control_complete : NULL, user_data));
-//  return false;
-//}
-
-static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
-  TU_VERIFY(div_ps != 0);
-
-  p_cdc->requested_line_coding.bit_rate = baudrate;
-  p_cdc->user_control_cb = complete_cb;
-  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
-                            complete_cb ? ch34x_control_complete : NULL, user_data));
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.stop_bits = stop_bits;
+  p_cdc->requested_line_coding.parity = parity;
+  p_cdc->requested_line_coding.data_bits = data_bits;
 
+  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
-//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) {
-//
-//}
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
 
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
+                                     complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    // stage 1 success, continue to stage 2
+    p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+    TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
+                                    p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), );
+  } else {
+    // stage 1 failed, notify user
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
+  }
+}
+
+// 2 stages: set baudrate (stage1) + set data format (stage2)
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-//  p_cdc->baudrate_requested = line_coding->bit_rate;
-//  p_cdc->user_control_cb = complete_cb;
-//  uint8_t factor, divisor, lcr;
-//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
-//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
-//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-//                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  (void) p_cdc;
-  (void) line_coding;
-  (void) complete_cb;
-  (void) user_data;
+  p_cdc->requested_line_coding = *line_coding;
+  p_cdc->user_control_cb = complete_cb;
+
+  if (complete_cb) {
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate,
+                                       ch34x_set_line_coding_stage1_complete, user_data));
+  } else {
+    // sync call
+    xfer_result_t result;
+
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.bit_rate = line_coding->bit_rate;
+
+    // stage 2 set data format
+    TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits,
+                                    NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = line_coding->stop_bits;
+    p_cdc->line_coding.parity = line_coding->parity;
+    p_cdc->line_coding.data_bits = line_coding->data_bits;
+
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (user_data) {
+      user_data = result;
+    }
+  }
 
   return true;
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 3f78a3007..5def8d212 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -63,7 +63,8 @@
 #define CH341_REG_0x2C         0x2C // undocumented register
 #define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
 
-#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
 
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )

From c196a2ed9cbd27188472d76ec428fdb24931d0b6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 16:04:30 +0700
Subject: [PATCH 16/19] move code around

---
 src/class/cdc/cdc_host.c | 94 +++++++++++++++++++++-------------------
 1 file changed, 49 insertions(+), 45 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 37fa30982..8965ee261 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1223,46 +1223,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #if CFG_TUH_CDC_CH34X
 
-enum {
-  CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SERIAL_INIT,
-  CONFIG_CH34X_SPECIAL_REG_WRITE,
-  CONFIG_CH34X_FLOW_CONTROL,
-  CONFIG_CH34X_MODEM_CONTROL,
-  CONFIG_CH34X_COMPLETE
-};
-
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
 static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
 
-static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
-  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
-  TU_VERIFY (itf_desc->bNumEndpoints == 3);
-  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
-
-  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
-  TU_VERIFY (p_cdc);
-
-  TU_LOG_DRV ("CH34x opened\r\n");
-  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
-
-  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
-
-  // data endpoints expected to be in pairs
-  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
-  desc_ep += 2;
-
-  // Interrupt endpoint: not used for now
-  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
-            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
-  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
-  p_cdc->ep_notif = desc_ep->bEndpointAddress;
-
-  return true;
-}
-
+//------------- control requestt -------------//
 static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
-                  uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
@@ -1318,6 +1284,17 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_
 //  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
+
+//------------- Driver API -------------//
+
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
@@ -1339,15 +1316,6 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
   return true;
 }
 
-static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
-  TU_VERIFY(div_ps != 0);
-  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
-                            complete_cb, user_data));
-  return true;
-}
-
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->requested_line_coding.bit_rate = baudrate;
@@ -1432,6 +1400,42 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
   return true;
 }
 
+//------------- Enumeration -------------//
+enum {
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
+
+  TU_LOG_DRV ("CH34x opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
+}
+
 static void ch34x_process_config(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
   uint8_t const itf_num = 0;

From 55cb713264a1fe531b548a05290ee8fe1289828f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 16:56:32 +0700
Subject: [PATCH 17/19] - add new API tuh_cdc_set_data_format() - add typedef
 for cdc enum

---
 src/class/cdc/cdc.h      | 20 ++++-----
 src/class/cdc/cdc_host.c | 90 +++++++++++++++++++++++++++++++++++-----
 src/class/cdc/cdc_host.h | 13 +++---
 3 files changed, 95 insertions(+), 28 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index deec32ae4..5cbd658fe 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -136,8 +136,7 @@ typedef enum{
 //--------------------------------------------------------------------+
 
 /// Communication Interface Management Element Request Codes
-typedef enum
-{
+typedef enum {
   CDC_REQUEST_SEND_ENCAPSULATED_COMMAND                    = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
   CDC_REQUEST_GET_ENCAPSULATED_RESPONSE                    = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
   CDC_REQUEST_SET_COMM_FEATURE                             = 0x02,
@@ -180,39 +179,38 @@ typedef enum
   CDC_REQUEST_GET_ATM_VC_STATISTICS                        = 0x53,
 
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
-}cdc_management_request_t;
+} cdc_management_request_t;
 
-enum {
+typedef enum {
   CDC_CONTROL_LINE_STATE_DTR = 0x01,
   CDC_CONTROL_LINE_STATE_RTS = 0x02,
-};
+} cdc_control_line_state_t;
 
-enum {
+typedef enum {
   CDC_LINE_CODING_STOP_BITS_1   = 0, // 1   bit
   CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
   CDC_LINE_CODING_STOP_BITS_2   = 2, // 2   bits
-};
+} cdc_line_coding_stopbits_t;
 
 // TODO Backward compatible for typos. Maybe removed in the future release
 #define CDC_LINE_CONDING_STOP_BITS_1   CDC_LINE_CODING_STOP_BITS_1
 #define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
 #define CDC_LINE_CONDING_STOP_BITS_2   CDC_LINE_CODING_STOP_BITS_2
 
-enum {
+typedef enum {
   CDC_LINE_CODING_PARITY_NONE  = 0,
   CDC_LINE_CODING_PARITY_ODD   = 1,
   CDC_LINE_CODING_PARITY_EVEN  = 2,
   CDC_LINE_CODING_PARITY_MARK  = 3,
   CDC_LINE_CODING_PARITY_SPACE = 4,
-};
+} cdc_line_coding_parity_t;
 
 //--------------------------------------------------------------------+
 // Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
 /// 6.3 Notification Codes
-typedef enum
-{
+typedef enum {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
   CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 8965ee261..f5182efc2 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -90,9 +90,10 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC];
 static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void acm_process_config(tuh_xfer_t* xfer);
 
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 //------------- FTDI prototypes -------------//
 #if CFG_TUH_CDC_FTDI
@@ -100,15 +101,13 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 
 static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
-// Store last request baudrate since divisor to baudrate is not easy
-// static uint32_t _ftdi_requested_baud;
-
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
 
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- CP210X prototypes -------------//
@@ -120,9 +119,10 @@ static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIS
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
 
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- CH34x prototypes -------------//
@@ -131,16 +131,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
-static void ch34x_process_config ( tuh_xfer_t* xfer );
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len);
+static void ch34x_process_config(tuh_xfer_t* xfer);
 
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- Common -------------//
-
 enum {
   SERIAL_DRIVER_ACM = 0,
 
@@ -166,6 +166,7 @@ typedef struct {
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 } cdch_serial_driver_t;
 
@@ -178,6 +179,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = acm_process_config,
       .set_control_line_state = acm_set_control_line_state,
       .set_baudrate           = acm_set_baudrate,
+      .set_data_format        = acm_set_data_format,
       .set_line_coding        = acm_set_line_coding
   },
 
@@ -189,6 +191,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = ftdi_process_config,
       .set_control_line_state = ftdi_sio_set_modem_ctrl,
       .set_baudrate           = ftdi_sio_set_baudrate,
+      .set_data_format        = ftdi_set_data_format,
       .set_line_coding        = ftdi_set_line_coding
   },
   #endif
@@ -201,6 +204,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = cp210x_process_config,
       .set_control_line_state = cp210x_set_modem_ctrl,
       .set_baudrate           = cp210x_set_baudrate,
+      .set_data_format        = cp210x_set_data_format,
       .set_line_coding        = cp210x_set_line_coding
   },
   #endif
@@ -213,6 +217,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = ch34x_process_config,
       .set_control_line_state = ch34x_set_modem_ctrl,
       .set_baudrate           = ch34x_set_baudrate,
+      .set_data_format        = ch34x_set_data_format,
       .set_line_coding        = ch34x_set_line_coding
   },
   #endif
@@ -562,6 +567,32 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   }
 }
 
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if (complete_cb) {
+    return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = stop_bits;
+    p_cdc->line_coding.parity = parity;
+    p_cdc->line_coding.data_bits = data_bits;
+    return true;
+  }
+}
+
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
@@ -900,6 +931,19 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const
   return true;
 }
 
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC ACM Set Data Format\r\n");
+
+  cdc_line_coding_t line_coding;
+  line_coding.bit_rate = p_cdc->line_coding.bit_rate;
+  line_coding.stop_bits = stop_bits;
+  line_coding.parity = parity;
+  line_coding.data_bits = data_bits;
+
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
 static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
   cdc_line_coding_t line_coding = p_cdc->line_coding;
@@ -968,6 +1012,18 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
 static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   (void) p_cdc;
   (void) line_coding;
@@ -1161,6 +1217,18 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9e5edd94e..d512a23a5 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -148,8 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 // Request to set baudrate
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-// Request to Set Line Coding (ACM only)
-// Should only use if you don't work with serial devices such as FTDI/CP210x
+// Request to set data format
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Set Line Coding = baudrate + data format
+// Note: only implemented by ACM and CH34x, not supported by FTDI and CP210x yet
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to Get Line Coding (ACM only)
@@ -159,15 +162,13 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 
 // Connect by set both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
 // Disconnect by clear both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }
 

From 87d509d416ea7c250f4256f897f6cc9a7b7d2121 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 20 Jan 2024 01:42:31 +0700
Subject: [PATCH 18/19] make CFG_TUH_CDC_LINE_CODING_ON_ENUM optional for ch34x

---
 examples/host/cdc_msc_hid/src/cdc_app.c |  8 ++++++--
 src/class/cdc/cdc_host.c                | 19 ++++++++++++++-----
 src/class/cdc/serial/ch34x.h            | 12 +-----------
 3 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 81052047c..e275e7943 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -85,13 +85,17 @@ void tuh_cdc_mount_cb(uint8_t idx) {
          itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
-  // otherwise you need to call tuh_cdc_set_line_coding() first
+  // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack
+  // while eneumerating new cdc device
   cdc_line_coding_t line_coding = {0};
   if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
     printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
     printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
+#else
+  // Set Line Coding upon mounted
+  cdc_line_coding_t new_line_coding = { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 };
+  tuh_cdc_set_line_coding(idx, &new_line_coding, NULL, 0);
 #endif
 }
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f5182efc2..cd948243d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1510,10 +1510,11 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   uintptr_t const state = xfer->user_data;
-  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
   uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
 
+  // TODO check xfer->result
+
   switch (state) {
     case CONFIG_CH34X_READ_VERSION:
       TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
@@ -1527,20 +1528,28 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
 
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      uint16_t const first_arg = tu_u16(lcr, 0x9c);
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
       TU_ASSERT(div_ps != 0, );
-
-      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      #else
+      uint16_t const first_arg = 0;
+      uint16_t const div_ps = 0;
+      #endif
 
       // Init CH34x with line coding
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
 
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
-      p_cdc->line_coding = line_coding;
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM);
+      #endif
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
 
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 5def8d212..b9121afb3 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,21 +27,11 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
-// For simplicity, only the name CH34X is used here,
-// but specifically only CH340 and CH341 are supported.
-
-// There is no official documentation for the CH34x chips. Reference can be found
+// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
 // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
-// set line_coding @ enumeration
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
-#else // this default is necessary to work properly
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
-#endif
-
 // USB requests
 #define CH34X_REQ_READ_VERSION 0x5F // dec  95
 #define CH34X_REQ_WRITE_REG    0x9A // dec 154

From 769a237b19bbe5254e1c83869b463c79afb1af34 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 20 Jan 2024 20:34:50 +0100
Subject: [PATCH 19/19] accumulated review changes

---
 src/class/cdc/cdc_host.c     | 68 ++++++++++++++++--------------------
 src/class/cdc/serial/ch34x.h |  7 ++++
 2 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index cd948243d..7adaa0c8c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -401,7 +401,9 @@ bool tuh_cdc_read_clear (uint8_t idx) {
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) {
+static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) {
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
   uint16_t const value = tu_le16toh(xfer->setup->wValue);
 
@@ -515,10 +517,7 @@ static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_
 // internal control complete to update state such as line state, encoding
 static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
-
-  process_internal_control_complete(p_cdc, xfer);
+  process_internal_control_complete(xfer, itf_num);
 }
 
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
@@ -1294,7 +1293,8 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
 static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
 
-//------------- control requestt -------------//
+//------------- control request -------------//
+
 static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
                               uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
@@ -1366,10 +1366,7 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
-  uint8_t const itf_num = 0;
-  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
-  process_internal_control_complete(p_cdc, xfer);
+  process_internal_control_complete(xfer, 0);
 }
 
 static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
@@ -1379,6 +1376,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
   p_cdc->requested_line_coding.data_bits = data_bits;
 
   uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_VERIFY(lcr != 0);
   TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
                                complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
@@ -1527,35 +1525,26 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
-      uint16_t const first_arg = tu_u16(lcr, 0x9c);
+      // init CH34x with line coding
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
       TU_ASSERT(div_ps != 0, );
-      #else
-      uint16_t const first_arg = 0;
-      uint16_t const div_ps = 0;
-      #endif
-
-      // Init CH34x with line coding
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps,
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT(lcr != 0, );
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
 
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
-      // do special reg write, purpose unknown, overtaken from WCH driver
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM);
-      #endif
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
+      // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
 
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
 
     case CONFIG_CH34X_MODEM_CONTROL:
@@ -1581,6 +1570,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t b;
   uint32_t c;
 
+  TU_VERIFY(baval != 0, 0);
   switch (baval) {
     case 921600:
       a = 0xf3;
@@ -1606,7 +1596,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
         b = 0;
         c = 11719;
       }
-      a = (unsigned char) (c / baval);
+      a = (uint8_t) (c / baval);
       if (a == 0 || a == 0xFF) {
         return 0;
       }
@@ -1620,29 +1610,33 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   // reg divisor = a, reg prescaler = b
   // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
   // otherwise the chip will buffer data.
-  return (uint16_t) (a << 8 | 0x80 | b);
+  return (uint16_t) ((uint16_t)a << 8 | 0x80 | b);
 }
 
 // calculate lcr value from data coding
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
   uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-  TU_VERIFY(data_bits >= 5, 0);
+  TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0);
   lcr |= (uint8_t) (data_bits - 5);
 
-  if (parity) {
-    lcr |= CH34X_LCR_ENABLE_PAR;
-  }
   switch(parity) {
+    case CDC_LINE_CODING_PARITY_NONE:
+      break;
+
+    case CDC_LINE_CODING_PARITY_ODD:
+    lcr |= CH34X_LCR_ENABLE_PAR;
+      break;
+
     case CDC_LINE_CODING_PARITY_EVEN:
-      lcr |= CH34X_LCR_PAR_EVEN;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN;
       break;
 
     case CDC_LINE_CODING_PARITY_MARK:
-      lcr |= CH34X_LCR_MARK_SPACE;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE;
       break;
 
     case CDC_LINE_CODING_PARITY_SPACE:
-      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
       break;
 
     default: break;
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index b9121afb3..c18066f57 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -32,6 +32,13 @@
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
 // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
+
 // USB requests
 #define CH34X_REQ_READ_VERSION 0x5F // dec  95
 #define CH34X_REQ_WRITE_REG    0x9A // dec 154