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mass rename tusb_dcd API to simply dcd

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This commit is contained in:
hathach 2018-03-28 13:47:58 +07:00
parent 5b4f948eec
commit 4deb4da6cb
10 changed files with 125 additions and 125 deletions
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12
tinyusb/class/cdc/cdc_device.c
View File

@ -159,7 +159,7 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
if ( TUSB_DESC_ENDPOINT == p_desc[DESCRIPTOR_OFFSET_TYPE])
{ // notification endpoint if any
TU_ASSERT( tusb_dcd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), TUSB_ERROR_DCD_OPEN_PIPE_FAILED);
TU_ASSERT( dcd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), TUSB_ERROR_DCD_OPEN_PIPE_FAILED);
p_cdc->ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
@ -181,7 +181,7 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
TU_ASSERT(TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
TU_ASSERT( tusb_dcd_edpt_open(rhport, p_endpoint), TUSB_ERROR_DCD_OPEN_PIPE_FAILED);
TU_ASSERT( dcd_edpt_open(rhport, p_endpoint), TUSB_ERROR_DCD_OPEN_PIPE_FAILED);
if ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK )
{
@ -199,7 +199,7 @@ tusb_error_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
p_cdc->interface_number = p_interface_desc->bInterfaceNumber;
// Prepare for incoming data
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
TU_ASSERT( dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
return TUSB_ERROR_NONE;
@ -277,7 +277,7 @@ tusb_error_t cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
fifo_write_n(&_rx_ff, _tmp_rx_buf, xferred_bytes);
// preparing for next
TU_ASSERT(tusb_dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
TU_ASSERT(dcd_edpt_xfer(rhport, p_cdc->ep_out, _tmp_rx_buf, sizeof(_tmp_rx_buf)), TUSB_ERROR_DCD_EDPT_XFER);
// fire callback
tud_cdc_rx_cb(rhport);
@ -292,10 +292,10 @@ bool tud_n_cdc_flush (uint8_t rhport)
uint8_t edpt = cdcd_data[rhport].ep_in;
VERIFY( !tusb_dcd_edpt_busy(rhport, edpt) );
VERIFY( !dcd_edpt_busy(rhport, edpt) );
uint16_t count = fifo_read_n(&_tx_ff, _tmp_tx_buf, sizeof(_tmp_tx_buf));
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, edpt, _tmp_tx_buf, count) );
TU_ASSERT( dcd_edpt_xfer(rhport, edpt, _tmp_tx_buf, count) );
return true;
}

10
tinyusb/class/hid/hid_device.c
View File

@ -110,7 +110,7 @@ STATIC_VAR hidd_interface_t keyboardd_data;
bool tud_hid_keyboard_busy(uint8_t rhport)
{
return tusb_dcd_edpt_busy(rhport, keyboardd_data.edpt_addr);
return dcd_edpt_busy(rhport, keyboardd_data.edpt_addr);
}
tusb_error_t tud_hid_keyboard_send(uint8_t rhport, hid_keyboard_report_t const *p_report)
@ -119,7 +119,7 @@ tusb_error_t tud_hid_keyboard_send(uint8_t rhport, hid_keyboard_report_t const *
hidd_interface_t * p_kbd = &keyboardd_data; // TODO &keyboardd_data[rhport];
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
TU_ASSERT( dcd_edpt_xfer(rhport, p_kbd->edpt_addr, (void*) p_report, sizeof(hid_keyboard_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
return TUSB_ERROR_NONE;
}
@ -133,7 +133,7 @@ STATIC_VAR hidd_interface_t moused_data;
bool tud_hid_mouse_is_busy(uint8_t rhport)
{
return tusb_dcd_edpt_busy(rhport, moused_data.edpt_addr);
return dcd_edpt_busy(rhport, moused_data.edpt_addr);
}
tusb_error_t tud_hid_mouse_send(uint8_t rhport, hid_mouse_report_t const *p_report)
@ -142,7 +142,7 @@ tusb_error_t tud_hid_mouse_send(uint8_t rhport, hid_mouse_report_t const *p_repo
hidd_interface_t * p_mouse = &moused_data; // TODO &keyboardd_data[rhport];
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
TU_ASSERT( dcd_edpt_xfer(rhport, p_mouse->edpt_addr, (void*) p_report, sizeof(hid_mouse_report_t)), TUSB_ERROR_DCD_EDPT_XFER ) ;
return TUSB_ERROR_NONE;
}
@ -283,7 +283,7 @@ tusb_error_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
VERIFY(p_hid, TUSB_ERROR_FAILED);
VERIFY( tusb_dcd_edpt_open(rhport, p_desc_endpoint), TUSB_ERROR_DCD_FAILED );
VERIFY( dcd_edpt_open(rhport, p_desc_endpoint), TUSB_ERROR_DCD_FAILED );
p_hid->edpt_addr = p_desc_endpoint->bEndpointAddress;

16
tinyusb/class/msc/msc_device.c
View File

@ -112,7 +112,7 @@ tusb_error_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
TU_ASSERT(TUSB_DESC_ENDPOINT == p_endpoint->bDescriptorType &&
TUSB_XFER_BULK == p_endpoint->bmAttributes.xfer, TUSB_ERROR_DESCRIPTOR_CORRUPTED);
TU_ASSERT( tusb_dcd_edpt_open(rhport, p_endpoint), TUSB_ERROR_DCD_FAILED );
TU_ASSERT( dcd_edpt_open(rhport, p_endpoint), TUSB_ERROR_DCD_FAILED );
if ( p_endpoint->bEndpointAddress & TUSB_DIR_IN_MASK )
{
@ -130,7 +130,7 @@ tusb_error_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * p_interface
(*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
//------------- Queue Endpoint OUT for Command Block Wrapper -------------//
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_DCD_EDPT_XFER );
TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), TUSB_ERROR_DCD_EDPT_XFER );
return TUSB_ERROR_NONE;
}
@ -223,14 +223,14 @@ tusb_error_t mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
if ( p_buffer == NULL || p_msc->data_len == 0 )
{
// application does not provide data to response --> possibly unsupported SCSI command
tusb_dcd_edpt_stall(rhport, ep_data);
dcd_edpt_stall(rhport, ep_data);
p_csw->status = MSC_CSW_STATUS_FAILED;
p_msc->stage = MSC_STAGE_STATUS;
}else
{
memcpy(p_msc->scsi_data, p_buffer, p_msc->data_len);
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, ep_data, p_msc->scsi_data, p_msc->data_len), TUSB_ERROR_DCD_EDPT_XFER );
TU_ASSERT( dcd_edpt_xfer(rhport, ep_data, p_msc->scsi_data, p_msc->data_len), TUSB_ERROR_DCD_EDPT_XFER );
}
}
}
@ -264,10 +264,10 @@ tusb_error_t mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_event_t event, u
// Move to default CMD stage after sending status
p_msc->stage = MSC_STAGE_CMD;
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
//------------- Queue the next CBW -------------//
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
TU_ASSERT( dcd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
}
return TUSB_ERROR_NONE;
@ -311,12 +311,12 @@ static bool read10_write10_data_xfer(uint8_t rhport, mscd_interface_t* p_msc)
p_csw->data_residue = p_cbw->xfer_bytes;
p_csw->status = MSC_CSW_STATUS_FAILED;
tusb_dcd_edpt_stall(rhport, ep_data);
dcd_edpt_stall(rhport, ep_data);
return true;
}else
{
TU_ASSERT( tusb_dcd_edpt_xfer(rhport, ep_data, p_buffer, xfer_block * block_size) );
TU_ASSERT( dcd_edpt_xfer(rhport, ep_data, p_buffer, xfer_block * block_size) );
}
return true;

32
tinyusb/device/dcd.h
View File

@ -61,39 +61,39 @@ typedef enum
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
bool tusb_dcd_init (uint8_t rhport);
void tusb_dcd_connect (uint8_t rhport);
void tusb_dcd_disconnect (uint8_t rhport);
void tusb_dcd_set_address (uint8_t rhport, uint8_t dev_addr);
void tusb_dcd_set_config (uint8_t rhport, uint8_t config_num);
bool dcd_init (uint8_t rhport);
void dcd_connect (uint8_t rhport);
void dcd_disconnect (uint8_t rhport);
void dcd_set_address (uint8_t rhport, uint8_t dev_addr);
void dcd_set_config (uint8_t rhport, uint8_t config_num);
/*------------------------------------------------------------------*/
/* Event Function
* Called by DCD to notify USBD
*------------------------------------------------------------------*/
void tusb_dcd_bus_event (uint8_t rhport, usbd_bus_event_type_t bus_event);
void tusb_dcd_setup_received (uint8_t rhport, uint8_t const* p_request);
void tusb_dcd_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, bool succeeded);
void dcd_bus_event (uint8_t rhport, usbd_bus_event_type_t bus_event);
void dcd_setup_received (uint8_t rhport, uint8_t const* p_request);
void dcd_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, bool succeeded);
static inline void tusb_dcd_control_complete(uint8_t rhport)
static inline void dcd_control_complete(uint8_t rhport)
{
// TODO all control complete is successful !!
tusb_dcd_xfer_complete(rhport, 0, 0, true);
dcd_xfer_complete(rhport, 0, 0, true);
}
/*------------------------------------------------------------------*/
/* Endpoint API
*------------------------------------------------------------------*/
//------------- Control Endpoint -------------//
bool tusb_dcd_control_xfer (uint8_t rhport, tusb_dir_t dir, uint8_t * buffer, uint16_t length);
bool dcd_control_xfer (uint8_t rhport, tusb_dir_t dir, uint8_t * buffer, uint16_t length);
//------------- Other Endpoints -------------//
bool tusb_dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
bool tusb_dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
bool tusb_dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr);
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
bool dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr);
void tusb_dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
void tusb_dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
#ifdef __cplusplus
}

20
tinyusb/device/usbd.c
View File

@ -201,11 +201,11 @@ static tusb_error_t usbd_main_stk(void);
tusb_error_t usbd_init (void)
{
#if (TUSB_CFG_CONTROLLER_0_MODE & TUSB_MODE_DEVICE)
tusb_dcd_init(0);
dcd_init(0);
#endif
#if (TUSB_CFG_CONTROLLER_1_MODE & TUSB_MODE_DEVICE)
tusb_dcd_init(1);
dcd_init(1);
#endif
//------------- Task init -------------//
@ -319,7 +319,7 @@ tusb_error_t usbd_control_xfer_st(uint8_t rhport, tusb_dir_t dir, uint8_t * buff
// Data
if ( length )
{
tusb_dcd_control_xfer(rhport, dir, buffer, length);
dcd_control_xfer(rhport, dir, buffer, length);
osal_semaphore_wait( usbd_control_xfer_sem_hdl, 100, &error );
STASK_ASSERT_STATUS( error );
@ -327,7 +327,7 @@ tusb_error_t usbd_control_xfer_st(uint8_t rhport, tusb_dir_t dir, uint8_t * buff
// Status opposite direction with Zero Length
// No need to wait for status to complete therefore
// status phase must not call tusb_dcd_control_complete/tusb_dcd_xfer_complete
// status phase must not call dcd_control_complete/dcd_xfer_complete
usbd_control_status(rhport, dir);
OSAL_SUBTASK_END
@ -364,7 +364,7 @@ static tusb_error_t proc_control_request_st(uint8_t rhport, tusb_control_request
}
else if ( TUSB_REQ_SET_ADDRESS == p_request->bRequest )
{
tusb_dcd_set_address(rhport, (uint8_t) p_request->wValue);
dcd_set_address(rhport, (uint8_t) p_request->wValue);
usbd_devices[rhport].state = TUSB_DEVICE_STATE_ADDRESSED;
#ifndef NRF52840_XXAA // nrf52 auto handle set address, we must not return status
@ -406,7 +406,7 @@ static tusb_error_t proc_control_request_st(uint8_t rhport, tusb_control_request
{
if (TUSB_REQ_CLEAR_FEATURE == p_request->bRequest )
{
tusb_dcd_edpt_clear_stall(rhport, u16_low_u8(p_request->wIndex) );
dcd_edpt_clear_stall(rhport, u16_low_u8(p_request->wIndex) );
usbd_control_status(rhport, p_request->bmRequestType_bit.direction);
} else
{
@ -427,7 +427,7 @@ static tusb_error_t proc_control_request_st(uint8_t rhport, tusb_control_request
// may need to open interface before set configured
static tusb_error_t proc_set_config_req(uint8_t rhport, uint8_t config_number)
{
tusb_dcd_set_config(rhport, config_number);
dcd_set_config(rhport, config_number);
usbd_devices[rhport].state = TUSB_DEVICE_STATE_CONFIGURED;
usbd_devices[rhport].config_num = config_number;
@ -526,7 +526,7 @@ static uint16_t get_descriptor(uint8_t rhport, tusb_control_request_t const * co
//--------------------------------------------------------------------+
// USBD-DCD Callback API
//--------------------------------------------------------------------+
void tusb_dcd_bus_event(uint8_t rhport, usbd_bus_event_type_t bus_event)
void dcd_bus_event(uint8_t rhport, usbd_bus_event_type_t bus_event)
{
switch(bus_event)
{
@ -564,7 +564,7 @@ void tusb_dcd_bus_event(uint8_t rhport, usbd_bus_event_type_t bus_event)
}
}
void tusb_dcd_setup_received(uint8_t rhport, uint8_t const* p_request)
void dcd_setup_received(uint8_t rhport, uint8_t const* p_request)
{
usbd_task_event_t task_event =
{
@ -576,7 +576,7 @@ void tusb_dcd_setup_received(uint8_t rhport, uint8_t const* p_request)
osal_queue_send(usbd_queue_hdl, &task_event);
}
void tusb_dcd_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, bool succeeded)
void dcd_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, bool succeeded)
{
if (ep_addr == 0 )
{

4
tinyusb/device/usbd_pvt.h
View File

@ -57,12 +57,12 @@ tusb_error_t usbd_control_xfer_st(uint8_t rhport, tusb_dir_t dir, uint8_t * buff
static inline bool usbd_control_status(uint8_t rhport, tusb_dir_t dir)
{
// status direction is reversed to one in the setup packet
return tusb_dcd_control_xfer(rhport, 1-dir, NULL, 0);
return dcd_control_xfer(rhport, 1-dir, NULL, 0);
}
static inline void usbd_control_stall(uint8_t rhport)
{
tusb_dcd_edpt_stall(rhport, 0);
dcd_edpt_stall(rhport, 0);
}

38
tinyusb/portable/nordic/nrf5x/dcd_nrf5x.c
View File

@ -230,7 +230,7 @@ void bus_reset(void)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
bool tusb_dcd_init (uint8_t rhport)
bool dcd_init (uint8_t rhport)
{
// USB Power detection
const nrf_drv_power_usbevt_config_t config =
@ -240,22 +240,22 @@ bool tusb_dcd_init (uint8_t rhport)
return ( NRF_SUCCESS == nrf_drv_power_usbevt_init(&config) );
}
void tusb_dcd_connect (uint8_t rhport)
void dcd_connect (uint8_t rhport)
{
}
void tusb_dcd_disconnect (uint8_t rhport)
void dcd_disconnect (uint8_t rhport)
{
}
void tusb_dcd_set_address (uint8_t rhport, uint8_t dev_addr)
void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
{
(void) rhport;
// Set Address is automatically update by hw controller
}
void tusb_dcd_set_config (uint8_t rhport, uint8_t config_num)
void dcd_set_config (uint8_t rhport, uint8_t config_num)
{
(void) rhport;
(void) config_num;
@ -327,12 +327,12 @@ static void control_xact_start(void)
// }
// }else
// {
// tusb_dcd_xfer_complete(0, 0, 0, true);
// dcd_xfer_complete(0, 0, 0, true);
// }
//}
bool tusb_dcd_control_xfer (uint8_t rhport, tusb_dir_t dir, uint8_t * buffer, uint16_t length)
bool dcd_control_xfer (uint8_t rhport, tusb_dir_t dir, uint8_t * buffer, uint16_t length)
{
(void) rhport;
@ -391,7 +391,7 @@ static void normal_xact_start(uint8_t epnum, uint8_t dir)
}
}
bool tusb_dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
{
(void) rhport;
@ -414,7 +414,7 @@ bool tusb_dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
return true;
}
bool tusb_dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
(void) rhport;
@ -438,7 +438,7 @@ bool tusb_dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint
return true;
}
void tusb_dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
@ -453,7 +453,7 @@ void tusb_dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
__ISB(); __DSB();
}
void tusb_dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
if ( ep_addr )
@ -462,7 +462,7 @@ void tusb_dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
}
}
bool tusb_dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr)
bool dcd_edpt_busy (uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
@ -505,12 +505,12 @@ void USBD_IRQHandler(void)
{
bus_reset();
tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESET);
dcd_bus_event(0, USBD_BUS_EVENT_RESET);
}
if ( int_status & USBD_INTEN_SOF_Msk )
{
tusb_dcd_bus_event(0, USBD_BUS_EVENT_SOF);
dcd_bus_event(0, USBD_BUS_EVENT_SOF);
}
if ( int_status & EDPT_END_ALL_MASK )
@ -527,7 +527,7 @@ void USBD_IRQHandler(void)
NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
};
tusb_dcd_setup_received(0, setup);
dcd_setup_received(0, setup);
}
if ( int_status & USBD_INTEN_EP0DATADONE_Msk )
@ -546,7 +546,7 @@ void USBD_IRQHandler(void)
}else
{
// Control IN complete
tusb_dcd_xfer_complete(0, 0, 0, true);
dcd_xfer_complete(0, 0, 0, true);
}
}
}
@ -560,7 +560,7 @@ void USBD_IRQHandler(void)
}else
{
// Control OUT complete
tusb_dcd_xfer_complete(0, 0, 0, true);
dcd_xfer_complete(0, 0, 0, true);
}
}
@ -587,7 +587,7 @@ void USBD_IRQHandler(void)
} else
{
// BULK/INT IN complete
tusb_dcd_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, true);
dcd_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, true);
}
}
}
@ -644,7 +644,7 @@ void USBD_IRQHandler(void)
xfer->total_len = xfer->actual_len;
// BULK/INT OUT complete
tusb_dcd_xfer_complete(0, epnum, xfer->actual_len, true);
dcd_xfer_complete(0, epnum, xfer->actual_len, true);
}
}
}

44
tinyusb/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
View File

@ -108,7 +108,7 @@ typedef struct ATTR_PACKED
STATIC_ASSERT( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
// If there is another tusb_dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
// next_td stored the 2nd request information
// current_td is used to keep track of number of remaining & xferred bytes of the current request.
// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
@ -164,18 +164,18 @@ static void queue_xfer_in_next_td(uint8_t ep_id);
//--------------------------------------------------------------------+
// CONTROLLER API
//--------------------------------------------------------------------+
void tusb_dcd_connect(uint8_t rhport)
void dcd_connect(uint8_t rhport)
{
(void) rhport;
LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
}
void tusb_dcd_set_config(uint8_t rhport, uint8_t config_num)
void dcd_set_config(uint8_t rhport, uint8_t config_num)
{
}
void tusb_dcd_set_address(uint8_t rhport, uint8_t dev_addr)
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
(void) rhport;
@ -183,7 +183,7 @@ void tusb_dcd_set_address(uint8_t rhport, uint8_t dev_addr)
LPC_USB->DEVCMDSTAT |= dev_addr;
}
bool tusb_dcd_init(uint8_t rhport)
bool dcd_init(uint8_t rhport)
{
(void) rhport;
@ -258,7 +258,7 @@ static void endpoint_non_control_isr(uint32_t int_status)
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
// TODO no way determine if the transfer is failed or not
tusb_dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
}
//------------- Next TD is available -------------//
@ -293,7 +293,7 @@ static void endpoint_control_isr(uint32_t int_status)
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
// FIXME xferred_byte for control xfer is not needed now !!!
tusb_dcd_xfer_complete(edpt_hdl, 0, true);
dcd_xfer_complete(edpt_hdl, 0, true);
}
}
}
@ -317,14 +317,14 @@ void hal_dcd_isr(uint8_t rhport)
if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
{
bus_reset();
tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESET);
dcd_bus_event(0, USBD_BUS_EVENT_RESET);
}
if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
{ // device disconnect
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{ // debouncing as this can be set when device is powering
tusb_dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
}
}
@ -336,13 +336,13 @@ void hal_dcd_isr(uint8_t rhport)
// Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
{
tusb_dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
}
}
}
// else
// { // resume signal
// tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESUME);
// dcd_bus_event(0, USBD_BUS_EVENT_RESUME);
// }
// }
}
@ -351,7 +351,7 @@ void hal_dcd_isr(uint8_t rhport)
if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
{ // received control request from host
// copy setup request & acknowledge so that the next setup can be received by hw
tusb_dcd_setup_received(rhport, (uint8_t*)&dcd_data.setup_request);
dcd_setup_received(rhport, (uint8_t*)&dcd_data.setup_request);
// NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
@ -375,14 +375,14 @@ void hal_dcd_isr(uint8_t rhport)
//--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
void tusb_dcd_control_stall(uint8_t rhport)
void dcd_control_stall(uint8_t rhport)
{
(void) rhport;
// TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
}
bool tusb_dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
{
(void) rhport;
@ -430,7 +430,7 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
//--------------------------------------------------------------------+
// BULK/INTERRUPT/ISOCHRONOUS PIPE API
//--------------------------------------------------------------------+
void tusb_dcd_edpt_stall(edpt_hdl_t edpt_hdl)
void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
{
dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
}
@ -440,7 +440,7 @@ bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
}
void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
{
uint8_t ep_id = edpt_addr2phy(edpt_addr);
// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
@ -458,7 +458,7 @@ void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
}
}
edpt_hdl_t tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
{
(void) rhport;
edpt_hdl_t const null_handle = { 0 };
@ -491,7 +491,7 @@ edpt_hdl_t tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_end
};
}
bool tusb_dcd_edpt_busy(edpt_hdl_t edpt_hdl)
bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
{
return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
}
@ -537,9 +537,9 @@ static void queue_xfer_in_next_td(uint8_t ep_id)
dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
}
tusb_error_t tusb_dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
{
ASSERT( !tusb_dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
@ -548,9 +548,9 @@ tusb_error_t tusb_dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uin
return TUSB_ERROR_NONE;
}
tusb_error_t tusb_dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
tusb_error_t dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
{
if( tusb_dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
{ // save this transfer data to next td if pipe is busy or already been stalled
dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
dcd_data.next_td[edpt_hdl.index].total_bytes = total_bytes;

38
tinyusb/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
View File

@ -122,7 +122,7 @@ static void bus_reset(void)
memclr_(&dcd_data, sizeof(dcd_data_t));
}
bool tusb_dcd_init(uint8_t rhport)
bool dcd_init(uint8_t rhport)
{
(void) rhport;
@ -169,7 +169,7 @@ static void endpoint_non_control_isr(uint32_t eot_int)
};
bool succeeded = (p_last_dd->status == DD_STATUS_NORMAL || p_last_dd->status == DD_STATUS_DATA_UNDERUN) ? true : false;
tusb_dcd_xfer_complete(edpt_hdl, p_last_dd->present_count, succeeded); // report only xferred bytes in the IOC qtd
dcd_xfer_complete(edpt_hdl, p_last_dd->present_count, succeeded); // report only xferred bytes in the IOC qtd
}
}
}
@ -190,7 +190,7 @@ static void endpoint_control_isr(void)
tusb_control_request_t control_request;
pipe_control_read(&control_request, 8); // TODO read before clear setup above
tusb_dcd_setup_received(0, (uint8_t*) &control_request);
dcd_setup_received(0, (uint8_t*) &control_request);
}
else if (endpoint_int_status & 0x03)
{
@ -210,7 +210,7 @@ static void endpoint_control_isr(void)
dcd_data.control_dma.int_on_complete = 0;
// FIXME xferred_byte for control xfer is not needed now !!!
tusb_dcd_xfer_complete(edpt_hdl, 0, true);
dcd_xfer_complete(edpt_hdl, 0, true);
}
}
}
@ -232,23 +232,23 @@ void hal_dcd_isr(uint8_t rhport)
if (dev_status_reg & SIE_DEV_STATUS_RESET_MASK)
{
bus_reset();
tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESET);
dcd_bus_event(0, USBD_BUS_EVENT_RESET);
}
if (dev_status_reg & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)
{ // device is disconnected, require using VBUS (P1_30)
tusb_dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
}
if (dev_status_reg & SIE_DEV_STATUS_SUSPEND_CHANGE_MASK)
{
if (dev_status_reg & SIE_DEV_STATUS_SUSPEND_MASK)
{
tusb_dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
}
// else
// {
// tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESUME);
// dcd_bus_event(0, USBD_BUS_EVENT_RESUME);
// }
}
}
@ -282,19 +282,19 @@ void hal_dcd_isr(uint8_t rhport)
//--------------------------------------------------------------------+
// USBD API - CONTROLLER
//--------------------------------------------------------------------+
void tusb_dcd_connect(uint8_t rhport)
void dcd_connect(uint8_t rhport)
{
(void) rhport;
sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
}
void tusb_dcd_set_address(uint8_t rhport, uint8_t dev_addr)
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
(void) rhport;
sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
}
void tusb_dcd_set_config(uint8_t rhport, uint8_t config_num)
void dcd_set_config(uint8_t rhport, uint8_t config_num)
{
(void) rhport;
(void) config_num;
@ -375,12 +375,12 @@ static tusb_error_t pipe_control_read(void * buffer, uint16_t length)
//--------------------------------------------------------------------+
// CONTROL PIPE API
//--------------------------------------------------------------------+
void tusb_dcd_control_stall(uint8_t rhport)
void dcd_control_stall(uint8_t rhport)
{
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
}
bool tusb_dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
{
(void) rhport;
@ -414,7 +414,7 @@ bool tusb_dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, u
//--------------------------------------------------------------------+
// BULK/INTERRUPT/ISO PIPE API
//--------------------------------------------------------------------+
edpt_hdl_t tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
{
(void) rhport;
@ -450,17 +450,17 @@ edpt_hdl_t tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_end
};
}
bool tusb_dcd_edpt_busy(edpt_hdl_t edpt_hdl)
bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
{
return (dcd_data.udca[edpt_hdl.index] != NULL && !dcd_data.udca[edpt_hdl.index]->is_retired);
}
void tusb_dcd_edpt_stall(edpt_hdl_t edpt_hdl)
void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
{
sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+edpt_hdl.index, 1, SIE_SET_ENDPOINT_STALLED_MASK);
}
void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
uint8_t ep_id = ep_addr2phy(ep_addr);
@ -478,7 +478,7 @@ void dd_xfer_init(dcd_dma_descriptor_t* p_dd, void* buffer, uint16_t total_bytes
p_dd->present_count = 0;
}
tusb_error_t tusb_dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
{ // NOTE for sure the qhd has no dds
dcd_dma_descriptor_t* const p_fixed_dd = &dcd_data.dd[edpt_hdl.index][0]; // always queue with the fixed DD
@ -489,7 +489,7 @@ tusb_error_t tusb_dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uin
return TUSB_ERROR_NONE;
}
tusb_error_t tusb_dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
tusb_error_t dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
{
dcd_dma_descriptor_t* const p_first_dd = &dcd_data.dd[edpt_hdl.index][0];

36
tinyusb/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
View File

@ -85,17 +85,17 @@ static dcd_data_t* const dcd_data_ptr[2] = { &dcd_data0, &dcd_data1 };
//--------------------------------------------------------------------+
// CONTROLLER API
//--------------------------------------------------------------------+
void tusb_dcd_connect(uint8_t rhport)
void dcd_connect(uint8_t rhport)
{
LPC_USB[rhport]->USBCMD_D |= BIT_(0);
}
void tusb_dcd_set_address(uint8_t rhport, uint8_t dev_addr)
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
}
void tusb_dcd_set_config(uint8_t rhport, uint8_t config_num)
void dcd_set_config(uint8_t rhport, uint8_t config_num)
{
}
@ -146,7 +146,7 @@ static void bus_reset(uint8_t rhport)
}
bool tusb_dcd_init(uint8_t rhport)
bool dcd_init(uint8_t rhport)
{
LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
dcd_data_t* p_dcd = dcd_data_ptr[rhport];
@ -234,7 +234,7 @@ static inline uint8_t qtd_find_free(uint8_t rhport)
// control transfer does not need to use qtd find function
// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
bool tusb_dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length)
bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length)
{
LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
@ -269,7 +269,7 @@ static inline volatile uint32_t * get_reg_control_addr(uint8_t rhport, uint8_t p
return &(LPC_USB[rhport]->ENDPTCTRL0) + edpt_phy2log(physical_endpoint);
}
void tusb_dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
{
uint8_t ep_idx = edpt_addr2phy(ep_addr);
volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
@ -284,7 +284,7 @@ void tusb_dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
}
}
void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
volatile uint32_t * reg_control = get_reg_control_addr(rhport, edpt_addr2phy(ep_addr));
@ -293,7 +293,7 @@ void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
}
bool tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
// TODO not support ISO yet
@ -322,7 +322,7 @@ bool tusb_dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_
return true;
}
bool tusb_dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
{
uint8_t ep_idx = edpt_addr2phy(ep_addr);
dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
@ -332,7 +332,7 @@ bool tusb_dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
}
// add only, controller virtually cannot know
// TODO remove and merge to tusb_dcd_edpt_xfer
// TODO remove and merge to dcd_edpt_xfer
static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
{
uint8_t qtd_idx = qtd_find_free(rhport);
@ -361,7 +361,7 @@ static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_
return true;
}
bool tusb_dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
uint8_t ep_idx = edpt_addr2phy(ep_addr);
@ -403,7 +403,7 @@ void xfer_complete_isr(uint8_t rhport, uint32_t reg_complete)
bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
uint8_t ep_addr = edpt_phy2addr(ep_idx);
tusb_dcd_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
dcd_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
}
}
}
@ -423,7 +423,7 @@ void hal_dcd_isr(uint8_t rhport)
if (int_status & INT_MASK_RESET)
{
bus_reset(rhport);
tusb_dcd_bus_event(rhport, USBD_BUS_EVENT_RESET);
dcd_bus_event(rhport, USBD_BUS_EVENT_RESET);
}
if (int_status & INT_MASK_SUSPEND)
@ -432,7 +432,7 @@ void hal_dcd_isr(uint8_t rhport)
{ // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
{
tusb_dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
dcd_bus_event(0, USBD_BUS_EVENT_SUSPENDED);
}
}
}
@ -442,7 +442,7 @@ void hal_dcd_isr(uint8_t rhport)
// {
// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
// {
// tusb_dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
// dcd_bus_event(0, USBD_BUS_EVENT_UNPLUGGED);
// }
// }
@ -459,7 +459,7 @@ void hal_dcd_isr(uint8_t rhport)
// 23.10.10.2 Operational model for setup transfers
lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
tusb_dcd_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request);
dcd_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request);
}
//------------- Control Request Completed -------------//
else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
@ -476,7 +476,7 @@ void hal_dcd_isr(uint8_t rhport)
bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
(void) succeeded;
tusb_dcd_control_complete(rhport);
dcd_control_complete(rhport);
}
}
}
@ -491,7 +491,7 @@ void hal_dcd_isr(uint8_t rhport)
if (int_status & INT_MASK_SOF)
{
tusb_dcd_bus_event(rhport, USBD_BUS_EVENT_SOF);
dcd_bus_event(rhport, USBD_BUS_EVENT_SOF);
}
if (int_status & INT_MASK_NAK) {}