mirror of
https://github.com/hathach/tinyusb.git
synced 2025-04-16 05:42:56 +00:00
Merge pull request #2300 from hathach/add-u5a5
Add support for stm32u5a5 (highspeed with built-in femtoPHY)
This commit is contained in:
Ha Thach
GitHub
commit
4c01c5a714
1
.idea/cmake.xml
generated
1
.idea/cmake.xml
generated
@ -65,6 +65,7 @@
|
||||
</configuration>
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||||
<configuration PROFILE_NAME="stm32u575eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
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<configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=3" />
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<configuration PROFILE_NAME="stm32u5a5nucleo" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u5a5nucleo -DLOG=3 -DLOGGER=RTT" />
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</configurations>
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</component>
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</project>
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@ -26,13 +26,8 @@
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include "bsp/board_api.h"
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//--------------------------------------------------------------------+
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// MACRO CONSTANT TYPEDEF PROTOTYPES
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//--------------------------------------------------------------------+
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/* Blink pattern
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* - 250 ms : button is not pressed
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* - 1000 ms : button is pressed (and hold)
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@ -44,21 +39,18 @@ enum {
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#define HELLO_STR "Hello from TinyUSB\r\n"
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int main(void)
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{
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int main(void) {
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board_init();
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board_led_write(true);
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uint32_t start_ms = 0;
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bool led_state = false;
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while (1)
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{
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while (1) {
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uint32_t interval_ms = board_button_read() ? BLINK_PRESSED : BLINK_UNPRESSED;
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// Blink and print every interval ms
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if ( !(board_millis() - start_ms < interval_ms) )
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{
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if (!(board_millis() - start_ms < interval_ms)) {
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board_uart_write(HELLO_STR, strlen(HELLO_STR));
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start_ms = board_millis();
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@ -69,16 +61,14 @@ int main(void)
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// echo
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uint8_t ch;
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if ( board_uart_read(&ch, 1) > 0 )
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{
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if (board_uart_read(&ch, 1) > 0) {
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board_uart_write(&ch, 1);
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}
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}
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}
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#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
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void app_main(void)
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{
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void app_main(void) {
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main();
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}
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#endif
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@ -217,7 +217,7 @@ function(family_configure_common TARGET RTOS)
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if (NOT TARGET segger_rtt)
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add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
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target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
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target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
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#target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
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endif()
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target_link_libraries(${TARGET} PUBLIC segger_rtt)
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endif ()
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@ -199,7 +199,7 @@ void board_init(void) {
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__HAL_RCC_OTGPHYC_CLK_ENABLE();
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#else
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// MUC with external ULPI PHY
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// MCU with external ULPI PHY
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/* ULPI CLK */
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GPIO_InitStruct.Pin = GPIO_PIN_5;
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@ -55,9 +55,7 @@ extern "C"
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// RCC Clock
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//--------------------------------------------------------------------+
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static inline void board_clock_init(void)
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{
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static void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
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@ -94,7 +92,8 @@ static inline void board_clock_init(void)
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.ClockType =
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RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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@ -104,6 +103,8 @@ static inline void board_clock_init(void)
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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}
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static void SystemPower_Config(void) {
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}
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#ifdef __cplusplus
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}
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@ -54,9 +54,7 @@ extern "C"
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// RCC Clock
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//--------------------------------------------------------------------+
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static inline void board_clock_init(void)
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{
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static void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
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@ -93,7 +91,8 @@ static inline void board_clock_init(void)
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.ClockType =
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RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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@ -103,6 +102,8 @@ static inline void board_clock_init(void)
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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}
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static void SystemPower_Config(void) {
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}
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#ifdef __cplusplus
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}
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167
hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
Normal file
167
hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
Normal file
@ -0,0 +1,167 @@
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/*
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******************************************************************************
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**
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** File : LinkerScript.ld
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**
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** Author : STM32CubeIDE
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**
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** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series
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** 4096Kbytes FLASH
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** 2512Kbytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used.
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is without any warranty
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** of any kind.
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**
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*****************************************************************************
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** @attention
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**
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** Copyright (c) 2023 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K
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SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4096K
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
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{
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KEEP(*(.isr_vector)) /* Startup code */
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} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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} >FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >FLASH
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.ARM :
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{
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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} >FLASH
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >FLASH
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >FLASH
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >FLASH
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections into "RAM" Ram type memory */
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.data :
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||||
{
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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_edata = .; /* define a global symbol at data end */
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||||
} >RAM AT> FLASH
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/* Uninitialized data section into "RAM" Ram type memory */
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.bss :
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{
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||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
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__bss_start__ = _sbss;
|
||||
*(.bss)
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*(.bss*)
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||||
*(COMMON)
|
||||
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
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||||
|
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/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
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||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
11
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
Normal file
11
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
Normal file
@ -0,0 +1,11 @@
|
||||
set(MCU_VARIANT stm32u5a5xx)
|
||||
set(JLINK_DEVICE stm32u5a5zj)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
STM32U5A5xx
|
||||
HSE_VALUE=16000000UL
|
||||
)
|
||||
endfunction()
|
||||
144
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
Normal file
144
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
Normal file
@ -0,0 +1,144 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
// LED GREEN
|
||||
#define LED_PORT GPIOC
|
||||
#define LED_PIN GPIO_PIN_7
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
// BUTTON
|
||||
#define BUTTON_PORT GPIOC
|
||||
#define BUTTON_PIN GPIO_PIN_13
|
||||
#define BUTTON_STATE_ACTIVE 1
|
||||
|
||||
// UART Enable for STLink VCOM
|
||||
#define UART_DEV USART1
|
||||
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
|
||||
#define UART_GPIO_PORT GPIOA
|
||||
#define UART_GPIO_AF GPIO_AF7_USART1
|
||||
#define UART_TX_PIN GPIO_PIN_9
|
||||
#define UART_RX_PIN GPIO_PIN_10
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// RCC Clock
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
static void SystemClock_Config(void) {
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
|
||||
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
HAL_PWREx_EnableVddA();
|
||||
|
||||
/** Configure the main internal regulator output voltage
|
||||
*/
|
||||
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1;
|
||||
RCC_OscInitStruct.PLL.PLLN = 20;
|
||||
RCC_OscInitStruct.PLL.PLLP = 8;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2;
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
||||
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
|
||||
| RCC_CLOCKTYPE_PCLK3;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
|
||||
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
|
||||
|
||||
// USB Clock
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
RCC_PeriphCLKInitTypeDef usb_clk_init = { 0};
|
||||
usb_clk_init.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
|
||||
usb_clk_init.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&usb_clk_init) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Set the OTG PHY reference clock selection
|
||||
*/
|
||||
HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
|
||||
|
||||
// USART clock
|
||||
RCC_PeriphCLKInitTypeDef uart_clk_init = { 0};
|
||||
uart_clk_init.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||||
uart_clk_init.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&uart_clk_init) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
static void SystemPower_Config(void) {
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
|
||||
/*
|
||||
* Switch to SMPS regulator instead of LDO
|
||||
*/
|
||||
if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN PWR */
|
||||
/* USER CODE END PWR */
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_H_ */
|
||||
11
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
Normal file
11
hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
Normal file
@ -0,0 +1,11 @@
|
||||
CFLAGS += \
|
||||
-DSTM32U5A5xx \
|
||||
-DHSE_VALUE=16000000UL \
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
|
||||
|
||||
SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = stm32u575zi
|
||||
352
hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
Normal file
352
hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
Normal file
@ -0,0 +1,352 @@
|
||||
#MicroXplorer Configuration settings - do not modify
|
||||
ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2
|
||||
ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,MonitoredBy-1\#ChannelRegularConversion,NbrOfConversionFlag
|
||||
ADC1.MonitoredBy-1\#ChannelRegularConversion=__NULL
|
||||
ADC1.NbrOfConversionFlag=1
|
||||
ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE
|
||||
ADC1.Rank-1\#ChannelRegularConversion=1
|
||||
ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_5CYCLE
|
||||
ADC1.master=1
|
||||
CAD.formats=
|
||||
CAD.pinconfig=
|
||||
CAD.provider=
|
||||
CORTEX_M33_NS.userName=CORTEX_M33
|
||||
File.Version=6
|
||||
GPDMA1.DIRECTION_GPDMACH0=DMA_MEMORY_TO_PERIPH
|
||||
GPDMA1.DIRECTION_GPDMACH3=DMA_MEMORY_TO_PERIPH
|
||||
GPDMA1.IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0=__NULL
|
||||
GPDMA1.IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3=__NULL
|
||||
GPDMA1.IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5=__NULL
|
||||
GPDMA1.IPParameters=IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5,REQUEST_GPDMACH5,IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3,REQUEST_GPDMACH3,DIRECTION_GPDMACH3,IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0,REQUEST_GPDMACH0,DIRECTION_GPDMACH0,SRCINC_GPDMACH0
|
||||
GPDMA1.REQUEST_GPDMACH0=GPDMA1_REQUEST_USART1_TX
|
||||
GPDMA1.REQUEST_GPDMACH3=GPDMA1_REQUEST_UCPD1_TX
|
||||
GPDMA1.REQUEST_GPDMACH5=GPDMA1_REQUEST_UCPD1_RX
|
||||
GPDMA1.SRCINC_GPDMACH0=DMA_SINC_INCREMENTED
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
KeepUserPlacement=false
|
||||
MMTAppReg1.MEMORYMAP.AP=RW_priv_only
|
||||
MMTAppReg1.MEMORYMAP.AppRegionName=RAM
|
||||
MMTAppReg1.MEMORYMAP.ContextName=CortexM33
|
||||
MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33
|
||||
MMTAppReg1.MEMORYMAP.DefaultDataRegion=true
|
||||
MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP
|
||||
MMTAppReg1.MEMORYMAP.Name=RAM
|
||||
MMTAppReg1.MEMORYMAP.Size=2555904
|
||||
MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
|
||||
MMTAppReg2.MEMORYMAP.AppRegionName=RAM Reserved Alias Region
|
||||
MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33
|
||||
MMTAppReg2.MEMORYMAP.DefaultDataRegion=false
|
||||
MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ReservedRegion,Name
|
||||
MMTAppReg2.MEMORYMAP.Name=RAM Reserved Alias Region
|
||||
MMTAppReg2.MEMORYMAP.ReservedRegion=true
|
||||
MMTAppReg2.MEMORYMAP.Size=2555904
|
||||
MMTAppReg2.MEMORYMAP.StartAddress=0x0A000000
|
||||
MMTAppReg3.MEMORYMAP.AP=RO_priv_only
|
||||
MMTAppReg3.MEMORYMAP.AppRegionName=FLASH
|
||||
MMTAppReg3.MEMORYMAP.Cacheability=WTRA
|
||||
MMTAppReg3.MEMORYMAP.ContextName=CortexM33
|
||||
MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33
|
||||
MMTAppReg3.MEMORYMAP.DefaultCodeRegion=true
|
||||
MMTAppReg3.MEMORYMAP.DefaultDataRegion=false
|
||||
MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
|
||||
MMTAppReg3.MEMORYMAP.MemType=ROM
|
||||
MMTAppReg3.MEMORYMAP.Name=FLASH
|
||||
MMTAppReg3.MEMORYMAP.Size=4194304
|
||||
MMTAppReg3.MEMORYMAP.StartAddress=0x08000000
|
||||
MMTAppRegionsCount=3
|
||||
MMTConfigApplied=false
|
||||
Mcu.CPN=STM32U5A5ZJT6Q
|
||||
Mcu.ContextProject=TrustZoneDisabled
|
||||
Mcu.Family=STM32U5
|
||||
Mcu.IP0=ADC1
|
||||
Mcu.IP1=CORTEX_M33_NS
|
||||
Mcu.IP10=UCPD1
|
||||
Mcu.IP11=USART1
|
||||
Mcu.IP12=USBPD
|
||||
Mcu.IP13=USBX
|
||||
Mcu.IP14=USB_OTG_HS
|
||||
Mcu.IP2=GPDMA1
|
||||
Mcu.IP3=ICACHE
|
||||
Mcu.IP4=MEMORYMAP
|
||||
Mcu.IP5=NVIC
|
||||
Mcu.IP6=PWR
|
||||
Mcu.IP7=RCC
|
||||
Mcu.IP8=SYS
|
||||
Mcu.IP9=THREADX
|
||||
Mcu.IPNb=15
|
||||
Mcu.Name=STM32U5A5ZJTxQ
|
||||
Mcu.Package=LQFP144
|
||||
Mcu.Pin0=PH0-OSC_IN (PH0)
|
||||
Mcu.Pin1=PH1-OSC_OUT (PH1)
|
||||
Mcu.Pin10=VP_GPDMA1_VS_GPDMACH0
|
||||
Mcu.Pin11=VP_GPDMA1_VS_GPDMACH3
|
||||
Mcu.Pin12=VP_GPDMA1_VS_GPDMACH5
|
||||
Mcu.Pin13=VP_ICACHE_VS_ICACHE
|
||||
Mcu.Pin14=VP_PWR_VS_DBSignals
|
||||
Mcu.Pin15=VP_PWR_VS_SECSignals
|
||||
Mcu.Pin16=VP_PWR_VS_LPOM
|
||||
Mcu.Pin17=VP_SYS_VS_tim6
|
||||
Mcu.Pin18=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault
|
||||
Mcu.Pin19=VP_USBPD_VS_USBPD1
|
||||
Mcu.Pin2=PC1
|
||||
Mcu.Pin20=VP_USBPD_VS_PD3TYPEC
|
||||
Mcu.Pin21=VP_USBPD_VS_usbpd_tim2
|
||||
Mcu.Pin22=VP_USBPD_VS_usbpd_usb_cohabitation
|
||||
Mcu.Pin23=VP_USBX_Core_System
|
||||
Mcu.Pin24=VP_USBX_UX Device CoreStack_HS
|
||||
Mcu.Pin25=VP_USBX_UX Device Controller_HS
|
||||
Mcu.Pin26=VP_USBX_UX Device CDC ACM Class_HS
|
||||
Mcu.Pin27=VP_MEMORYMAP_VS_MEMORYMAP
|
||||
Mcu.Pin3=PB15
|
||||
Mcu.Pin4=PG2
|
||||
Mcu.Pin5=PA9
|
||||
Mcu.Pin6=PA10
|
||||
Mcu.Pin7=PA11
|
||||
Mcu.Pin8=PA12
|
||||
Mcu.Pin9=PA15 (JTDI)
|
||||
Mcu.PinsNb=28
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32U5A5ZJTxQ
|
||||
MxCube.Version=6.9.2
|
||||
MxDb.Version=DB.6.0.92
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
NVIC.GPDMA1_Channel0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.GPDMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.GPDMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.OTG_HS_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true\:true
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
|
||||
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
|
||||
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
|
||||
NVIC.SavedPendsvIrqHandlerGenerated=true
|
||||
NVIC.SavedSvcallIrqHandlerGenerated=true
|
||||
NVIC.SavedSystickIrqHandlerGenerated=true
|
||||
NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:false\:false\:false\:true\:false
|
||||
NVIC.TIM6_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.TimeBase=TIM6_IRQn
|
||||
NVIC.TimeBaseIP=TIM6
|
||||
NVIC.UCPD1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:false\:true
|
||||
NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd
|
||||
PA10.GPIO_PuPd=GPIO_PULLUP
|
||||
PA10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
|
||||
PA10.Mode=Asynchronous
|
||||
PA10.Signal=USART1_RX
|
||||
PA11.GPIOParameters=GPIO_Speed
|
||||
PA11.GPIO_Speed=GPIO_SPEED_FREQ_LOW
|
||||
PA11.Mode=Internal_Phy_Device
|
||||
PA11.Signal=USB_OTG_HS_DM
|
||||
PA12.GPIOParameters=GPIO_Speed
|
||||
PA12.GPIO_Speed=GPIO_SPEED_FREQ_LOW
|
||||
PA12.Mode=Internal_Phy_Device
|
||||
PA12.Signal=USB_OTG_HS_DP
|
||||
PA15\ (JTDI).Mode=Sink_AllSignals
|
||||
PA15\ (JTDI).Signal=UCPD1_CC1
|
||||
PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd
|
||||
PA9.GPIO_PuPd=GPIO_PULLUP
|
||||
PA9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
|
||||
PA9.Mode=Asynchronous
|
||||
PA9.Signal=USART1_TX
|
||||
PB15.Mode=Sink_AllSignals
|
||||
PB15.Signal=UCPD1_CC2
|
||||
PC1.Mode=IN2-Single-Ended
|
||||
PC1.Signal=ADC1_IN2
|
||||
PG2.GPIOParameters=GPIO_Label
|
||||
PG2.GPIO_Label=LED_RED
|
||||
PG2.Locked=true
|
||||
PG2.Signal=GPIO_Output
|
||||
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
|
||||
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
|
||||
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
|
||||
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
|
||||
PWR.IPParameters=PowerMode
|
||||
PWR.PowerMode=PWR_SMPS_SUPPLY
|
||||
PinOutPanel.RotationAngle=0
|
||||
ProjectManager.AskForMigrate=true
|
||||
ProjectManager.BackupPrevious=false
|
||||
ProjectManager.CompilerOptimize=6
|
||||
ProjectManager.ComputerToolchain=false
|
||||
ProjectManager.CoupleFile=false
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32U5A5ZJTxQ
|
||||
ProjectManager.Example=Ux_Device_CDC_ACM
|
||||
ProjectManager.ExampleSource=MxCubeFw
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.3.0
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x200
|
||||
ProjectManager.KeepUserCode=true
|
||||
ProjectManager.LPBAM.generateCode=
|
||||
ProjectManager.LastFirmware=true
|
||||
ProjectManager.LibraryCopy=1
|
||||
ProjectManager.MainLocation=Core/Src
|
||||
ProjectManager.NoMain=false
|
||||
ProjectManager.PreviousToolchain=
|
||||
ProjectManager.ProjectBuild=false
|
||||
ProjectManager.ProjectFileName=stm32u5a5nucleo.ioc
|
||||
ProjectManager.ProjectName=stm32u5a5nucleo
|
||||
ProjectManager.ProjectStructure=
|
||||
ProjectManager.RegisterCallBack=
|
||||
ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=STM32CubeIDE
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UAScriptAfterPath=
|
||||
ProjectManager.UAScriptBeforePath=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_ICACHE_Init-ICACHE-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-false,6-MX_UCPD1_Init-UCPD1-false-LL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-true-HAL-false,8-MX_USBPD_Init-USBPD-false-HAL-false,9-MX_USBX_Init-USBX-false-HAL-false,10-MX_ADC1_Init-ADC1-false-HAL-true,11-MX_MEMORYMAP_Init-MEMORYMAP-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
|
||||
RCC.ADCFreq_Value=16000000
|
||||
RCC.ADF1Freq_Value=160000000
|
||||
RCC.AHBFreq_Value=160000000
|
||||
RCC.APB1Freq_Value=160000000
|
||||
RCC.APB1TimFreq_Value=160000000
|
||||
RCC.APB2Freq_Value=160000000
|
||||
RCC.APB2TimFreq_Value=160000000
|
||||
RCC.APB3Freq_Value=160000000
|
||||
RCC.CK48Freq_Value=48000000
|
||||
RCC.CRSFreq_Value=48000000
|
||||
RCC.CortexFreq_Value=160000000
|
||||
RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI
|
||||
RCC.DACFreq_Value=32000
|
||||
RCC.EPOD_VALUE=16000000
|
||||
RCC.FCLKCortexFreq_Value=160000000
|
||||
RCC.FDCANFreq_Value=160000000
|
||||
RCC.FamilyName=M
|
||||
RCC.HCLKFreq_Value=160000000
|
||||
RCC.HSE_VALUE=16000000
|
||||
RCC.HSI48_VALUE=48000000
|
||||
RCC.HSI_VALUE=16000000
|
||||
RCC.I2C1Freq_Value=160000000
|
||||
RCC.I2C2Freq_Value=160000000
|
||||
RCC.I2C3Freq_Value=160000000
|
||||
RCC.I2C4Freq_Value=160000000
|
||||
RCC.I2C5Freq_Value=160000000
|
||||
RCC.I2C6Freq_Value=160000000
|
||||
RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2C5Freq_Value,I2C6Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSIClockRange,MSI_VALUE,OCTOSPIMFreq_Value,PLL1P,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBPHYCLockSelection,USBPHYFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value
|
||||
RCC.LPTIM2Freq_Value=160000000
|
||||
RCC.LPUART1Freq_Value=160000000
|
||||
RCC.LSCOPinFreq_Value=32000
|
||||
RCC.LSE_VALUE=32768
|
||||
RCC.LSIDIV_VALUE=32000
|
||||
RCC.LSI_VALUE=32000
|
||||
RCC.MCO1PinFreq_Value=160000000
|
||||
RCC.MDF1Freq_Value=160000000
|
||||
RCC.MSIClockRange=RCC_MSIRANGE_0
|
||||
RCC.MSI_VALUE=48000000
|
||||
RCC.OCTOSPIMFreq_Value=160000000
|
||||
RCC.PLL1P=8
|
||||
RCC.PLL2FRACN=0
|
||||
RCC.PLL2PoutputFreq_Value=3096000000
|
||||
RCC.PLL2QoutputFreq_Value=3096000000
|
||||
RCC.PLL2RoutputFreq_Value=3096000000
|
||||
RCC.PLL3FRACN=0
|
||||
RCC.PLL3PoutputFreq_Value=3096000000
|
||||
RCC.PLL3QoutputFreq_Value=3096000000
|
||||
RCC.PLL3RoutputFreq_Value=3096000000
|
||||
RCC.PLLFRACN=0
|
||||
RCC.PLLN=20
|
||||
RCC.PLLPoutputFreq_Value=40000000
|
||||
RCC.PLLQoutputFreq_Value=160000000
|
||||
RCC.PLLRCLKFreq_Value=160000000
|
||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
||||
RCC.RNGFreq_Value=48000000
|
||||
RCC.SAESFreq_Value=48000000
|
||||
RCC.SAI1Freq_Value=3096000000
|
||||
RCC.SAI2Freq_Value=3096000000
|
||||
RCC.SDMMCFreq_Value=40000000
|
||||
RCC.SPI1Freq_Value=160000000
|
||||
RCC.SPI2Freq_Value=160000000
|
||||
RCC.SPI3Freq_Value=160000000
|
||||
RCC.SYSCLKFreq_VALUE=160000000
|
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||
RCC.UART4Freq_Value=160000000
|
||||
RCC.UART5Freq_Value=160000000
|
||||
RCC.USART1Freq_Value=160000000
|
||||
RCC.USART2Freq_Value=160000000
|
||||
RCC.USART3Freq_Value=160000000
|
||||
RCC.USART6Freq_Value=160000000
|
||||
RCC.USBPHYCLockSelection=RCC_USBPHYCLKSOURCE_HSE
|
||||
RCC.USBPHYFreq_Value=16000000
|
||||
RCC.VCOInput2Freq_Value=48000000
|
||||
RCC.VCOInput3Freq_Value=48000000
|
||||
RCC.VCOInputFreq_Value=16000000
|
||||
RCC.VCOOutputFreq_Value=320000000
|
||||
RCC.VCOPLL2OutputFreq_Value=6192000000
|
||||
RCC.VCOPLL3OutputFreq_Value=6192000000
|
||||
USART1.IPParameters=VirtualMode-Asynchronous
|
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC
|
||||
USBX.BSP.number=1
|
||||
USBX.Core_System=1
|
||||
USBX.IPParameters=Core_System,UX_Device_CoreStack,UX_Device_Controller,UX_DEVICE_CDC_ACM,USBD_CDCACM_EPIN_ADDR,USBD_CDCACM_EPOUT_HS_MPS,USBD_CDCACM_EPIN_HS_MPS,UX_DEVICE_APP_MEM_POOL_SIZE,USBD_PRODUCT_STRING,UX_SLAVE_REQUEST_DATA_MAX_LENGTH,USBX_DEVICE_SYS_SIZE,USBD_PID,USBD_SERIAL_NUMBER,UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH,USBD_CDCACM_EPINCMD_ADDR,MAX_POWER_IN_MILLI_AMPER
|
||||
USBX.MAX_POWER_IN_MILLI_AMPER=0
|
||||
USBX.USBD_CDCACM_EPINCMD_ADDR=2
|
||||
USBX.USBD_CDCACM_EPIN_ADDR=1
|
||||
USBX.USBD_CDCACM_EPIN_HS_MPS=512
|
||||
USBX.USBD_CDCACM_EPOUT_HS_MPS=512
|
||||
USBX.USBD_PID=22336
|
||||
USBX.USBD_PRODUCT_STRING=STM32 Virtual ComPort
|
||||
USBX.USBD_SERIAL_NUMBER=CDC_ACM001
|
||||
USBX.USBX_DEVICE_SYS_SIZE=4*1024
|
||||
USBX.UX_DEVICE_APP_MEM_POOL_SIZE=8192
|
||||
USBX.UX_DEVICE_CDC_ACM=1
|
||||
USBX.UX_Device_Controller=1
|
||||
USBX.UX_Device_CoreStack=1
|
||||
USBX.UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH=256
|
||||
USBX.UX_SLAVE_REQUEST_DATA_MAX_LENGTH=512
|
||||
USBX0.BSP.STBoard=false
|
||||
USBX0.BSP.api=Unknown
|
||||
USBX0.BSP.component=
|
||||
USBX0.BSP.condition=
|
||||
USBX0.BSP.instance=USB_OTG_HS
|
||||
USBX0.BSP.ip=USB_OTG_HS
|
||||
USBX0.BSP.mode=Device_Only
|
||||
USBX0.BSP.name=USBDevice
|
||||
USBX0.BSP.semaphore=
|
||||
USBX0.BSP.solution=USB_OTG_HS
|
||||
USB_OTG_HS.IPParameters=VirtualMode
|
||||
USB_OTG_HS.VirtualMode=Device_HS
|
||||
VP_GPDMA1_VS_GPDMACH0.Mode=SIMPLEREQUEST_GPDMACH0
|
||||
VP_GPDMA1_VS_GPDMACH0.Signal=GPDMA1_VS_GPDMACH0
|
||||
VP_GPDMA1_VS_GPDMACH3.Mode=SIMPLEREQUEST_GPDMACH3
|
||||
VP_GPDMA1_VS_GPDMACH3.Signal=GPDMA1_VS_GPDMACH3
|
||||
VP_GPDMA1_VS_GPDMACH5.Mode=SIMPLEREQUEST_GPDMACH5
|
||||
VP_GPDMA1_VS_GPDMACH5.Signal=GPDMA1_VS_GPDMACH5
|
||||
VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
|
||||
VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
|
||||
VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
|
||||
VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
|
||||
VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
|
||||
VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
|
||||
VP_PWR_VS_LPOM.Mode=PowerOptimisation
|
||||
VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM
|
||||
VP_PWR_VS_SECSignals.Mode=Security/Privilege
|
||||
VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
|
||||
VP_SYS_VS_tim6.Mode=TIM6
|
||||
VP_SYS_VS_tim6.Signal=SYS_VS_tim6
|
||||
VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default
|
||||
VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault
|
||||
VP_USBPD_VS_PD3TYPEC.Mode=PD3_TypeC
|
||||
VP_USBPD_VS_PD3TYPEC.Signal=USBPD_VS_PD3TYPEC
|
||||
VP_USBPD_VS_USBPD1.Mode=USBPD_P0
|
||||
VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1
|
||||
VP_USBPD_VS_usbpd_tim2.Mode=TIM2
|
||||
VP_USBPD_VS_usbpd_tim2.Signal=USBPD_VS_usbpd_tim2
|
||||
VP_USBPD_VS_usbpd_usb_cohabitation.Mode=Enable USB Support
|
||||
VP_USBPD_VS_usbpd_usb_cohabitation.Signal=USBPD_VS_usbpd_usb_cohabitation
|
||||
VP_USBX_Core_System.Mode=Core_System
|
||||
VP_USBX_Core_System.Signal=USBX_Core_System
|
||||
VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Mode=UX_Device_class_CDC_ACM_HS
|
||||
VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Signal=USBX_UX Device CDC ACM Class_HS
|
||||
VP_USBX_UX\ Device\ Controller_HS.Mode=UX_Device_Controller_HS
|
||||
VP_USBX_UX\ Device\ Controller_HS.Signal=USBX_UX Device Controller_HS
|
||||
VP_USBX_UX\ Device\ CoreStack_HS.Mode=UX_Device_CoreStack_HS
|
||||
VP_USBX_UX\ Device\ CoreStack_HS.Signal=USBX_UX Device CoreStack_HS
|
||||
board=NUCLEO-U5A5ZJ-Q
|
||||
boardIOC=true
|
||||
@ -38,6 +38,10 @@
|
||||
#endif
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
|
||||
TU_ATTR_UNUSED static void Error_Handler(void) {
|
||||
}
|
||||
|
||||
#include "board.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
@ -47,6 +51,10 @@ void OTG_FS_IRQHandler(void) {
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
void OTG_HS_IRQHandler(void) {
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
@ -54,8 +62,9 @@ void OTG_FS_IRQHandler(void) {
|
||||
UART_HandleTypeDef UartHandle;
|
||||
|
||||
void board_init(void) {
|
||||
|
||||
board_clock_init();
|
||||
// Init clock, implemented in board.h
|
||||
SystemClock_Config();
|
||||
SystemPower_Config();
|
||||
|
||||
// Enable All GPIOs clocks
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
@ -75,9 +84,6 @@ void board_init(void) {
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
@ -101,7 +107,7 @@ void board_init(void) {
|
||||
GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
||||
GPIO_InitStruct.Alternate = UART_GPIO_AF;
|
||||
HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
|
||||
|
||||
@ -116,10 +122,9 @@ void board_init(void) {
|
||||
UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
|
||||
HAL_UART_Init(&UartHandle);
|
||||
|
||||
/* Configure USB FS GPIOs */
|
||||
/* Configure USB GPIOs */
|
||||
/* Configure DM DP Pins */
|
||||
GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
@ -135,6 +140,12 @@ void board_init(void) {
|
||||
GPIO_InitStruct.Alternate = GPIO_AF10_USB;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
#ifdef USB_OTG_FS
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE
|
||||
// Configure VBUS Pin OTG_FS_VBUS_SENSE
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_9;
|
||||
@ -156,8 +167,35 @@ void board_init(void) {
|
||||
/* Enable USB power on Pwrctrl CR2 register */
|
||||
HAL_PWREx_EnableVddUSB();
|
||||
|
||||
/* USB_OTG_FS clock enable */
|
||||
/* USB clock enable */
|
||||
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
||||
|
||||
#else
|
||||
// STM59x/Ax/Fx/Gx only have 1 USB HS port
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* USB clock enable */
|
||||
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
|
||||
__HAL_RCC_USBPHYC_CLK_ENABLE();
|
||||
|
||||
/* Enable USB power on Pwrctrl CR2 register */
|
||||
HAL_PWREx_EnableVddUSB();
|
||||
HAL_PWREx_EnableUSBHSTranceiverSupply();
|
||||
|
||||
/*Configuring the SYSCFG registers OTG_HS PHY*/
|
||||
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
|
||||
|
||||
// Disable VBUS sense (B device)
|
||||
USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
||||
|
||||
// B-peripheral session valid override enable
|
||||
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
|
||||
USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
|
||||
#endif // USB_OTG_FS
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
@ -217,9 +217,7 @@
|
||||
|
||||
// TypeC controller
|
||||
#define TUP_USBIP_TYPEC_STM32
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#define TUP_TYPEC_RHPORTS_NUM 1
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
|
||||
@ -261,14 +259,21 @@
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
|
||||
#if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
|
||||
defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
|
||||
#define TUP_DCD_ENDPOINT_MAX 9
|
||||
#define TUP_RHPORT_HIGHSPEED 1
|
||||
#else
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
|
||||
#define TUP_USBIP_FSDEV
|
||||
#define TUP_USBIP_FSDEV_STM32
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Sony
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
@ -103,20 +103,17 @@ static bool _out_ep_closed; // Flag to check if RX FIFO si
|
||||
static bool _sof_en;
|
||||
|
||||
// Calculate the RX FIFO size according to recommendations from reference manual
|
||||
static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count)
|
||||
{
|
||||
static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
|
||||
return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
|
||||
}
|
||||
|
||||
static void update_grxfsiz(uint8_t rhport)
|
||||
{
|
||||
static void update_grxfsiz(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
|
||||
|
||||
// Determine largest EP size for RX FIFO
|
||||
uint16_t max_epsize = 0;
|
||||
for (uint8_t epnum = 0; epnum < ep_count; epnum++)
|
||||
{
|
||||
for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
|
||||
max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
|
||||
}
|
||||
|
||||
@ -125,8 +122,7 @@ static void update_grxfsiz(uint8_t rhport)
|
||||
}
|
||||
|
||||
// Start of Bus Reset
|
||||
static void bus_reset(uint8_t rhport)
|
||||
{
|
||||
static void bus_reset(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
|
||||
|
||||
@ -139,8 +135,7 @@ static void bus_reset(uint8_t rhport)
|
||||
dwc2->dcfg &= ~DCFG_DAD_Msk;
|
||||
|
||||
// 1. NAK for all OUT endpoints
|
||||
for ( uint8_t n = 0; n < ep_count; n++ )
|
||||
{
|
||||
for (uint8_t n = 0; n < ep_count; n++) {
|
||||
dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
|
||||
}
|
||||
|
||||
@ -218,24 +213,22 @@ static void bus_reset(uint8_t rhport)
|
||||
dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
|
||||
}
|
||||
|
||||
static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
|
||||
{
|
||||
static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets,
|
||||
uint16_t total_bytes) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
// EP0 is limited to one packet each xfer
|
||||
// We use multiple transaction of xfer->max_size length to get a whole transfer done
|
||||
if ( epnum == 0 )
|
||||
{
|
||||
if (epnum == 0) {
|
||||
xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
|
||||
total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
|
||||
ep0_pending[dir] -= total_bytes;
|
||||
}
|
||||
|
||||
// IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
|
||||
if ( dir == TUSB_DIR_IN )
|
||||
{
|
||||
if (dir == TUSB_DIR_IN) {
|
||||
dwc2_epin_t* epin = dwc2->epin;
|
||||
|
||||
// A full IN transfer (multiple packets, possibly) triggers XFRC.
|
||||
@ -245,20 +238,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
|
||||
epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
|
||||
|
||||
// For ISO endpoint set correct odd/even bit for next frame.
|
||||
if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
|
||||
{
|
||||
if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
|
||||
// Take odd/even bit from frame counter.
|
||||
uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
|
||||
epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
|
||||
}
|
||||
// Enable fifo empty interrupt only if there are something to put in the fifo.
|
||||
if ( total_bytes != 0 )
|
||||
{
|
||||
if (total_bytes != 0) {
|
||||
dwc2->diepempmsk |= (1 << epnum);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dwc2_epout_t* epout = dwc2->epout;
|
||||
|
||||
// A full OUT transfer (multiple packets, possibly) triggers XFRC.
|
||||
@ -268,8 +257,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
|
||||
|
||||
epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
|
||||
if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
|
||||
XFER_CTL_BASE(epnum, dir)->interval == 1 )
|
||||
{
|
||||
XFER_CTL_BASE(epnum, dir)->interval == 1) {
|
||||
// Take odd/even bit from frame counter.
|
||||
uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
|
||||
epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
|
||||
@ -281,78 +269,21 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
|
||||
/* Controller API
|
||||
*------------------------------------------------------------------*/
|
||||
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
|
||||
void print_dwc2_info(dwc2_regs_t * dwc2)
|
||||
{
|
||||
dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
|
||||
dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
|
||||
dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
|
||||
|
||||
// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
|
||||
// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
|
||||
// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);
|
||||
|
||||
// HW configure 2
|
||||
TU_LOG(DWC2_DEBUG, "\r\n");
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2);
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb );
|
||||
|
||||
// HW configure 3
|
||||
TU_LOG(DWC2_DEBUG, "\r\n");
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3);
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size );
|
||||
|
||||
// HW configure 4
|
||||
TU_LOG(DWC2_DEBUG, "\r\n");
|
||||
TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4);
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable );
|
||||
TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic );
|
||||
void print_dwc2_info(dwc2_regs_t* dwc2) {
|
||||
// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
|
||||
// use dwc2_info.py/md for bit-field value and comparison with other ports
|
||||
volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
|
||||
TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
|
||||
for (size_t i = 0; i < 5; i++) {
|
||||
TU_LOG(DWC2_DEBUG, "0x%08lX, ", p[i]);
|
||||
}
|
||||
TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void reset_core(dwc2_regs_t * dwc2)
|
||||
{
|
||||
static void reset_core(dwc2_regs_t* dwc2) {
|
||||
// reset core
|
||||
dwc2->grstctl |= GRSTCTL_CSRST;
|
||||
|
||||
@ -366,8 +297,7 @@ static void reset_core(dwc2_regs_t * dwc2)
|
||||
// wait for device mode ?
|
||||
}
|
||||
|
||||
static bool phy_hs_supported(dwc2_regs_t * dwc2)
|
||||
{
|
||||
static bool phy_hs_supported(dwc2_regs_t* dwc2) {
|
||||
// note: esp32 incorrect report its hs_phy_type as utmi
|
||||
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
|
||||
return false;
|
||||
@ -376,8 +306,7 @@ static bool phy_hs_supported(dwc2_regs_t * dwc2)
|
||||
#endif
|
||||
}
|
||||
|
||||
static void phy_fs_init(dwc2_regs_t * dwc2)
|
||||
{
|
||||
static void phy_fs_init(dwc2_regs_t* dwc2) {
|
||||
TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
|
||||
|
||||
// Select FS PHY
|
||||
@ -401,15 +330,13 @@ static void phy_fs_init(dwc2_regs_t * dwc2)
|
||||
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
|
||||
}
|
||||
|
||||
static void phy_hs_init(dwc2_regs_t * dwc2)
|
||||
{
|
||||
static void phy_hs_init(dwc2_regs_t* dwc2) {
|
||||
uint32_t gusbcfg = dwc2->gusbcfg;
|
||||
|
||||
// De-select FS PHY
|
||||
gusbcfg &= ~GUSBCFG_PHYSEL;
|
||||
|
||||
if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
|
||||
{
|
||||
if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
|
||||
TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
|
||||
|
||||
// Select ULPI
|
||||
@ -423,8 +350,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
|
||||
|
||||
// Disable FS/LS ULPI
|
||||
gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
|
||||
}else
|
||||
{
|
||||
} else {
|
||||
TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
|
||||
|
||||
// Select UTMI+ with 8-bit interface
|
||||
@ -465,8 +391,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
|
||||
dwc2->dcfg = dcfg;
|
||||
}
|
||||
|
||||
static bool check_dwc2(dwc2_regs_t * dwc2)
|
||||
{
|
||||
static bool check_dwc2(dwc2_regs_t* dwc2) {
|
||||
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
|
||||
print_dwc2_info(dwc2);
|
||||
#endif
|
||||
@ -481,28 +406,22 @@ static bool check_dwc2(dwc2_regs_t * dwc2)
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_init (uint8_t rhport)
|
||||
{
|
||||
void dcd_init(uint8_t rhport) {
|
||||
// Programming model begins in the last section of the chapter on the USB
|
||||
// peripheral in each Reference Manual.
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
// Check Synopsys ID register, failed if controller clock/power is not enabled
|
||||
TU_VERIFY(check_dwc2(dwc2), );
|
||||
|
||||
if (!check_dwc2(dwc2)) return;
|
||||
dcd_disconnect(rhport);
|
||||
|
||||
// max number of endpoints & total_fifo_size are:
|
||||
// hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
|
||||
|
||||
if( phy_hs_supported(dwc2) )
|
||||
{
|
||||
// Highspeed
|
||||
phy_hs_init(dwc2);
|
||||
}else
|
||||
{
|
||||
// core does not support highspeed or hs-phy is not present
|
||||
phy_fs_init(dwc2);
|
||||
if (phy_hs_supported(dwc2)) {
|
||||
phy_hs_init(dwc2); // Highspeed
|
||||
} else {
|
||||
phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
|
||||
}
|
||||
|
||||
// Restart PHY clock
|
||||
@ -528,6 +447,14 @@ void dcd_init (uint8_t rhport)
|
||||
// (non zero-length packet), send STALL back and discard.
|
||||
dwc2->dcfg |= DCFG_NZLSOHSK;
|
||||
|
||||
// flush all TX fifo and wait for it cleared
|
||||
dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
|
||||
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
|
||||
|
||||
// flush RX fifo and wait for it cleared
|
||||
dwc2->grstctl = GRSTCTL_RXFFLSH;
|
||||
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
|
||||
|
||||
// Clear all interrupts
|
||||
uint32_t int_mask = dwc2->gintsts;
|
||||
dwc2->gintsts |= int_mask;
|
||||
@ -554,18 +481,15 @@ void dcd_init (uint8_t rhport)
|
||||
dcd_connect(rhport);
|
||||
}
|
||||
|
||||
void dcd_int_enable (uint8_t rhport)
|
||||
{
|
||||
void dcd_int_enable(uint8_t rhport) {
|
||||
dwc2_dcd_int_enable(rhport);
|
||||
}
|
||||
|
||||
void dcd_int_disable (uint8_t rhport)
|
||||
{
|
||||
void dcd_int_disable(uint8_t rhport) {
|
||||
dwc2_dcd_int_disable(rhport);
|
||||
}
|
||||
|
||||
void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
|
||||
{
|
||||
void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
|
||||
|
||||
@ -573,8 +497,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
|
||||
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
|
||||
}
|
||||
|
||||
void dcd_remote_wakeup(uint8_t rhport)
|
||||
{
|
||||
void dcd_remote_wakeup(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -592,35 +515,29 @@ void dcd_remote_wakeup(uint8_t rhport)
|
||||
dwc2->dctl &= ~DCTL_RWUSIG;
|
||||
}
|
||||
|
||||
void dcd_connect(uint8_t rhport)
|
||||
{
|
||||
void dcd_connect(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
dwc2->dctl &= ~DCTL_SDIS;
|
||||
}
|
||||
|
||||
void dcd_disconnect(uint8_t rhport)
|
||||
{
|
||||
void dcd_disconnect(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
dwc2->dctl |= DCTL_SDIS;
|
||||
}
|
||||
|
||||
// Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose!
|
||||
void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
{
|
||||
void dcd_sof_enable(uint8_t rhport, bool en) {
|
||||
(void) rhport;
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
_sof_en = en;
|
||||
|
||||
if (en)
|
||||
{
|
||||
if (en) {
|
||||
dwc2->gintsts = GINTSTS_SOF;
|
||||
dwc2->gintmsk |= GINTMSK_SOFM;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dwc2->gintmsk &= ~GINTMSK_SOFM;
|
||||
}
|
||||
}
|
||||
@ -629,8 +546,7 @@ void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
/* DCD Endpoint port
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
{
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -647,14 +563,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
|
||||
uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
|
||||
|
||||
if(dir == TUSB_DIR_OUT)
|
||||
{
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
// Calculate required size of RX FIFO
|
||||
uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
|
||||
|
||||
// If size_rx needs to be extended check if possible and if so enlarge it
|
||||
if (dwc2->grxfsiz < sz)
|
||||
{
|
||||
if (dwc2->grxfsiz < sz) {
|
||||
TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
|
||||
|
||||
// Enlarge RX FIFO
|
||||
@ -667,9 +581,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
(xfer->max_size << DOEPCTL_MPSIZ_Pos);
|
||||
|
||||
dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// "USB Data FIFOs" section in reference manual
|
||||
// Peripheral FIFO architecture
|
||||
//
|
||||
@ -696,11 +608,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
|
||||
_allocated_fifo_words_tx += fifo_size;
|
||||
|
||||
TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size*4, _dwc2_controller[rhport].ep_fifo_size-_allocated_fifo_words_tx*4);
|
||||
TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %lu", fifo_size * 4,
|
||||
_dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
|
||||
|
||||
// DIEPTXF starts at FIFO #1.
|
||||
// Both TXFD and TXSA are in unit of 32-bit words.
|
||||
dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
|
||||
dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
|
||||
(_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
|
||||
|
||||
dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
|
||||
(epnum << DIEPCTL_TXFNUM_Pos) |
|
||||
@ -715,16 +629,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
|
||||
}
|
||||
|
||||
// Close all non-control endpoints, cancel all pending transfers if any.
|
||||
void dcd_edpt_close_all (uint8_t rhport)
|
||||
{
|
||||
void dcd_edpt_close_all(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
|
||||
|
||||
// Disable non-control interrupt
|
||||
dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
|
||||
|
||||
for(uint8_t n = 1; n < ep_count; n++)
|
||||
{
|
||||
for (uint8_t n = 1; n < ep_count; n++) {
|
||||
// disable OUT endpoint
|
||||
dwc2->epout[n].doepctl = 0;
|
||||
xfer_status[n][TUSB_DIR_OUT].max_size = 0;
|
||||
@ -738,8 +650,7 @@ void dcd_edpt_close_all (uint8_t rhport)
|
||||
_allocated_fifo_words_tx = 16;
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
||||
{
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
@ -749,15 +660,12 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
||||
xfer->total_len = total_bytes;
|
||||
|
||||
// EP0 can only handle one packet
|
||||
if(epnum == 0)
|
||||
{
|
||||
if (epnum == 0) {
|
||||
ep0_pending[dir] = total_bytes;
|
||||
|
||||
// Schedule the first transaction for EP0 transfer
|
||||
edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
uint16_t num_packets = (total_bytes / xfer->max_size);
|
||||
uint16_t const short_packet_size = total_bytes % xfer->max_size;
|
||||
|
||||
@ -775,8 +683,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
||||
// bytes should be written and second to keep the return value free to give back a boolean
|
||||
// success message. If total_bytes is too big, the FIFO will copy only what is available
|
||||
// into the USB buffer!
|
||||
bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
|
||||
{
|
||||
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
|
||||
// USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
|
||||
TU_ASSERT(ff->item_size == 1);
|
||||
|
||||
@ -800,8 +707,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
|
||||
return true;
|
||||
}
|
||||
|
||||
static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
|
||||
{
|
||||
static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -809,17 +715,13 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if ( dir == TUSB_DIR_IN )
|
||||
{
|
||||
if (dir == TUSB_DIR_IN) {
|
||||
dwc2_epin_t* epin = dwc2->epin;
|
||||
|
||||
// Only disable currently enabled non-control endpoint
|
||||
if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) )
|
||||
{
|
||||
if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
|
||||
epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// Stop transmitting packets and NAK IN xfers.
|
||||
epin[epnum].diepctl |= DIEPCTL_SNAK;
|
||||
while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
|
||||
@ -834,18 +736,13 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
|
||||
// Flush the FIFO, and wait until we have confirmed it cleared.
|
||||
dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
|
||||
while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dwc2_epout_t* epout = dwc2->epout;
|
||||
|
||||
// Only disable currently enabled non-control endpoint
|
||||
if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) )
|
||||
{
|
||||
if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
|
||||
epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// Asserting GONAK is required to STALL an OUT endpoint.
|
||||
// Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
|
||||
// anyway, and it can't be cleared by user code. If this while loop never
|
||||
@ -868,8 +765,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
|
||||
/**
|
||||
* Close an endpoint.
|
||||
*/
|
||||
void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
@ -880,28 +776,23 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
|
||||
// Update max_size
|
||||
xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation
|
||||
|
||||
if (dir == TUSB_DIR_IN)
|
||||
{
|
||||
if (dir == TUSB_DIR_IN) {
|
||||
uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
|
||||
uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
|
||||
|
||||
// For now only the last opened endpoint can be closed without fuss.
|
||||
TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx,);
|
||||
_allocated_fifo_words_tx -= fifo_size;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
_out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
dcd_edpt_disable(rhport, ep_addr, true);
|
||||
}
|
||||
|
||||
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -910,13 +801,10 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
// Clear stall and reset data toggle
|
||||
if ( dir == TUSB_DIR_IN )
|
||||
{
|
||||
if (dir == TUSB_DIR_IN) {
|
||||
dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
|
||||
dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
|
||||
dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
|
||||
}
|
||||
@ -925,8 +813,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
||||
/*------------------------------------------------------------------*/
|
||||
|
||||
// Read a single data packet from receive FIFO
|
||||
static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
|
||||
{
|
||||
static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -934,16 +821,14 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
|
||||
|
||||
// Reading full available 32 bit words from fifo
|
||||
uint16_t full_words = len >> 2;
|
||||
while(full_words--)
|
||||
{
|
||||
while (full_words--) {
|
||||
tu_unaligned_write32(dst, *rx_fifo);
|
||||
dst += 4;
|
||||
}
|
||||
|
||||
// Read the remaining 1-3 bytes from fifo
|
||||
uint8_t const bytes_rem = len & 0x03;
|
||||
if ( bytes_rem != 0 )
|
||||
{
|
||||
if (bytes_rem != 0) {
|
||||
uint32_t const tmp = *rx_fifo;
|
||||
dst[0] = tu_u32_byte0(tmp);
|
||||
if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
|
||||
@ -952,8 +837,7 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
|
||||
}
|
||||
|
||||
// Write a single data packet to EPIN FIFO
|
||||
static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len)
|
||||
{
|
||||
static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
|
||||
(void) rhport;
|
||||
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
@ -961,16 +845,14 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const *
|
||||
|
||||
// Pushing full available 32 bit words to fifo
|
||||
uint16_t full_words = len >> 2;
|
||||
while(full_words--)
|
||||
{
|
||||
while (full_words--) {
|
||||
*tx_fifo = tu_unaligned_read32(src);
|
||||
src += 4;
|
||||
}
|
||||
|
||||
// Write the remaining 1-3 bytes into fifo
|
||||
uint8_t const bytes_rem = len & 0x03;
|
||||
if ( bytes_rem )
|
||||
{
|
||||
if (bytes_rem) {
|
||||
uint32_t tmp_word = src[0];
|
||||
if (bytes_rem > 1) tmp_word |= (src[1] << 8);
|
||||
if (bytes_rem > 2) tmp_word |= (src[2] << 16);
|
||||
@ -979,8 +861,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const *
|
||||
}
|
||||
}
|
||||
|
||||
static void handle_rxflvl_irq(uint8_t rhport)
|
||||
{
|
||||
static void handle_rxflvl_irq(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
volatile uint32_t const* rx_fifo = dwc2->fifo[0];
|
||||
|
||||
@ -1003,10 +884,10 @@ static void handle_rxflvl_irq(uint8_t rhport)
|
||||
// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
|
||||
//#endif
|
||||
|
||||
switch ( pktsts )
|
||||
{
|
||||
switch (pktsts) {
|
||||
// Global OUT NAK: do nothing
|
||||
case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
|
||||
case GRXSTS_PKTSTS_GLOBALOUTNAK:
|
||||
break;
|
||||
|
||||
case GRXSTS_PKTSTS_SETUPRX:
|
||||
// Setup packet received
|
||||
@ -1022,19 +903,15 @@ static void handle_rxflvl_irq(uint8_t rhport)
|
||||
epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
|
||||
break;
|
||||
|
||||
case GRXSTS_PKTSTS_OUTRX:
|
||||
{
|
||||
case GRXSTS_PKTSTS_OUTRX: {
|
||||
// Out packet received
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
|
||||
|
||||
// Read packet off RxFIFO
|
||||
if ( xfer->ff )
|
||||
{
|
||||
if (xfer->ff) {
|
||||
// Ring buffer
|
||||
tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// Linear buffer
|
||||
read_fifo_packet(rhport, xfer->buffer, bcnt);
|
||||
|
||||
@ -1043,11 +920,9 @@ static void handle_rxflvl_irq(uint8_t rhport)
|
||||
}
|
||||
|
||||
// Truncate transfer length in case of short packet
|
||||
if ( bcnt < xfer->max_size )
|
||||
{
|
||||
if (bcnt < xfer->max_size) {
|
||||
xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
|
||||
if ( epnum == 0 )
|
||||
{
|
||||
if (epnum == 0) {
|
||||
xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
|
||||
ep0_pending[TUSB_DIR_OUT] = 0;
|
||||
}
|
||||
@ -1062,12 +937,10 @@ static void handle_rxflvl_irq(uint8_t rhport)
|
||||
// XFRC complete is additionally generated when
|
||||
// - setup packet is received
|
||||
// - complete the data stage of control write is complete
|
||||
if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
|
||||
{
|
||||
if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
|
||||
uint32_t doepint = epout->doepint;
|
||||
|
||||
if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR))
|
||||
{
|
||||
if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) {
|
||||
// skip this "no-data" transfer complete event
|
||||
// Note: STPKTRX will be clear later by setup received handler
|
||||
uint32_t clear_flags = DOEPINT_XFRC;
|
||||
@ -1087,29 +960,24 @@ static void handle_rxflvl_irq(uint8_t rhport)
|
||||
}
|
||||
}
|
||||
|
||||
static void handle_epout_irq (uint8_t rhport)
|
||||
{
|
||||
static void handle_epout_irq(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
|
||||
|
||||
// DAINT for a given EP clears when DOEPINTx is cleared.
|
||||
// OEPINT will be cleared when DAINT's out bits are cleared.
|
||||
for ( uint8_t n = 0; n < ep_count; n++ )
|
||||
{
|
||||
if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) )
|
||||
{
|
||||
for (uint8_t n = 0; n < ep_count; n++) {
|
||||
if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) {
|
||||
dwc2_epout_t* epout = &dwc2->epout[n];
|
||||
|
||||
uint32_t const doepint = epout->doepint;
|
||||
|
||||
// SETUP packet Setup Phase done.
|
||||
if ( doepint & DOEPINT_STUP )
|
||||
{
|
||||
if (doepint & DOEPINT_STUP) {
|
||||
uint32_t clear_flag = DOEPINT_STUP;
|
||||
|
||||
// STPKTRX is only available for version from 3_00a
|
||||
if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
|
||||
{
|
||||
if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
|
||||
clear_flag |= DOEPINT_STPKTRX;
|
||||
}
|
||||
|
||||
@ -1118,20 +986,16 @@ static void handle_epout_irq (uint8_t rhport)
|
||||
}
|
||||
|
||||
// OUT XFER complete
|
||||
if ( epout->doepint & DOEPINT_XFRC )
|
||||
{
|
||||
if (epout->doepint & DOEPINT_XFRC) {
|
||||
epout->doepint = DOEPINT_XFRC;
|
||||
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
|
||||
|
||||
// EP0 can only handle one packet
|
||||
if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
|
||||
{
|
||||
if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
|
||||
// Schedule another packet to be received.
|
||||
edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
@ -1139,40 +1003,32 @@ static void handle_epout_irq (uint8_t rhport)
|
||||
}
|
||||
}
|
||||
|
||||
static void handle_epin_irq (uint8_t rhport)
|
||||
{
|
||||
static void handle_epin_irq(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
|
||||
dwc2_epin_t* epin = dwc2->epin;
|
||||
|
||||
// DAINT for a given EP clears when DIEPINTx is cleared.
|
||||
// IEPINT will be cleared when DAINT's out bits are cleared.
|
||||
for ( uint8_t n = 0; n < ep_count; n++ )
|
||||
{
|
||||
if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) )
|
||||
{
|
||||
for (uint8_t n = 0; n < ep_count; n++) {
|
||||
if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) {
|
||||
// IN XFER complete (entire xfer).
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
|
||||
|
||||
if ( epin[n].diepint & DIEPINT_XFRC )
|
||||
{
|
||||
if (epin[n].diepint & DIEPINT_XFRC) {
|
||||
epin[n].diepint = DIEPINT_XFRC;
|
||||
|
||||
// EP0 can only handle one packet
|
||||
if ( (n == 0) && ep0_pending[TUSB_DIR_IN] )
|
||||
{
|
||||
if ((n == 0) && ep0_pending[TUSB_DIR_IN]) {
|
||||
// Schedule another packet to be transmitted.
|
||||
edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
|
||||
// XFER FIFO empty
|
||||
if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
|
||||
{
|
||||
if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
|
||||
// diepint's TXFE bit is read-only, software cannot clear it.
|
||||
// It will only be cleared by hardware when written bytes is more than
|
||||
// - 64 bytes or
|
||||
@ -1181,8 +1037,7 @@ static void handle_epin_irq (uint8_t rhport)
|
||||
uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
|
||||
|
||||
// Process every single packet (only whole packets can be written to fifo)
|
||||
for ( uint16_t i = 0; i < remaining_packets; i++ )
|
||||
{
|
||||
for (uint16_t i = 0; i < remaining_packets; i++) {
|
||||
uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
|
||||
|
||||
// Packet can not be larger than ep max size
|
||||
@ -1193,13 +1048,10 @@ static void handle_epin_irq (uint8_t rhport)
|
||||
if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
|
||||
|
||||
// Push packet to Tx-FIFO
|
||||
if ( xfer->ff )
|
||||
{
|
||||
if (xfer->ff) {
|
||||
volatile uint32_t* tx_fifo = dwc2->fifo[n];
|
||||
tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
write_fifo_packet(rhport, n, xfer->buffer, packet_size);
|
||||
|
||||
// Increment pointer to xfer data
|
||||
@ -1208,8 +1060,7 @@ static void handle_epin_irq (uint8_t rhport)
|
||||
}
|
||||
|
||||
// Turn off TXFE if all bytes are written.
|
||||
if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
|
||||
{
|
||||
if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) {
|
||||
dwc2->diepempmsk &= ~(1 << n);
|
||||
}
|
||||
}
|
||||
@ -1217,29 +1068,24 @@ static void handle_epin_irq (uint8_t rhport)
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_int_handler(uint8_t rhport)
|
||||
{
|
||||
void dcd_int_handler(uint8_t rhport) {
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
uint32_t const int_mask = dwc2->gintmsk;
|
||||
uint32_t const int_status = dwc2->gintsts & int_mask;
|
||||
|
||||
if(int_status & GINTSTS_USBRST)
|
||||
{
|
||||
if (int_status & GINTSTS_USBRST) {
|
||||
// USBRST is start of reset.
|
||||
dwc2->gintsts = GINTSTS_USBRST;
|
||||
bus_reset(rhport);
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_ENUMDNE)
|
||||
{
|
||||
if (int_status & GINTSTS_ENUMDNE) {
|
||||
// ENUMDNE is the end of reset where speed of the link is detected
|
||||
|
||||
dwc2->gintsts = GINTSTS_ENUMDNE;
|
||||
|
||||
tusb_speed_t speed;
|
||||
switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos)
|
||||
{
|
||||
switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) {
|
||||
case DSTS_ENUMSPD_HS:
|
||||
speed = TUSB_SPEED_HIGH;
|
||||
break;
|
||||
@ -1255,17 +1101,17 @@ void dcd_int_handler(uint8_t rhport)
|
||||
break;
|
||||
}
|
||||
|
||||
// TODO must update GUSBCFG_TRDT according to link speed
|
||||
|
||||
dcd_event_bus_reset(rhport, speed, true);
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_USBSUSP)
|
||||
{
|
||||
if (int_status & GINTSTS_USBSUSP) {
|
||||
dwc2->gintsts = GINTSTS_USBSUSP;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_WKUINT)
|
||||
{
|
||||
if (int_status & GINTSTS_WKUINT) {
|
||||
dwc2->gintsts = GINTSTS_WKUINT;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||
}
|
||||
@ -1273,30 +1119,24 @@ void dcd_int_handler(uint8_t rhport)
|
||||
// TODO check GINTSTS_DISCINT for disconnect detection
|
||||
// if(int_status & GINTSTS_DISCINT)
|
||||
|
||||
if(int_status & GINTSTS_OTGINT)
|
||||
{
|
||||
if (int_status & GINTSTS_OTGINT) {
|
||||
// OTG INT bit is read-only
|
||||
uint32_t const otg_int = dwc2->gotgint;
|
||||
|
||||
if (otg_int & GOTGINT_SEDET)
|
||||
{
|
||||
if (otg_int & GOTGINT_SEDET) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
}
|
||||
|
||||
dwc2->gotgint = otg_int;
|
||||
}
|
||||
|
||||
if(int_status & GINTSTS_SOF)
|
||||
{
|
||||
if (int_status & GINTSTS_SOF) {
|
||||
dwc2->gotgint = GINTSTS_SOF;
|
||||
|
||||
if (_sof_en)
|
||||
{
|
||||
if (_sof_en) {
|
||||
uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
|
||||
dcd_event_sof(rhport, frame, true);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
// Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection
|
||||
dwc2->gintmsk &= ~GINTMSK_SOFM;
|
||||
}
|
||||
@ -1305,22 +1145,19 @@ void dcd_int_handler(uint8_t rhport)
|
||||
}
|
||||
|
||||
// RxFIFO non-empty interrupt handling.
|
||||
if(int_status & GINTSTS_RXFLVL)
|
||||
{
|
||||
if (int_status & GINTSTS_RXFLVL) {
|
||||
// RXFLVL bit is read-only
|
||||
|
||||
// Mask out RXFLVL while reading data from FIFO
|
||||
dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
|
||||
|
||||
// Loop until all available packets were handled
|
||||
do
|
||||
{
|
||||
do {
|
||||
handle_rxflvl_irq(rhport);
|
||||
} while (dwc2->gotgint & GINTSTS_RXFLVL);
|
||||
|
||||
// Manage RX FIFO size
|
||||
if (_out_ep_closed)
|
||||
{
|
||||
if (_out_ep_closed) {
|
||||
update_grxfsiz(rhport);
|
||||
|
||||
// Disable flag
|
||||
@ -1331,15 +1168,13 @@ void dcd_int_handler(uint8_t rhport)
|
||||
}
|
||||
|
||||
// OUT endpoint interrupt handling.
|
||||
if(int_status & GINTSTS_OEPINT)
|
||||
{
|
||||
if (int_status & GINTSTS_OEPINT) {
|
||||
// OEPINT is read-only, clear using DOEPINTn
|
||||
handle_epout_irq(rhport);
|
||||
}
|
||||
|
||||
// IN endpoint interrupt handling.
|
||||
if(int_status & GINTSTS_IEPINT)
|
||||
{
|
||||
if (int_status & GINTSTS_IEPINT) {
|
||||
// IEPINT bit read-only, clear using DIEPINTn
|
||||
handle_epin_irq(rhport);
|
||||
}
|
||||
|
||||
54
src/portable/synopsys/dwc2/dwc2_info.md
Normal file
54
src/portable/synopsys/dwc2/dwc2_info.md
Normal file
@ -0,0 +1,54 @@
|
||||
| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 |
|
||||
|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
|
||||
| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
|
||||
| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
|
||||
| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
|
||||
| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
|
||||
| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
|
||||
| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
|
||||
| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
|
||||
| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|
||||
| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
|
||||
| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
|
||||
| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
|
||||
| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
|
||||
| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
|
||||
| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
|
||||
| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
|
||||
| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
|
||||
| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
|
||||
| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
|
||||
| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
|
||||
| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
|
||||
| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
|
||||
| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
|
||||
| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
|
||||
| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
|
||||
| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
|
||||
| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|
||||
| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|
||||
| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|
||||
| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|
||||
| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
|
||||
| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
|
||||
| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
|
||||
158
src/portable/synopsys/dwc2/dwc2_info.py
Normal file
158
src/portable/synopsys/dwc2/dwc2_info.py
Normal file
@ -0,0 +1,158 @@
|
||||
import click
|
||||
import ctypes
|
||||
import pandas as pd
|
||||
|
||||
# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
|
||||
dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
|
||||
dwc2_reg_value = {
|
||||
'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
|
||||
'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
|
||||
'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
|
||||
'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
|
||||
'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
|
||||
'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
|
||||
'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
|
||||
'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
|
||||
'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
|
||||
'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
|
||||
'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
|
||||
'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
|
||||
'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
|
||||
'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
|
||||
'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
|
||||
}
|
||||
|
||||
# Combine dwc2_info with dwc2_reg_list
|
||||
# dwc2_info = {
|
||||
# 'BCM2711 (Pi4)': {
|
||||
# 'guid': 0x2708A000,
|
||||
# 'gsnpsid': 0x4F54280A,
|
||||
# 'ghwcfg1': 0,
|
||||
# 'ghwcfg2': 0x228DDD50,
|
||||
# 'ghwcfg3': 0xFF000E8,
|
||||
# 'ghwcfg4': 0x1FF00020
|
||||
# },
|
||||
dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
|
||||
|
||||
class GHWCFG2(ctypes.LittleEndianStructure):
|
||||
_fields_ = [
|
||||
("op_mode", ctypes.c_uint32, 3),
|
||||
("arch", ctypes.c_uint32, 2),
|
||||
("point2point", ctypes.c_uint32, 1),
|
||||
("hs_phy_type", ctypes.c_uint32, 2),
|
||||
("fs_phy_type", ctypes.c_uint32, 2),
|
||||
("num_dev_ep", ctypes.c_uint32, 4),
|
||||
("num_host_ch", ctypes.c_uint32, 4),
|
||||
("period_channel_support", ctypes.c_uint32, 1),
|
||||
("enable_dynamic_fifo", ctypes.c_uint32, 1),
|
||||
("mul_cpu_int", ctypes.c_uint32, 1),
|
||||
("reserved21", ctypes.c_uint32, 1),
|
||||
("nperiod_tx_q_depth", ctypes.c_uint32, 2),
|
||||
("host_period_tx_q_depth", ctypes.c_uint32, 2),
|
||||
("dev_token_q_depth", ctypes.c_uint32, 5),
|
||||
("otg_enable_ic_usb", ctypes.c_uint32, 1)
|
||||
]
|
||||
|
||||
|
||||
class GHWCFG3(ctypes.LittleEndianStructure):
|
||||
_fields_ = [
|
||||
("xfer_size_width", ctypes.c_uint32, 4),
|
||||
("packet_size_width", ctypes.c_uint32, 3),
|
||||
("otg_enable", ctypes.c_uint32, 1),
|
||||
("i2c_enable", ctypes.c_uint32, 1),
|
||||
("vendor_ctrl_itf", ctypes.c_uint32, 1),
|
||||
("optional_feature_removed", ctypes.c_uint32, 1),
|
||||
("synch_reset", ctypes.c_uint32, 1),
|
||||
("otg_adp_support", ctypes.c_uint32, 1),
|
||||
("otg_enable_hsic", ctypes.c_uint32, 1),
|
||||
("battery_charger_support", ctypes.c_uint32, 1),
|
||||
("lpm_mode", ctypes.c_uint32, 1),
|
||||
("total_fifo_size", ctypes.c_uint32, 16)
|
||||
]
|
||||
|
||||
|
||||
class GHWCFG4(ctypes.LittleEndianStructure):
|
||||
_fields_ = [
|
||||
("num_dev_period_in_ep", ctypes.c_uint32, 4),
|
||||
("power_optimized", ctypes.c_uint32, 1),
|
||||
("ahb_freq_min", ctypes.c_uint32, 1),
|
||||
("hibernation", ctypes.c_uint32, 1),
|
||||
("reserved7", ctypes.c_uint32, 3),
|
||||
("service_interval_mode", ctypes.c_uint32, 1),
|
||||
("ipg_isoc_en", ctypes.c_uint32, 1),
|
||||
("acg_enable", ctypes.c_uint32, 1),
|
||||
("reserved13", ctypes.c_uint32, 1),
|
||||
("utmi_phy_data_width", ctypes.c_uint32, 2),
|
||||
("dev_ctrl_ep_num", ctypes.c_uint32, 4),
|
||||
("iddg_filter_enabled", ctypes.c_uint32, 1),
|
||||
("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("a_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("b_valid_filter_enabled", ctypes.c_uint32, 1),
|
||||
("dedicated_fifos", ctypes.c_uint32, 1),
|
||||
("num_dev_in_eps", ctypes.c_uint32, 4),
|
||||
("dma_desc_enable", ctypes.c_uint32, 1),
|
||||
("dma_dynamic", ctypes.c_uint32, 1)
|
||||
]
|
||||
|
||||
|
||||
@click.group()
|
||||
def cli():
|
||||
pass
|
||||
|
||||
|
||||
@cli.command()
|
||||
@click.argument('mcus', nargs=-1)
|
||||
@click.option('-a', '--all', is_flag=True, help='Print all bit-field values')
|
||||
def info(mcus, all):
|
||||
"""Print DWC2 register values for given MCU(s)"""
|
||||
if len(mcus) == 0:
|
||||
mcus = dwc2_info
|
||||
|
||||
for mcu in mcus:
|
||||
for entry in dwc2_info:
|
||||
if mcu.lower() in entry.lower():
|
||||
print(f"## {entry}")
|
||||
for r_name, r_value in dwc2_info[entry].items():
|
||||
print(f"{r_name} = 0x{r_value:08X}")
|
||||
# Print bit-field values
|
||||
if all and r_name.upper() in globals():
|
||||
class_name = globals()[r_name.upper()]
|
||||
ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
|
||||
for field_name, field_type, _ in class_name._fields_:
|
||||
print(f" {field_name} = {getattr(ghwcfg, field_name)}")
|
||||
|
||||
|
||||
@cli.command()
|
||||
def render_md():
|
||||
"""Render dwc2_info to Markdown table"""
|
||||
# Create an empty list to hold the dictionaries
|
||||
dwc2_info_list = []
|
||||
|
||||
#Iterate over the dwc2_info dictionary and extract fields
|
||||
for device, reg_values in dwc2_info.items():
|
||||
entry_dict = {"Device": device}
|
||||
for r_name, r_value in reg_values.items():
|
||||
entry_dict[r_name] = f"0x{r_value:08X}"
|
||||
# Print bit-field values
|
||||
if r_name.upper() in globals():
|
||||
class_name = globals()[r_name.upper()]
|
||||
ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
|
||||
for field_name, field_type, _ in class_name._fields_:
|
||||
entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name)
|
||||
|
||||
dwc2_info_list.append(entry_dict)
|
||||
|
||||
# Create a Pandas DataFrame from the list of dictionaries
|
||||
df = pd.DataFrame(dwc2_info_list).set_index('Device')
|
||||
|
||||
# Transpose the DataFrame to switch rows and columns
|
||||
df = df.T
|
||||
#print(df)
|
||||
|
||||
# Write the Markdown table to a file
|
||||
with open('dwc2_info.md', 'w') as md_file:
|
||||
md_file.write(df.to_markdown())
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
cli()
|
||||
@ -24,8 +24,8 @@
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _DWC2_STM32_H_
|
||||
#define _DWC2_STM32_H_
|
||||
#ifndef DWC2_STM32_H_
|
||||
#define DWC2_STM32_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -84,20 +84,16 @@
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
|
||||
#include "stm32u5xx.h"
|
||||
// NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
|
||||
// USB_OTG_FS_BASE and OTG_FS_IRQn not defined
|
||||
#if (! defined USB_OTG_FS)
|
||||
// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
|
||||
#ifdef USB_OTG_FS
|
||||
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
|
||||
#define EP_MAX_FS 6
|
||||
#define EP_FIFO_SIZE_FS 1280
|
||||
#else
|
||||
#define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE
|
||||
#define EP_MAX_HS 9
|
||||
#define EP_FIFO_SIZE_HS 4096
|
||||
#define USB_OTG_FS_PERIPH_BASE USB_OTG_HS_BASE
|
||||
#define OTG_FS_IRQn OTG_HS_IRQn
|
||||
#else
|
||||
#define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE
|
||||
#endif
|
||||
#define EP_MAX_FS 6
|
||||
#define EP_FIFO_SIZE_FS 1280
|
||||
|
||||
#else
|
||||
#error "Unsupported MCUs"
|
||||
#endif
|
||||
@ -111,8 +107,7 @@
|
||||
|
||||
// On STM32 for consistency we associate
|
||||
// - Port0 to OTG_FS, and Port1 to OTG_HS
|
||||
static const dwc2_controller_t _dwc2_controller[] =
|
||||
{
|
||||
static const dwc2_controller_t _dwc2_controller[] = {
|
||||
#ifdef USB_OTG_FS_PERIPH_BASE
|
||||
{ .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
|
||||
#endif
|
||||
@ -129,41 +124,35 @@ static const dwc2_controller_t _dwc2_controller[] =
|
||||
// SystemCoreClock is already included by family header
|
||||
// extern uint32_t SystemCoreClock;
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void dwc2_dcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
|
||||
NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void dwc2_dcd_int_disable (uint8_t rhport)
|
||||
{
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
|
||||
NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline void dwc2_remote_wakeup_delay(void)
|
||||
{
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
|
||||
// try to delay for 1 ms
|
||||
uint32_t count = SystemCoreClock / 1000;
|
||||
while (count--) __NOP();
|
||||
}
|
||||
|
||||
// MCU specific PHY init, called BEFORE core reset
|
||||
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
{
|
||||
if ( hs_phy_type == HS_PHY_TYPE_NONE )
|
||||
{
|
||||
// - dwc2 3.30a (H5) use USB_HS_PHYC
|
||||
// - dwc2 4.11a (U5) use femtoPHY
|
||||
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
if (hs_phy_type == HS_PHY_TYPE_NONE) {
|
||||
// Enable on-chip FS PHY
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
|
||||
}else
|
||||
{
|
||||
// Disable FS PHY
|
||||
} else {
|
||||
#if CFG_TUSB_MCU != OPT_MCU_STM32U5
|
||||
// Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
|
||||
dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
|
||||
#endif
|
||||
|
||||
// Enable on-chip HS PHY
|
||||
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI)
|
||||
{
|
||||
if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
|
||||
#ifdef USB_HS_PHYC
|
||||
// Enable UTMI HS PHY
|
||||
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
|
||||
@ -196,40 +185,47 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
|
||||
// Enable PLL internal PHY
|
||||
USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
|
||||
#else
|
||||
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// MCU specific PHY update, it is called AFTER init() and core reset
|
||||
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
{
|
||||
static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
|
||||
// used to set turnaround time for fullspeed, nothing to do in highspeed mode
|
||||
if ( hs_phy_type == HS_PHY_TYPE_NONE )
|
||||
{
|
||||
if (hs_phy_type == HS_PHY_TYPE_NONE) {
|
||||
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
|
||||
uint32_t turnaround;
|
||||
|
||||
if ( SystemCoreClock >= 32000000u )
|
||||
if (SystemCoreClock >= 32000000u) {
|
||||
turnaround = 0x6u;
|
||||
else if ( SystemCoreClock >= 27500000u )
|
||||
} else if (SystemCoreClock >= 27500000u) {
|
||||
turnaround = 0x7u;
|
||||
else if ( SystemCoreClock >= 24000000u )
|
||||
} else if (SystemCoreClock >= 24000000u) {
|
||||
turnaround = 0x8u;
|
||||
else if ( SystemCoreClock >= 21800000u )
|
||||
} else if (SystemCoreClock >= 21800000u) {
|
||||
turnaround = 0x9u;
|
||||
else if ( SystemCoreClock >= 20000000u )
|
||||
}
|
||||
else if (SystemCoreClock >= 20000000u) {
|
||||
turnaround = 0xAu;
|
||||
else if ( SystemCoreClock >= 18500000u )
|
||||
}
|
||||
else if (SystemCoreClock >= 18500000u) {
|
||||
turnaround = 0xBu;
|
||||
else if ( SystemCoreClock >= 17200000u )
|
||||
}
|
||||
else if (SystemCoreClock >= 17200000u) {
|
||||
turnaround = 0xCu;
|
||||
else if ( SystemCoreClock >= 16000000u )
|
||||
}
|
||||
else if (SystemCoreClock >= 16000000u) {
|
||||
turnaround = 0xDu;
|
||||
else if ( SystemCoreClock >= 15000000u )
|
||||
}
|
||||
else if (SystemCoreClock >= 15000000u) {
|
||||
turnaround = 0xEu;
|
||||
else
|
||||
}
|
||||
else {
|
||||
turnaround = 0xFu;
|
||||
}
|
||||
|
||||
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
|
||||
}
|
||||
@ -239,4 +235,4 @@ static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DWC2_STM32_H_ */
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -174,7 +174,7 @@
|
||||
// NXP LPC MCX
|
||||
#define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series
|
||||
|
||||
// Helper to check if configured MCU is one of listed
|
||||
// Check if configured MCU is one of listed
|
||||
// Apply _TU_CHECK_MCU with || as separator to list of input
|
||||
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
|
||||
#define TU_CHECK_MCU(...) (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
|
||||
|
||||
@ -108,7 +108,7 @@ deps_optional = {
|
||||
'd922865fc0326a102c26211c44b8e42f52c1e53d',
|
||||
'stm32l5'],
|
||||
'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git',
|
||||
'bc00f3c9d8a4e25220f84c26d414902cc6bdf566',
|
||||
'06d7edade7167b0eafdd550bf77cfc4fa98eae2e',
|
||||
'stm32u5'],
|
||||
'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git',
|
||||
'9c5d1920dd9fabbe2548e10561d63db829bb744f',
|
||||
@ -153,7 +153,7 @@ deps_optional = {
|
||||
'675c32a75df37f39d50d61f51cb0dcf53f07e1cb',
|
||||
'stm32l5'],
|
||||
'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git',
|
||||
'2e1d4cdb386e33391cb261dfff4fefa92e4aa35a',
|
||||
'4d93097a67928e9377e655ddd14622adc31b9770',
|
||||
'stm32u5'],
|
||||
'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git',
|
||||
'2c5f06638be516c1b772f768456ba637f077bac8',
|
||||
@ -181,6 +181,10 @@ deps_all = {**deps_mandatory, **deps_optional}
|
||||
TOP = Path(__file__).parent.parent.resolve()
|
||||
|
||||
|
||||
def run_cmd(cmd):
|
||||
return subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
|
||||
|
||||
def get_a_dep(d):
|
||||
if d not in deps_all.keys():
|
||||
print('{} is not found in dependency list')
|
||||
@ -189,25 +193,24 @@ def get_a_dep(d):
|
||||
commit = deps_all[d][1]
|
||||
families = deps_all[d][2]
|
||||
|
||||
print('cloning {} with {}'.format(d, url))
|
||||
print(f'cloning {d} with {url}')
|
||||
|
||||
p = Path(TOP / d)
|
||||
git_cmd = "git -C {}".format(p)
|
||||
git_cmd = f"git -C {p}"
|
||||
|
||||
# Init git deps if not existed
|
||||
if not p.exists():
|
||||
p.mkdir(parents=True)
|
||||
subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
run_cmd(f"git -C {p} init")
|
||||
run_cmd(f"git -C {p} remote add origin {url}")
|
||||
|
||||
# Check if commit is already fetched
|
||||
result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
result = run_cmd(f"git -C {p} rev-parse HEAD")
|
||||
head = result.stdout.decode("utf-8").splitlines()[0]
|
||||
|
||||
run_cmd(f"git -C {p} reset --hard")
|
||||
if commit != head:
|
||||
subprocess.run("{} reset --hard".format(git_cmd, commit), shell=True)
|
||||
subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True)
|
||||
subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
run_cmd(f"git -C {p} fetch --depth 1 origin {commit}")
|
||||
run_cmd(f"git -C {p} checkout FETCH_HEAD")
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user